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Hi,
I want to make my own design, by adding some hardware into the WARPlab 6.3 reference design. First I'm trying to understand all necessary steps to compile a new XPS and SDK project. To practice this I simply did the following steps:
1. I downloaded the w2_warplab_buffers.mdl file, did not change ANYTHING to it and then generated a core of it with a new version number 1.01.a instead of 1.00.a.
2. Then I simply copied the generated pcore folder "w2_warplab_buffers_plbw_v1_01_a" out of netlist folder and put in the pcores folder of the reference design.
3. Then I opened up XPS and chanded the HW_VER parameter to 1.01.a of the warplab_buffers_plbw_0 instance.
4. I changed nothing else and generated the bitstream. It took about an hour, but there were no errors.
5. Then I exported to SDK and made a new board support package, according to the steps suggested in this thread: (http://warp.rice.edu/forums/viewtopic.php?id=1727)
chrishunter wrote:
1) First, make sure to add the XPS project directory (the one with the system.xmp file) to your local repositories in the SDK. To do this, click the "Xilinx Tools" menu item and then "Repositories." The "edk_user_repository" from your SVN checkout should be in the "Global Repositories" field and your XPS project should be in the "Local Repositories" field.
2) Add a new Xilinx Board Support Package to your SDK project. When the "New Board Support Package Project" window pops up, give it a name like warplab_bsp and then make sure that "standalone" is selected for the OS.
3) Next, the "Board Support Package Settings" will pop up.
4) Check the box next to the WARP_HW_VER library and click the version number next to it. If you are using v2 hardware, select the 2.20a version. This selection box allows the C code for WARPLab to implement the different calls needed to configure the three generations of WARP hardware.
5) Check the box next to WARPxilnet and select the latest version (3.00a).
6) Click OK. The BSP will start to build. However, there will be an error because WARPxilnet has not yet been configured to point to a particular Ethernet MAC instance.
7) Right-click on the bsp you created in "Project Explorer" and select "Board Support Package Settings." Click on the WARPxilnet item in the left side of the overview window. You'll see that the emac_instname parameter currently is set to "none." Click "none" and you should see a new selection box that will let you choose the "TriMode_MAC_GMII" if you are using WARP v2. Select that and then hit OK.
The BSP should then compile. Let me know if there are any other problems with the compilation and we can work through it.
6. Then I imported the "w2_WARPLab_v6p3_2rf" C project that was already in the workspace. But here I get a problem. I doesn't recognise very important functions:
Errors wrote:
../src/warplab.c:478: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXDELAY' undeclared (first use in this function)
../src/warplab.c:478: error: (Each undeclared identifier is reported only once
../src/warplab.c:478: error: for each function it appears in.)
../src/warplab.c:479: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_STARTCAPTURE' undeclared (first use in this function)
../src/warplab.c:480: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXLENGTH' undeclared (first use in this function)
../src/warplab.c:481: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TRANSMODE' undeclared (first use in this function)
../src/warplab.c:482: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RADIO2TXBUFF_TXEN' undeclared (first use in this function)
../src/warplab.c:483: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RADIO3TXBUFF_TXEN' undeclared (first use in this function)
../src/warplab.c:484: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RADIO2RXBUFF_RXEN' undeclared (first use in this function)
../src/warplab.c:485: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RADIO3RXBUFF_RXEN' undeclared (first use in this function)
../src/warplab.c:486: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_RADIO1_AGC_EN' undeclared (first use in this function)
../src/warplab.c:487: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_RADIO2_AGC_EN' undeclared (first use in this function)
../src/warplab.c:488: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_RADIO3_AGC_EN' undeclared (first use in this function)
../src/warplab.c:489: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_RADIO4_AGC_EN' undeclared (first use in this function)
../src/warplab.c:490: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_AGC_TRIGGER_DELAY' undeclared (first use in this function)
../src/warplab.c:491: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_MGC_AGC_SEL' undeclared (first use in this function)
../src/warplab.c:492: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_AGC_EN' undeclared (first use in this function)
../src/warplab.c:1076: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO2' undeclared (first use in this function)
../src/warplab.c:1101: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO3' undeclared (first use in this function)
../src/warplab.c:1150: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO2' undeclared (first use in this function)
../src/warplab.c:1178: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO3' undeclared (first use in this function)
../src/warplab.c:1240: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO2' undeclared (first use in this function)
../src/warplab.c:1269: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO3' undeclared (first use in this function)
../src/warplab.c:1419: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_CAPTUREDONE' undeclared (first use in this function)
../src/warplab.c:1458: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_STARTTX' undeclared (first use in this function)
../src/warplab.c:1469: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_STOPTX' undeclared (first use in this function)
../src/warplab.c:1480: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_STARTTXRX' undeclared (first use in this function)
../src/warplab.c:1492: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_AGCDONEADDR' undeclared (first use in this function)
../src/warplab.c:1514: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RADIO2AGCDONERSSI' undeclared (first use in this function)
../src/warplab.c:1524: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RADIO3AGCDONERSSI' undeclared (first use in this function)
../src/warplab.c:1566: error: 'XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_DCO_EN_SEL' undeclared (first use in this function)
../src/warplab.c:1579: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_THRESHOLDS' undeclared (first use in this function)
../src/warplab.c: In function 'warplab_AGC_Reset':
../src/warplab.c:1747: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_SRESET_IN' undeclared (first use in this function)
../src/warplab.c: In function 'warplab_AGC_MasterReset':
../src/warplab.c:1759: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_AGC_EN' undeclared (first use in this function)
../src/warplab.c:1761: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_MRESET_IN' undeclared (first use in this function)
../src/warplab.c: In function 'warplab_AGC_Start':
../src/warplab.c:1775: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_PACKET_IN' undeclared (first use in this function)
../src/warplab.c: In function 'warplab_AGC_Initialize':
../src/warplab.c:1790: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_AGC_EN' undeclared (first use in this function)
../src/warplab.c:1791: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_SRESET_IN' undeclared (first use in this function)
../src/warplab.c:1792: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_MRESET_IN' undeclared (first use in this function)
../src/warplab.c:1795: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_ADJ' undeclared (first use in this function)
../src/warplab.c:1798: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_DCO_TIMING' undeclared (first use in this function)
../src/warplab.c:1801: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GBB_INIT' undeclared (first use in this function)
../src/warplab.c:1804: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_THRESHOLDS' undeclared (first use in this function)
../src/warplab.c:1807: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_TIMING' undeclared (first use in this function)
../src/warplab.c:1810: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_AVG_LEN' undeclared (first use in this function)
../src/warplab.c:1813: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_BITS' undeclared (first use in this function)
../src/warplab.c: In function 'warplab_AGC_setNoiseEstimate':
../src/warplab.c:1834: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GBB_INIT' undeclared (first use in this function)
../src/warplab.c: In function 'warplab_AGC_GetGains':
../src/warplab.c:1844: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GBB_A' undeclared (first use in this function)
../src/warplab.c:1845: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GRF_A' undeclared (first use in this function)
../src/warplab.c:1847: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GBB_B' undeclared (first use in this function)
../src/warplab.c:1848: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GRF_B' undeclared (first use in this function)
../src/warplab.c:1850: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GBB_C' undeclared (first use in this function)
../src/warplab.c:1851: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GRF_C' undeclared (first use in this function)
../src/warplab.c:1853: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GBB_D' undeclared (first use in this function)
../src/warplab.c:1854: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GRF_D' undeclared (first use in this function)
../src/warplab.c: In function 'warplab_AGC_SetTarget':
../src/warplab.c:1874: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_T_DB' undeclared (first use in this function)
../src/warplab.c: In function 'warplab_AGC_SetDCO':
../src/warplab.c:1884: error: 'XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_BITS' undeclared (first use in this function)
make: *** [src/warplab.o] Error 1
So I guess there's still a step I am missing. Because it misses some important basic functions and it also seems to miss almost every function that has AGC in its name.
Do you know what I still need to do?
I've uploaded my XPS and SDK project here: https://www.dropbox.com/s/5q1nygb38pwln … eter_W.zip .
Last edited by Pieter_W (2013-Feb-05 08:44:43)
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All of those XPAR_ names are defined in an automatically-generated file called xparameters.h. It should be automatically included and available to your software project after building the BSP. When you followed my earlier steps for building the BSP, did the SDK successfully compile the code after you clicked "OK" in the pop-up? If it failed to compile, I think that would explain why you are seeing all the errors in warplab.c
One way to check if the BSP actually built correctly is to look at the icon for it in the Project Explorer on the left. If there is a little red X over the bsp's icon then there was a compilation error. There should be a little red X over your warplab software project since it also failed to compile.
If the BSP did not compile, we need to see what error messages it produced. The Console view at the bottom of the screen (where I assume you copied those error messages from) is actually used for the output of both the warplab software compilation and the output of the bsp software compilation. If you single-click and highlight the bsp project on the Project Explorer on the left, the console should switch over to showing you the output of that build. If there are error messages there, what are they?
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I deleted my BSP and made it again, but there were no errors. This is all it says
make -k all
libgen -hw ../EDK_Project_hw_platform/system.xml\
-lp .. -lp D:/Dropbox/2_Thesis/WARP_Repository/WARP/edk_user_repository\
-pe ppc405_0 \
-log libgen.log \
system.mss
libgen
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: libgen -hw ../EDK_Project_hw_platform/system.xml -lp .. -lp
D:/Dropbox/2_Thesis/WARP_Repository/WARP/edk_user_repository -pe ppc405_0 -log
libgen.log system.mss
Staging source files.
Running DRCs.
XilNet DRC ...
Running generate.
Running post_generate.
Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
"Compiling common"
powerpc-eabi-ar: creating ../../../lib/libxil.a
"Compiling llfifo"
"Compiling lldma"
"Compiling standalone"
"Compiling EEPROM"
"Compiling radio_controller"
"Compiling uartlite"
"Compiling lltemac"
"Compiling llfifo"
"Compiling warp_v4_userio"
"Compiling bram"
"Compiling dmacentral"
"Compiling gpio"
"Compiling tmrctr"
"Compiling cpu_ppc405"
Running execs_generate.
'Finished building libraries'
I also right-clicked on the "w2_WARPLab_v6p3_2rf" C project and changed the BSP reference to my new BSP, but nothing changed.
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Did you change the name of the instantiated pcore? Then instead of, e.g. XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GBB_A, an entry named XPAR_NEWNAMEOFPCORE_0_MEMMAP_GBB_A can be found in xparameters.h.
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Can you open up the Board Support Package Settings by right-clicking on the bsp? Click on "drivers" on the left under "Overview." What driver is listed for warplab_buffers?
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chrishunter wrote:
Can you open up the Board Support Package Settings by right-clicking on the bsp? Click on "drivers" on the left under "Overview." What driver is listed for warplab_buffers?
It says "Generic - 1.00.a". This means there is probably something wrong with the versioning right?
I've found this thread saying something about versioning, but, like i replied in that thread, I was not able to find those files mentioned. So I didn't do anything, besides copying the pcore folder.
http://warp.rice.edu/forums/viewtopic.p … 7343#p7343
(Its about OFDM.)
-Make changes to ofdm_txrx_supermimo.mdl
-Increment the netlist folder name (./phy_netlist_v10 to _v11, for example)
-Open the EDK export settings and increment the pcore version number (from 3.00.e to 3.00.f, for example)
-Export the updated pcore
-Create a mdlsrc folder in the new pcore folder (pcores/ofdm_txrx_supermimo_v3_00_f/mdlsrc)
-Manually copy the .mdl, .m, .v and .cdc (from the netlist folder) files to the mdlsrc folder
-Copy the new pcore folder to the XPS project pcores folder
-Update the MHS file HW_VER parameter with the new pcore version
However in XPS the shown IP version of the warplab_buffer core states 1.01.a under Bus Interfaces.
Last edited by Pieter_W (2013-Feb-05 09:47:00)
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christian wrote:
Did you change the name of the instantiated pcore? Then instead of, e.g. XPAR_WARPLAB_AGC_PLBW_0_MEMMAP_GBB_A, an entry named XPAR_NEWNAMEOFPCORE_0_MEMMAP_GBB_A can be found in xparameters.h.
I did not change the name or anything. I only generated it again out of simulink with a newer version number.
Here's what's in my xparameters.h. There's nothing there that resembles it.
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.2 EDK_P.28xd
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
*
* Description: Driver parameters
*
*******************************************************************/
#define STDIN_BASEADDRESS 0x84020000
#define STDOUT_BASEADDRESS 0x84020000
/******************************************************************/
/* Definitions for driver EEPROM_ONEWIRE */
#define XPAR_EEPROM_ONEWIRE_NUM_INSTANCES 1
/* Definitions for peripheral EEPROM_CONTROLLER */
#define XPAR_EEPROM_CONTROLLER_DEVICE_ID 0
#define XPAR_EEPROM_CONTROLLER_MEM0_BASEADDR 0xC5400000
#define XPAR_EEPROM_CONTROLLER_MEM0_HIGHADDR 0xC540FFFF
/******************************************************************/
/* Definitions for peripheral PLBV46_PLBV46_BRIDGE_0 */
#define XPAR_PLBV46_PLBV46_BRIDGE_0_BRIDGE_BASEADDR 0x86200000
#define XPAR_PLBV46_PLBV46_BRIDGE_0_BRIDGE_HIGHADDR 0x8620FFFF
#define XPAR_PLBV46_PLBV46_BRIDGE_0_RNG0_BASEADDR 0xC6000000
#define XPAR_PLBV46_PLBV46_BRIDGE_0_RNG0_HIGHADDR 0xC600FFFF
#define XPAR_PLBV46_PLBV46_BRIDGE_0_RNG1_BASEADDR 0xCAC00000
#define XPAR_PLBV46_PLBV46_BRIDGE_0_RNG1_HIGHADDR 0xCAC0FFFF
/* Definitions for peripheral PPC405_0_DOCM_CNTLR */
#define XPAR_PPC405_0_DOCM_CNTLR_BASEADDR 0x40110000
#define XPAR_PPC405_0_DOCM_CNTLR_HIGHADDR 0x4011FFFF
/* Definitions for peripheral PPC405_0_IOCM_CNTLR */
#define XPAR_PPC405_0_IOCM_CNTLR_BASEADDR 0xFFFF0000
#define XPAR_PPC405_0_IOCM_CNTLR_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral WARPLAB_AGC_PLBW_0 */
#define XPAR_WARPLAB_AGC_PLBW_0_BASEADDR 0xC6000000
#define XPAR_WARPLAB_AGC_PLBW_0_HIGHADDR 0xC600FFFF
/* Definitions for peripheral WARPLAB_BUFFERS_PLBW_0 */
#define XPAR_WARPLAB_BUFFERS_PLBW_0_BASEADDR 0x83800000
#define XPAR_WARPLAB_BUFFERS_PLBW_0_HIGHADDR 0x83BFFFFF
/******************************************************************/
/* Definitions for driver RADIO_CONTROLLER */
#define XPAR_RADIO_CONTROLLER_NUM_INSTANCES 1
/* Definitions for peripheral RADIO_CONTROLLER_0 */
#define XPAR_RADIO_CONTROLLER_0_DEVICE_ID 0
#define XPAR_RADIO_CONTROLLER_0_BASEADDR 0xCAC00000
#define XPAR_RADIO_CONTROLLER_0_HIGHADDR 0xCAC0FFFF
/******************************************************************/
/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 2
/* Definitions for peripheral RS232_DB9 */
#define XPAR_RS232_DB9_BASEADDR 0x84020000
#define XPAR_RS232_DB9_HIGHADDR 0x8402FFFF
#define XPAR_RS232_DB9_DEVICE_ID 0
#define XPAR_RS232_DB9_BAUDRATE 57600
#define XPAR_RS232_DB9_USE_PARITY 0
#define XPAR_RS232_DB9_ODD_PARITY 0
#define XPAR_RS232_DB9_DATA_BITS 8
/* Definitions for peripheral RS232_USB */
#define XPAR_RS232_USB_BASEADDR 0x84000000
#define XPAR_RS232_USB_HIGHADDR 0x8400FFFF
#define XPAR_RS232_USB_DEVICE_ID 1
#define XPAR_RS232_USB_BAUDRATE 57600
#define XPAR_RS232_USB_USE_PARITY 0
#define XPAR_RS232_USB_ODD_PARITY 0
#define XPAR_RS232_USB_DATA_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral RS232_DB9 */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DB9_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x84020000
#define XPAR_UARTLITE_0_HIGHADDR 0x8402FFFF
#define XPAR_UARTLITE_0_BAUDRATE 57600
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN 8
/* Canonical definitions for peripheral RS232_USB */
#define XPAR_UARTLITE_1_DEVICE_ID XPAR_RS232_USB_DEVICE_ID
#define XPAR_UARTLITE_1_BASEADDR 0x84000000
#define XPAR_UARTLITE_1_HIGHADDR 0x8400FFFF
#define XPAR_UARTLITE_1_BAUDRATE 57600
#define XPAR_UARTLITE_1_USE_PARITY 0
#define XPAR_UARTLITE_1_ODD_PARITY 0
#define XPAR_UARTLITE_1_DATA_BITS 8
#define XPAR_UARTLITE_1_SIO_CHAN -1
/******************************************************************/
/* Definitions for driver LLTEMAC */
#define XPAR_XLLTEMAC_NUM_INSTANCES 1
/* Definitions for peripheral TRIMODE_MAC_GMII Channel 0 */
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_DEVICE_ID 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_BASEADDR 0x87000000
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_HIGHADDR 0x8707ffff
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_TXCSUM 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_RXCSUM 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_PHY_TYPE 1
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_TXVLAN_TRAN 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_RXVLAN_TRAN 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_TXVLAN_TAG 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_RXVLAN_TAG 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_TXVLAN_STRP 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_RXVLAN_STRP 0
#define XPAR_TRIMODE_MAC_GMII_CHAN_0_MCAST_EXTEND 0
/* Canonical definitions for peripheral TRIMODE_MAC_GMII Channel 0 */
#define XPAR_LLTEMAC_0_DEVICE_ID 0
#define XPAR_LLTEMAC_0_BASEADDR 0x87000000
#define XPAR_LLTEMAC_0_HIGHADDR 0x8707ffff
#define XPAR_LLTEMAC_0_TXCSUM 0
#define XPAR_LLTEMAC_0_RXCSUM 0
#define XPAR_LLTEMAC_0_PHY_TYPE 1
#define XPAR_LLTEMAC_0_TXVLAN_TRAN 0
#define XPAR_LLTEMAC_0_RXVLAN_TRAN 0
#define XPAR_LLTEMAC_0_TXVLAN_TAG 0
#define XPAR_LLTEMAC_0_RXVLAN_TAG 0
#define XPAR_LLTEMAC_0_TXVLAN_STRP 0
#define XPAR_LLTEMAC_0_RXVLAN_STRP 0
#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
#define XPAR_LLTEMAC_0_INTR 0xFF
/* LocalLink TYPE Enumerations */
#define XPAR_LL_FIFO 1
#define XPAR_LL_DMA 2
/* Canonical LocalLink parameters for TRIMODE_MAC_GMII */
#define XPAR_LLTEMAC_0_LLINK_CONNECTED_TYPE XPAR_LL_FIFO
#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x81a00000
#define XPAR_LLTEMAC_0_LLINK_CONNECTED_FIFO_INTR 0xFF
#define XPAR_LLTEMAC_0_LLINK_CONNECTED_DMARX_INTR 0xFF
#define XPAR_LLTEMAC_0_LLINK_CONNECTED_DMATX_INTR 0xFF
/******************************************************************/
/* Definitions for driver LLFIFO */
#define XPAR_XLLFIFO_NUM_INSTANCES 1
/* Definitions for peripheral TRIMODE_MAC_GMII_FIFO */
#define XPAR_TRIMODE_MAC_GMII_FIFO_DEVICE_ID 0
#define XPAR_TRIMODE_MAC_GMII_FIFO_BASEADDR 0x81A00000
#define XPAR_TRIMODE_MAC_GMII_FIFO_HIGHADDR 0x81A0FFFF
/******************************************************************/
/* Canonical definitions for peripheral TRIMODE_MAC_GMII_FIFO */
#define XPAR_LLFIFO_0_DEVICE_ID XPAR_TRIMODE_MAC_GMII_FIFO_DEVICE_ID
#define XPAR_LLFIFO_0_BASEADDR 0x81A00000
#define XPAR_LLFIFO_0_HIGHADDR 0x81A0FFFF
/******************************************************************/
/* Definitions for driver WARP_V4_USERIO */
#define XPAR_WARP_V4_USERIO_NUM_INSTANCES 1
/* Definitions for peripheral USERIO */
#define XPAR_USERIO_DEVICE_ID 0
#define XPAR_USERIO_BASEADDR 0xC9600000
#define XPAR_USERIO_HIGHADDR 0xC960FFFF
/******************************************************************/
/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 1
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_1 */
#define XPAR_XPS_BRAM_IF_CNTLR_1_DEVICE_ID 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_DATA_WIDTH 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_ECC 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_FAULT_INJECT 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_CE_FAILING_REGISTERS 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_UE_FAILING_REGISTERS 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_ECC_STATUS_REGISTERS 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_CE_COUNTER_WIDTH 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_ECC_ONOFF_REGISTER 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_ECC_ONOFF_RESET_VALUE 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_WRITE_ACCESS 0
#define XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
#define XPAR_XPS_BRAM_IF_CNTLR_1_HIGHADDR 0x0000FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_BRAM_IF_CNTLR_1 */
#define XPAR_BRAM_0_DEVICE_ID XPAR_XPS_BRAM_IF_CNTLR_1_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 0
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_BRAM_0_WRITE_ACCESS 0
#define XPAR_BRAM_0_BASEADDR 0x00000000
#define XPAR_BRAM_0_HIGHADDR 0x0000FFFF
/******************************************************************/
/* Definitions for driver DMACENTRAL */
#define XPAR_XDMACENTRAL_NUM_INSTANCES 1
/* Definitions for peripheral XPS_CENTRAL_DMA_0 */
#define XPAR_XPS_CENTRAL_DMA_0_DEVICE_ID 0
#define XPAR_XPS_CENTRAL_DMA_0_BASEADDR 0x80200000
#define XPAR_XPS_CENTRAL_DMA_0_HIGHADDR 0x8020FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_CENTRAL_DMA_0 */
#define XPAR_DMACENTRAL_0_DEVICE_ID XPAR_XPS_CENTRAL_DMA_0_DEVICE_ID
#define XPAR_DMACENTRAL_0_BASEADDR 0x80200000
#define XPAR_DMACENTRAL_0_HIGHADDR 0x8020FFFF
/******************************************************************/
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 1
/* Definitions for peripheral XPS_GPIO_0 */
#define XPAR_XPS_GPIO_0_BASEADDR 0x81400000
#define XPAR_XPS_GPIO_0_HIGHADDR 0x8140FFFF
#define XPAR_XPS_GPIO_0_DEVICE_ID 0
#define XPAR_XPS_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_XPS_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1
/* Definitions for peripheral XPS_TIMER_0 */
#define XPAR_XPS_TIMER_0_DEVICE_ID 0
#define XPAR_XPS_TIMER_0_BASEADDR 0x83C00000
#define XPAR_XPS_TIMER_0_HIGHADDR 0x83C0FFFF
#define XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ 80000000
/******************************************************************/
/* Canonical definitions for peripheral XPS_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_0_DEVICE_ID
#define XPAR_TMRCTR_0_BASEADDR 0x83C00000
#define XPAR_TMRCTR_0_HIGHADDR 0x83C0FFFF
#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ
/******************************************************************/
/* Definition for PPC cacheable regions */
#define XPAR_CACHEABLE_REGION_MASK 0x80800001
/******************************************************************/
/* Definitions for bus frequencies */
#define XPAR_CPU_PPC405_DPLB0_FREQ_HZ 80000000
#define XPAR_CPU_PPC405_IPLB0_FREQ_HZ 80000000
/******************************************************************/
/* Canonical definitions for bus frequencies */
#define XPAR_PROC_BUS_0_FREQ_HZ 80000000
/******************************************************************/
#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 160000000
#define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 160000000
/******************************************************************/
#define XPAR_CPU_ID 0
#define XPAR_PPC405_VIRTEX4_ID 0
#define XPAR_PPC405_VIRTEX4_DPLB0_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB0_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB0_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB0_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB1_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_IPLB1_NATIVE_DWIDTH 64
#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_BASE 0xffffffff
#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_HIGH 0x00000000
#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_BASE 0xffffffff
#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_HIGH 0x00000000
#define XPAR_PPC405_VIRTEX4_FASTEST_PLB_CLOCK DPLB0
#define XPAR_PPC405_VIRTEX4_GENERATE_PLB_TIMESPECS 1
#define XPAR_PPC405_VIRTEX4_DPLB0_P2P 0
#define XPAR_PPC405_VIRTEX4_DPLB1_P2P 1
#define XPAR_PPC405_VIRTEX4_IPLB0_P2P 0
#define XPAR_PPC405_VIRTEX4_IPLB1_P2P 1
#define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100
#define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x000001FF
#define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1
#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1
#define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0
#define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1
#define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000
#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011
#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011
#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000
#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000
#define XPAR_PPC405_VIRTEX4_HW_VER "2.01.b"
/******************************************************************/
Last edited by Pieter_W (2013-Feb-05 09:43:56)
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If you are getting a generic driver instead of the actual w2_warplab_buffers_plbw driver, then the SDK isn't seeing a local repository for your XPS project (step 1 from my list of steps you quoted in your first post)
Pieter_W wrote:
Command Line: libgen -hw ../EDK_Project_hw_platform/system.xml -lp .. -lp
D:/Dropbox/2_Thesis/WARP_Repository/WARP/edk_user_repository -pe ppc405_0 -log
libgen.log system.mss
This line also looks like it doesn't have the XPS project in the repository path. Did you perhaps add the SDK_Workspace subfolder to the local repository path instead of the folder that contains the .xmp? You have to add the XPS project folder (the parent to the SDK_Workspace folder) to the local repository.
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Oh my god, yes indeed, I added the workspace instead of the project folder. That's a stupid mistake. I'm sorry for wasting your time like this. I was hoping it would be another kind of error. Thanks a lot.
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No problem. I'm glad it's working now.
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Hi, so have a new problem now. There still seems to be something missing or wrong. THe code now completely compiles and i can put it on the FPGA. Also when I open Putty I can see this coming up:
Configuring network
... initializing DMA
... ... complete!
... initializing Ethernet
... ... complete!
... complete!
IP Address: 10.0.0.1
Listening on UDP port 9000.
WARPLabv06_3 2RF Started - Waiting for connection from MATLAB
So that seems to be working just fine. I also see the "01" on the board.
However, when I try to run a MatLab script I get the "No Ack Received - Connection Timed out". Weird.
Here's what I've already tried:
-I've tried uploading my previous compilation of just the standard warplab 6.3 reference design. There I get the same output and I can run my scripts. So my cable connections and network configurations of my laptop should be just fine.
-I've already just tried pinging to "10.0.0.1" in cmd, but it times out as well.
-I've also run the " warplab_networkCheck(1)" command in matlab, which returns this:
checking set up of computer network interfaces... ok
checking installation of pnet... ok
checking configuration of Node 1...
No ACK received - Connection has timed out.
----Error! node not responding to commands
Results Summary:
Node | S/N |HWGEN|WLVER|RADIO| ACK | SYNC
-----------------------------------------
1| | | | | FAIL| FAIL
ans =
-1
Btw, I use a script of my own, that I made starting from a simple_streaming example m-file. Because I only have 1 WARP board so I use 1 Radio daughterboard for sending and 1 for receiving. But the m-file works just fine with the standard reference design.
What else could possibly be wrong?
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Pieter_W wrote:
-I've already just tried pinging to "10.0.0.1" in cmd, but it times out as well.
If pinging fails, then all bets are off on anything else working. One thing to check: we made the jump from 100Mbps Ethernet to 1Gbps Ethernet for WARP v2 in WARPLab 6.0 and later. If you are using an old 100Mbps switch, that could be a reason that you aren't able to reach the board. You'll need to use a 1Gbps switch to make this design work.
Alternatively, if you only have access to a 100Mbps switch, it's just a simple C-code change to roll back to 100Mbps support in WARPLab. On line 115 of warplab.c, there is a #define for ENET_LINK_SPEED. Just change that from 1000 to 100.
If it isn't an Ethernet speed problem, the next thing to check is your routing table on your PC. Is the Ethernet interface you are using set on the 10.0.0.X subnet that the WARPLab design expects?
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I'm not using a switch, since I'm using only 1 board.
I've set my IP address to 10.0.0.200 and subnet 255.255.255.0. But I know this cant the be the problem, because my conlaptop configuration works with the standard reference design. The only difference is the design I upload to the FPGA.
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hmm, if that's the case then it should be working. Have you tried regenerating the linker script before programming the board?
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Yes, i have.
I chose the iocm for the code sections, the docm for the data sections and i didnt change anything for the heap and stack. That's all, right?
Last edited by Pieter_W (2013-Feb-05 13:47:06)
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Yeah, that should be fine. Can you post your full MSS file? To get to it, click the "+" next to the bsp in the "Project Explorer" and then double-click on the system.mss file. Then, at the bottom of the screen should should see two tabs: Overview and Source. Overview is the pretty visualization of your MSS, but it isn't something you can paste here. Click on "Source" and then paste that.
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Here it is:
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 3.06.a
PARAMETER PROC_INSTANCE = ppc405_0
PARAMETER STDIN = rs232_db9
PARAMETER STDOUT = rs232_db9
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_ppc405
PARAMETER DRIVER_VER = 1.12.a
PARAMETER HW_INSTANCE = ppc405_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = eeprom_onewire
PARAMETER DRIVER_VER = 1.10.a
PARAMETER HW_INSTANCE = eeprom_controller
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = plbv46_plbv46_bridge_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ppc405_0_docm_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ppc405_0_iocm_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = radio_controller
PARAMETER DRIVER_VER = 1.30.a
PARAMETER HW_INSTANCE = radio_controller_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = rs232_db9
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = rs232_usb
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = lltemac
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = trimode_mac_gmii
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = llfifo
PARAMETER DRIVER_VER = 2.02.a
PARAMETER HW_INSTANCE = trimode_mac_gmii_fifo
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = warp_v4_userio
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = userio
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = w2_warplab_agc_plbw
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = warplab_agc_plbw_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = w2_warplab_buffers_plbw
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = warplab_buffers_plbw_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 3.01.a
PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = dmacentral
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = xps_central_dma_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = xps_gpio_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 2.04.a
PARAMETER HW_INSTANCE = xps_timer_0
END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = WARP_HW_VER
PARAMETER LIBRARY_VER = 2.20.a
PARAMETER PROC_INSTANCE = ppc405_0
END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = WARPxilnet
PARAMETER LIBRARY_VER = 3.00.a
PARAMETER PROC_INSTANCE = ppc405_0
PARAMETER EMAC_INSTNAME = trimode_mac_gmii
END
There are still three instances with 'generic'. Could that be a problem?
EDIT: I've compared this to the .mss file I have in the standard reference design, and the only difference is that for "OS" the 'OS_VER' = 3.03.a instead of '3.06.a'. But I'm guessing that just due to updates in the repository. The only other difference is the order in which the drivers appear.
Last edited by Pieter_W (2013-Feb-05 14:30:46)
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Your MSS looks great. No problems there as far as I can see.
Pieter_W wrote:
I chose the iocm for the code sections, the docm for the data sections and i didnt change anything for the heap and stack. That's all, right?
I missed this edit from your earlier post. I think this is the problem. WARPxilnet uses a central DMA controller to get packets two and from the FIFO for Ethernet (for example, writing bytes to the FIFO occurs here). The central DMA controller can only access memory in BRAM... it can't see things in the docm of the PPC.
What you are seeing is that code is booting and running, but the DMA transfer isn't working at all so you have no communication over Ethernet. In your linker script, put the data in xps_bram_if_cntrl_1 instead of docm. I believe you can leave heap and stack in docm, but maybe change those also if it still doesn't work. I think it will start working after this change.
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Hmm, it still doesn't work. I've tried putting the data in the bram_ctrl and tried putting the heap and stack in both possibilities.
I almost don't dare to ask. It's just a suggestion, but I think it could save us some time. I obviously did something wrong or forgot to do something, although I really don't know what. Could you maybe try to do what I wanted to do, like I said in my first post. I figure, apart from the compiling time, it should only take 5-10 mins. And then just see, if you do something, that I did not mention here in this thread.
I know it's kinda rude to ask, but I actually want to save your time.
I think when I get this workflow working, I'll just make a list of everything I should take care of and I'll be able to get started without much trouble in the future.
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Oh wait! Now it works! The latest combination for the Linker script did the trick.
I'm happy for me and you. :) Thanks a million times. I'm gonna start working on a file to remember everything that needs to be done.
Last edited by Pieter_W (2013-Feb-05 14:55:53)
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Great, good to hear.
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Hi,
I try to regenerate WARPLab v7.5.1 bit file from very beginning for w3 2RF. I made a clean working environment with appropriate folder structure. The steps I follow are:
1) I get the following versions of the models from the SVN repository and generate the pcores through SysGen (ISE 14.4) and then put them in the pcores directory:
- warplab_agc_axiw_v3_00_b (generated from warplab_agc_v3 v3.00.b)
- w3_warplab_buffers_axiw_v3_01_c (generated from warplab_buffers v3.01.c)
- w3_warplab_trigger_proc_axiw_v1_04_b (generated from warplab_trigger_proc v1.04.b)
2) I modify the mpd file for the buffers as explained in the README file:
# PORT rf_rx_iq_rssi_int = "", DIR = OUT --- Need to add interrupt parameters
# PORT rf_tx_iq_int = "", DIR = OUT --- Need to add interrupt parameters
PORT rf_rx_iq_rssi_int = "", DIR = OUT, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
PORT rf_tx_iq_int = "", DIR = OUT, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
3) I open the system.xmp file with XPS and generate the bit file and export the design to SDK environment. The hw environment is created and SDK opens.
4) In SDK, I generate the BSP with the settings below. I name it as warplab_bsp_0:
- WARP_FPGA_BOARD_LIB v2.20.a
- WARP_HW_VER v3.10.a
- WARPxilnet_v3.04.a
5) I import the src files into the SDK environment. It compiles without any error.
6) I generate the download.bit file through Xilinx Tools -> Program FPGA. I see that it is generated.
However, when I program the FPGA, I don't see the display is set to 01. Instead it shows 00. And I cannot run the wl_setup.m from MATLAB.
Do you have any idea what the problem is. Am I missing something throughout the steps above?
Thanks.
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That looks like the correct process. One thing to check:
6) I generate the download.bit file through Xilinx Tools -> Program FPGA. I see that it is generated.
In the Program FPGA dialog, did you select the WARPLab .elf file? By default the SDK will use an empty (bootloop) binary for the CPU. In hardware the bootloop would behave the way you describe.
Another thing to check is if the WARP v3 node's UART prints anything after you configure the FPGA with download.bit.
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Thank you murphpo, I selected the .elf file instead of bootloop. Now it works.
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