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#1 2018-Jun-21 04:41:40

vutran
Member
Registered: 2017-Jul-01
Posts: 43

using warplab trigger in other design - IDELAYCTRL problem

Hi,

I want to use warplab_trigger for my extension on 802.11 reference design. But I face this problem:

PhysDesignRules:2216 - IDELAYCTRL not found for clock region CLOCKREGION_X0Y3. The IODELAYE1 block warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/trigger_sources_b9a8d19442/external_trigger_inputs_and_iodelays_d04df33fc8/black_box1/trig3_idelay/IODELAYE1_inst has an IDELAY_TYPE attribute of FIXED, VARIABLE, or VAR_LOADABLE. This programming requires that there be an IDELAYCTRL block programmed within the same clock region.

I have no idea how to config the IDELAYCTRL for the warplab_trigger. Can you please give me some instruction?

Thank you

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#2 2018-Jun-21 08:52:05

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4964

Re: using warplab trigger in other design - IDELAYCTRL problem

That's a strange error. Can you describe exactly what changes you made to the design to trigger this error?

The IDELAYCTRL is an FPGA primitive that manages the IDELAY/ODELAY blocks in at each IO pin. There are specific (and confusing) rules for instantiating IDELAYCTRL blocks (AR37695 is just one example; see V6 IO user guide pg 117 for more details). The 802.11 and WARPLab Ref Designs both use I/ODELAY for the Ethernet RGMII interfaces and in the DRAM controller. The WARPLab design also uses I/ODELAYs in the trigger processor (for the external triggers routed to the debug header).

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#3 2018-Jun-21 10:05:25

vutran
Member
Registered: 2017-Jul-01
Posts: 43

Re: using warplab trigger in other design - IDELAYCTRL problem

I added my own logic to the phy_rx to capture the raw data at other antennas, so I add a trigger_in pin to the phy_rx to trigger my extended logic. Then I copy the warplab_trigger pcore to the 802.11 project, instantiate the trigger in the following system.mhs, and added the CM_PLL pins in system.ucf. I left the debug output (of the trigger) unconnected and the debug input connected to ground. Please have a look at the following system.mhs (I can't find a way to attach file, so I paste the content of the file below - only related part because it is longer than 65536 characters)

#-----------------------------------------------------------  system.mhs
...
# CM-PLL pins
PORT cm_pll_hdr_in_d = cm_pll_0_in & cm_pll_1_in & cm_pll_2_in & cm_pll_3_in, DIR = I, VEC = [0:3]
PORT cm_pll_hdr_out_d = cm_pll_0_out & cm_pll_1_out & cm_pll_2_out & cm_pll_3_out, DIR = O, VEC = [0:3]

BEGIN w3_warplab_trigger_proc_axiw
PARAMETER INSTANCE = warplab_trigger_proc
PARAMETER HW_VER = 1.07.g
PARAMETER C_BASEADDR = 0x93000000
PARAMETER C_HIGHADDR = 0x93000FFF
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
BUS_INTERFACE S_AXI = mb_low_axi_periph
BUS_INTERFACE AXI_STR_ETH_A_RXD = ETH_A_MAC_AXIS_RXD
BUS_INTERFACE AXI_STR_ETH_B_RXD = ETH_B_MAC_AXIS_RXD
PORT axi_aclk = clk_160MHz
PORT trig_0_out = raw_trigger
PORT sysgen_clk = clk_160MHz
PORT agc_done_in = agc_done
PORT debug_1_in = net_gnd
PORT debug_2_in = net_gnd
PORT debug_3_in = net_gnd
# CM-PLL header trigger inputs
PORT cm_pll_0_in = cm_pll_0_in
PORT cm_pll_1_in = cm_pll_1_in
PORT cm_pll_2_in = cm_pll_2_in
PORT cm_pll_3_in = cm_pll_3_in
PORT cm_pll_0_out = cm_pll_0_out
PORT cm_pll_1_out = cm_pll_1_out
PORT cm_pll_2_out = cm_pll_2_out
PORT cm_pll_3_out = cm_pll_3_out
PORT rfa_rssi = RFA_RSSI_D
PORT rfb_rssi = RFB_RSSI_D
PORT rfc_rssi = RFC_RSSI_D
PORT rfd_rssi = RFD_RSSI_D
PORT rssi_clk = wlan_rssi_clk
PORT debug_0_in = net_gnd
END

BEGIN wlan_phy_rx_pmd_axiw
PARAMETER INSTANCE = wlan_phy_rx
PARAMETER HW_VER = 4.01.x
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
PARAMETER C_BASEADDR = 0x41000000
PARAMETER C_HIGHADDR = 0x4100FFFF
BUS_INTERFACE PORTB = WLAN_RX_PKT_BUF_PORTB
BUS_INTERFACE RAWPORTB = WLAN_RX_PKT_RAW_PORTB
BUS_INTERFACE S_AXI = mb_low_axi_periph
PORT axi_aclk = clk_160MHz
PORT sysgen_clk = clk_160MHz
# PORT pkt_det_in = net_wlan_phy_rx_pkt_det_in
PORT pkt_det_in = net_gnd
PORT rx_sigs_invalid = rx_sigs_invalid
PORT rx_iq_samp_ce = agc_iq_valid_out
PORT rfa_rx_i = agc_rfa_i
PORT rfa_rx_q = agc_rfa_q
PORT rfa_rssi = RFA_RSSI_D_REG
PORT rfb_rx_i = agc_rfb_i
PORT rfb_rx_q = agc_rfb_q
PORT rfb_rssi = RFB_RSSI_D_REG
PORT rfc_rx_i = agc_rfc_i
PORT rfc_rx_q = agc_rfc_q
PORT rfc_rssi = RFC_RSSI_D
PORT rfd_rx_i = agc_rfd_i
PORT rfd_rx_q = agc_rfd_q
PORT rfd_rssi = RFD_RSSI_D
PORT rssi_adc_clk = wlan_rssi_clk
PORT pkt_det_o = phy_rx_pkt_det
PORT rfa_g_rf = agc_rfa_g_rf
PORT rfa_g_bb = agc_rfa_g_bb
PORT rfb_g_rf = agc_rfb_g_rf
PORT rfb_g_bb = agc_rfb_g_bb
PORT rfc_g_rf = agc_rfc_g_rf
PORT rfc_g_bb = agc_rfc_g_bb
PORT rfd_g_rf = agc_rfd_g_rf
PORT rfd_g_bb = agc_rfd_g_bb
PORT agc_done = agc_done
# MAC <-> PHY ports
PORT phy_rx_reset = phy_rx_reset
PORT phy_rx_block_pktdet = phy_rx_block_pktdet
PORT phy_cca_ind_busy = mac_phy_cca_ind_busy
PORT phy_rx_data_byte = mac_phy_rx_data_byte
PORT phy_rx_data_bytenum = mac_phy_rx_data_bytenum
PORT phy_rx_data_done_ind = mac_phy_rx_data_done_ind
PORT phy_rx_data_ind = mac_phy_rx_data_ind
PORT phy_rx_end_ind = mac_phy_rx_end_ind
PORT phy_rx_end_rxerror = mac_phy_rx_end_rxerror
PORT phy_rx_fcs_good_ind = mac_phy_rx_fcs_good_ind
PORT phy_rx_phy_hdr_ind = mac_phy_rx_phy_hdr_ind
PORT phy_rx_phy_hdr_length = mac_phy_rx_phy_hdr_length
PORT phy_rx_phy_hdr_mcs = mac_phy_rx_phy_hdr_mcs
PORT phy_rx_phy_hdr_phy_mode = mac_phy_rx_phy_hdr_phy_mode
PORT phy_rx_phy_hdr_unsupported = mac_phy_rx_phy_hdr_unsupported
PORT phy_rx_start_ind = mac_phy_rx_start_ind
PORT phy_rx_start_phy_sel = phy_rx_start_phy_sel
# Debug ports
PORT dbg_dsss_rx_active = dbg_dsss_rx_active
PORT dbg_lts_timeout = dbg_lts_timeout
PORT dbg_pkt_det_dsss = dbg_pkt_det_dsss
PORT dbg_pkt_det_ofdm = dbg_pkt_det_ofdm
PORT dbg_payload = dbg_ofdm_rx_active
PORT dbg_rssi_det = dbg_rssi_det
PORT dbg_signal_err_disp = dbg_signal_err_disp
PORT trigger_in = raw_trigger
END

# -------------------------------------------------------------------------- system.ucf

# Trigger in/out via CM-PLL daisy chain headers - CM-PLL rev 1.1
NET "cm_pll_hdr_in_d<0>"          LOC = "V28"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # CLKHDR_CTRL3  in W3 schematics
NET "cm_pll_hdr_in_d<1>"          LOC = "V27"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # CLKHDR_CTRL2  in W3 schematics
NET "cm_pll_hdr_in_d<2>"          LOC = "V33"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # CLKHDR_CTRL1  in W3 schematics
NET "cm_pll_hdr_in_d<3>"          LOC = "V34"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # CLKHDR_CTRL0  in W3 schematics

NET "cm_pll_hdr_out_d<0>"         LOC = "V32"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL4  in W3 schematics
NET "cm_pll_hdr_out_d<1>"         LOC = "W34"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL5  in W3 schematics
NET "cm_pll_hdr_out_d<2>"         LOC = "W30"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL6  in W3 schematics
NET "cm_pll_hdr_out_d<3>"         LOC = "W29"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL7  in W3 schematics

INST "warplab_trigger_proc"       AREA_GROUP = "WL_TRIGGER_PROC";

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#4 2018-Jun-21 10:31:24

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4964

Re: using warplab trigger in other design - IDELAYCTRL problem

I think the problem is that you didn't connect the warplab_trigger_proc  debug_in/debug_out ports to top-level pins. The trigger_proc core HDL requires these ports be connected to pins, otherwise the I/ODELAY primitives can't be associated with specific IOBs in hardware.

What functionality do you need from the warplab_trigger_proc core?

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#5 2018-Jun-21 11:12:40

vutran
Member
Registered: 2017-Jul-01
Posts: 43

Re: using warplab trigger in other design - IDELAYCTRL problem

Thank you. I'm trying that solution and let you know the result. I need to calibrate the phase difference of carrier signal among 8 antennas (2 Warps) for beam-forming (but it is not MIMO - much simpler, I believe). So I insert another Bram port in phy_rx to capture raw signal of all antennas. I don't want to change any logic of the current 802.11 design so that I can still it as an AP.

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#6 2018-Jun-22 12:10:58

vutran
Member
Registered: 2017-Jul-01
Posts: 43

Re: using warplab trigger in other design - IDELAYCTRL problem

It's correct, it compiles successfully when I connect the debug ports to IO pins. Thank you.

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