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In the V10.1 tools, it is suggested to include Xilinx EDK Processor block and select sysgen compilation target 'Export as a poce for EDK' for converting sysgen application model to pcore. The registers are also represented by Xilinx's 'From Register' and 'To Register' blocks.
In the V9.1, WARP team suggested to use sysgen2opb and created 'Read Only Reg' and 'Read Write Reg'.
However, in V9.1 Xilinx tools, we could also do what was suggested for V10.1.
Why WARP team didn't suggest to use Xilinx's built-in flow in previous version?
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My recollection is that Sysgen v9.1 only supported exporting pcores with FSL interfaces, which only worked with MicroBlaze systems (or Virtex-4 ones, with a kludgey APU-FSL hook). There was no way to use the pcores with a Virtex-II Pro PPC. In v9.2, they added a PLB46 export option, but EDK 9.2 didn't support PLB46 for Virtex-II Pro devices. v10.1 was the first version where both a PLB46 export and flow from Sysgen to V2P PPC was possible.
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