WARP Project Forums - Wireless Open-Access Research Platform

You are not logged in.

#1 2018-Aug-01 04:26:25

vutran
Member
Registered: 2017-Jul-01
Posts: 43

concurrent multiple Rx in 802.11Ref

Hi,

I want to implement an extension to 802.11Ref design to receive RAW Rx data from 4 antennas (I need the 802.11 not WARPLab). Though I can receive and store RX-A perfectly, the data on Rx-B, Rx-C and Rx-D (I have added the blocks for 4 antennas like this app note) are almost zeros. This is weird because the reference design seems to enable the 4 antennas at the same time.
Can you please give me some clues to solve this problem?

Last edited by vutran (2018-Aug-01 04:29:37)

Offline

 

#2 2018-Aug-01 08:58:53

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4964

Re: concurrent multiple Rx in 802.11Ref

Did you change the C code to put all four RF interfaces in Rx mode? By default the 802.11 code only enables Rx mode on RF A.

Offline

 

#3 2018-Aug-02 01:59:32

vutran
Member
Registered: 2017-Jul-01
Posts: 43

Re: concurrent multiple Rx in 802.11Ref

Thanks for your help, I can receive data at 4 antennas now. But I have another problem with Ant_D, it shows severe noise that my module cannot decode the data. Please check this image, it shows the data record on Ant_A and Ant_D using a splitter with 60dB attenuator. I suspect this is related to the previous post I asked but I haven't found the way to adjust the delay in the ADC.

Can you guide me how to adjust the delay in AD line or some suggestions on this problem?

I found only 1 line in w3_low.c (495) calling ad_init(AD_BASEADDR, AD_ALL_RF, 3), and it set the same value for all antennas

Offline

 

#4 2018-Aug-02 22:32:00

vutran
Member
Registered: 2017-Jul-01
Posts: 43

Re: concurrent multiple Rx in 802.11Ref

Hi,
Another phenomenon is that turning ON/OFF the board sometime helps. I think it is a problem with IDELAY at ADC pin, am I correct?
Do you have any suggestions?

Offline

 

#5 2018-Aug-03 10:20:41

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4964

Re: concurrent multiple Rx in 802.11Ref

A few suggestions:
-Are you using w3_ad_bridge v3.03.b for the FMC interfaces (same version as the on-board interfaces)?

-The sampling clock output to the FMC module is driven by the CLKOUT4 port of the AD9512 buffer on the W3 board. The CLKOUT4 port has a programmable delay block which you can configure from C code. Adjusting this delay will adjust the relative phases of the FPGA clock and the sampling clock on the FMC module; this might help resolve the IO timing issues you're seeing in your design.

The code below is a starting point; add this code at the end of w3_node_init() in w3_low.c. Refer to the AD9512 datasheet for details on the CLKOUT4 delay registers (registers 0x34/0x35/0x36).

Code:

// Set delay on CLKOUT4 (sampling clk output to FMC)
clk_spi_write(CLK_BASEADDR, CLK_SAMP_CS, 0x34, 0); //disable delay bypass
clk_spi_write(CLK_BASEADDR, CLK_SAMP_CS, 0x35, 0x00); //Set largest full-scale delay
clk_spi_write(CLK_BASEADDR, CLK_SAMP_CS, 0x36, 0x3E); //Set max delay 

// Apply config updates
clk_spi_write(CLK_BASEADDR, CLK_SAMP_CS, 0x5A, 0x01); //Self-clearing register update flag

// Sync outputs (High -> Low transition on bit 2 - Soft SYNC)
clk_spi_write(CLK_BASEADDR, CLK_SAMP_CS, 0x58, 0x04);
clk_spi_write(CLK_BASEADDR, CLK_SAMP_CS, 0x5A, 0x01); //Self-clearing register update flag
clk_spi_write(CLK_BASEADDR, CLK_SAMP_CS, 0x58, 0x00);
clk_spi_write(CLK_BASEADDR, CLK_SAMP_CS, 0x5A, 0x01); //Self-clearing register update flag

Offline

 

#6 2018-Aug-10 07:30:52

vutran
Member
Registered: 2017-Jul-01
Posts: 43

Re: concurrent multiple Rx in 802.11Ref

Thank you very much. It works at a delay of 4.65 ns.
However, I still face another problem with the following error message on boot:

Code:

(ad_set_TxDCO): ERROR - invalid csMask (0x04000000) or DCO (65535)!
(ad_set_TxDCO): ERROR - invalid csMask (0x04000000) or DCO (65535)!

I connect 2 boards via CMPLL cable. The slave board (input ref clock) shows this error. It seems the DCO value for AntC is 65535, but this value is read from EEPROM (line 809, 810 radio_controller.c), so I don't have any idea to change it.
Can you give me some suggestions?

Last edited by vutran (2018-Aug-10 07:32:45)

Offline

 

#7 2018-Aug-10 09:43:45

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 4964

Re: concurrent multiple Rx in 802.11Ref

A TxDCO calibration value of 65535 (0xFFFF) indicates the EERPOM contents are invalid (corrupted, overwritten, etc). You can safely ignore that warning for now; typically DCO correction values are small, that warning implies the DCO correction is left at zero. Fixing the EERPOM contents require re-calibrating the TxDCO on the FMC-RF-2X245 interfaces; I'll look for the design that does this (our manufacturer does the calibration during testing, it's been a long time since I did it directly).

Offline

 

Board footer