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#1 2019-Jul-12 16:48:11

amgoyal
Member
Registered: 2019-Jul-12
Posts: 1

Running WARP v3 ref design 7.7.1 at 80Msps sampling rate

Hey! I am pretty new to the platform and have some questions regarding the hardware:

1. The default sample rate of the warp board is 40Msps. Is it possible to somehow increase it to 80Msps or any other value for that matter?

2. The maximum pass-band of the tx and rx low pass filters is 36Mhz. Is it possible to increase that any further?

Thanks

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#2 2019-Jul-15 09:47:12

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Running WARP v3 ref design 7.7.1 at 80Msps sampling rate

It would be possible to run the ADC/DACs at 80MSps - the AD9963 datasheet has more details on the analog converter capabilities. The sampling rate is configured during boot in the C code. But the C code must configure clock rates compatible with the FPGA design. The reference WARPLab FPGA design assumes a 40MHz sampling clock. Also, as you noted, the MAX2829 RF bandwidth is limited to <40MHz. Running the converters at 80MSps would allow oversampling but would not increase the achievable RF bandwidth.

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