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Hello,
I am having difficulty placing the heap and stack into SRAM. I am running a warplab v4 project that has been changed to include among other things, the memory controllers for the sram as well as the utility bus splits. I have also added the external ports (fpga0_SRAMx...) to the .mhs file as done in ofdm reference designs 11 and 12. I am able to successfully upload and run the project on the board whenever the heap and stack are assigned to docm, however the application i wish to run requires a much larger heap than I can achieve with the current docm size. Placing the heap and stack in SRAM causes the board to be unresponsive (i.e. segmented led's do not turn on, board does not accept commands). Below I have included a portion of the .mhs related to SRAM1. Similar entries exist for SRAM0. Are there any additional configurations required outside of making changes to the .mhs file in order to get the heap and stack on SRAM?
Thanks in advance,
DGonzalez
PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN, DIR = O, VEC = [0:0]
PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN, DIR = O
PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN, DIR = O
PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN, DIR = O, VEC = [0:3]
PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN, DIR = O
PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_CE_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_CE, DIR = O
PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_A_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_A, DIR = O, VEC = [11:29]
PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ, DIR = IO, VEC = [0:31]
PORT fpga_0_SRAM1_CLOCK = sys_clk_s, DIR = O
BEGIN xps_mch_emc
PARAMETER INSTANCE = SRAM1_ZBT_512Kx32
PARAMETER HW_VER = 2.00.a
PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 12500
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MAX_MEM_WIDTH = 32
PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_MEM0_WIDTH = 32
PARAMETER C_SYNCH_MEM_0 = 1
PARAMETER C_TCEDV_PS_MEM_0 = 0
PARAMETER C_TWC_PS_MEM_0 = 0
PARAMETER C_TAVDV_PS_MEM_0 = 0
PARAMETER C_TWP_PS_MEM_0 = 0
PARAMETER C_THZCE_PS_MEM_0 = 0
PARAMETER C_TLZWE_PS_MEM_0 = 0
PARAMETER C_MEM0_BASEADDR = 0x00000000
PARAMETER C_MEM0_HIGHADDR = 0x001fffff
BUS_INTERFACE SPLB = plb0
PORT Mem_A = fpga_0_SRAM1_ZBT_512Kx32_Mem_A_split
PORT Mem_BEN = fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN
PORT Mem_WEN = fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN
PORT Mem_DQ = fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ
PORT Mem_OEN = fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN
PORT Mem_ADV_LDN = fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN
PORT Mem_CKEN = fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN
PORT Mem_CE = fpga_0_SRAM1_ZBT_512Kx32_Mem_CE
PORT RdClk = sys_clk_s
END
BEGIN util_bus_split
PARAMETER INSTANCE = SRAM1_ZBT_512Kx32_util_bus_split_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 11
PARAMETER C_SPLIT = 30
PORT Sig = fpga_0_SRAM1_ZBT_512Kx32_Mem_A_split
PORT Out1 = fpga_0_SRAM1_ZBT_512Kx32_Mem_A
END
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A few questions:
-Did you update the UCF with the SRAM pin assignments? You can use the OFDM refdes or a Base System Builder project to get these constraints.
-When you assign the heap/stack to the SRAMs, do you leave the other code sections in on-chip memory? This is required if you want it to boot automatically (i.e. without using a boot loader).
-Can you read/write anything to the SRAM? Try creating a new software project with all its code sections assigned to on-chip memory. Then in code, try reading/writing to the SRAM (memcpy(SRAM1_ZBT_512Kx32_BASEADDR, someArray, len) for example).
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