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We want to implement 802.11b 's PHY design
and we have already have build a simple structure about it (like scramble and preamble spec...etc)
but we meet a big problem about data modulation and demodulation.
We have simulate the DSSS/Barker code/BPSK modulation and demodulation successfually,
but we meet timing problem when we want to generate it for real pcore.
We don't konw when the pkt begining and how to sychronize two board's clock for carrier recovery.
We have "vague" information from OFDM_MIMO_design : which using RSSI to know the pkt begin
and "PKT_decactor" pcore to send the bigin siginal? using AGC pcore to control Antana's gain and "syncronize clock"??
but we don't know the detail about these....
So how can i use these existing module to help our design@@???
Or we should do our siginal recovery pcore like costas loop design??
-----------and after this i have some question we meet-------------------------------------------
--We have using our design send 1Mbps BPSK Sin wave and using chipscope to observe the "user_RSSI_ADC_D",
--and the receiver really get same siginal wave we sended but RSSI is always 0.@@
--(Sorry I have figure this problem out. The answer is we don't send clk to rssi_clk.....)
My question is that the clock rate is 40MHz which is mean one clock cycle in our Matlab design is 1/40us??
And there are a lot of downsampler and upsampler in your OFDM_TX_RX design.
What is the purpose of these circuit??? Is it play the role of "filter (ex: down sampler fro LPF)"???
And is the pkt_detector pcore is generated from a part of OFDM_TXRX mdlsrc in RX part??? How can you do that@@?
Thanks a lot@@!!!
Last edited by eddyxd (2009-Aug-20 03:29:13)
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And is the pkt_detector pcore is generated from a part of OFDM_TXRX mdlsrc in RX part??? How can you do that@@?
The latest OFDM transceiver core includes the packet detection logic; there is no separate packet detector pcore anymore. We did this for efficiency reasons, to avoid duplication of logic between two cores. The basic function is the same- to detect a rise in average RSSI, indicating the arrival of a packet.
The AGC core analyzes the RSSI and magnitude of I/Q to determine the best Rx gains to apply per packet. It also estimates and corrects any residual DC offset in the I/Q samples once gains have been set.
And there are a lot of downsampler and upsampler in your OFDM_TX_RX design.
Those blocks apply a rate change to the given signal, either by zero stuffing or repeating (for upsample) or by discarding samples (for downsample). The System Generator users guide has much more information about this and about how multi-rate designs are implemented.
We don't konw when the pkt begining and how to sychronize two board's clock for carrier recovery.
Carrier frequency offset recovery is a tricky part of any wireless design. I don't know enough about 802.11b to say exactly how it should be done. It's probably some combination of preamble-based estimation and tracking using phase estimates derived from the data (like a Costas loop).
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