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Hello all,
We have posted a new reference design (http://warp.rice.edu/trac/wiki/OFDMReferenceDesign). The key changes are:
+updated radio controller to 1.08.a
+added interrupt-driven Ethernet w/DMA
-removed Xilkernel dependency
-removed dynamic memory allocation support
This design is in lockstep with v2.1 of the WARPMAC framework (http://warp.rice.edu/trac/browser/Platf … .c?rev=603)
-Chris
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To run this new reference design, do we have to wait until the arrival of new boards or we can use the current FPGA board and radio card?
Thanks.
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This design will work with your current hardware (and all WARP hardware out there).
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1. I was going through the new OFDM reference design and would like to ask about what is unique about myID = 2, the check condition which has been put up at a few places in the csma code.
2. Moreover, the empty while() loop in CSMA mac looks wrong to me. Perhaps the loop body should contain something of the sort
if(txBuffer.isNew==0){
warpmac_pollEthernet(ethernet_callback);
}
as is the case in the earlier code of noMAC. Is that correct?
Last edited by toolbox (2007-Jun-20 13:32:47)
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1) Don't read too much into the myID=2 code; That's just some extra state to deal with a third node that acts as a multi-hop relay (the source and sinks are IDs 0 and 1). All that code does is receive from OFDM and send to OFDM (no ethernet).
2) We've switched over to using interrupts for the ethernet. Notice that the new "warpmac_setEmacHandler" function now attached the callback directly to warpmac (http://warp.rice.edu/trac/browser/Resea … v=612#L307). It will automatically be called when something is received from Ethernet.
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(1) What is the ADC/DAC sampling rate for reference design V03? Are they the same?
(2) Where are these clock comes from?
I am confused by the following facts:
(A) The photos on the repository page show that you use wires from the clock board. In an old post, you mentioned that the clock board will distribute a very clear 40MHz clock to ADC and DAC.
(B) The mhs file of reference design V03 shows that the dcm module still takes in 100MHz clock and generates a 50MHz clock for opb bus.
(C) In your ofdm_TxRx_mimo.mdl, the TX DAC gateway blocks are 4 times faster than the RX ADC gateway blocks. Is this the version you used to generate the bitstream?
In short, the rate change in ofdm_TxRx_mimo.mdl does not match a 50MHz opb and 40 MHz ADAC.
Thanks.
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1) The clock configuration in this design is identical to the previous versions: 200/100/50MHz for PPC/PLB/(OPB + ADC/DAC).
2) Same as always; what I said in this post still applies.
a) The photos show the clock board providing the radio reference clock, not the sampling clock. The clock boards with 40MHz oscillators (for the sampling clock) are still being built. Your hardware uses oscillators mounted on the radio board itself for the reference; either configuration works equally well with the reference design.
c) The analog converters run at 50MHz, but our occupied bandwidth is 12.5MHz (1/4 of Nyquist). The OFDM model includes an interpolating polyphase filter to achieve this rate change. A matching decimation filter is contained in the AGC core, since the AGC processing requires both RSSI and I/Q samples. The AGC provides filtered, 1/4 rate samples to the OFDM PHY's inputs, hence the slower gateways in.
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