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Hello,
I want to utilize the DebugIO pins (J16) to connect an external circuit (sensors/actors) with the WARP board. To do this, I have several questions for which I could not find an answer in the Rice and/or Xilinx documents.
1) Electrical considerations:
What are the allowed current limitations for the VirtexIIP/4? I found limitations for the Virtex4 (link) to be 10mA (recomm. p. pin) and 100mA (max. p. pin).
2) FPGA considerations:
Do I have to change anything in the design files (e.g. change Bank0 behavior to be input-and-output), or is it sufficient to configure the xps_gpio core accordingly (bi-directional non-input-only)? Do I have to add information buffers in the FPGA fabric?
3) Code considerations:
Is it sufficient to use the XGpio_mGetDataReg macro to get information from the pins, or do I also have to use XGpio_mSetDataDirection and/or other macros?
Any comments/hints are highly appreciated.
Christian
Last edited by Christian (2010-Aug-09 04:27:15)
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1) 10mA is the maximum. The I/O pins have protection diodes to prevent blowing out the pin and they limit the current to 10mA. The 100mA is the absolute maximum and I don't recommend being that close. Both versions of the FPGA Board connect to a 3.3V I/O bank.
2) All you should need is the gpio core and the entries in the UCF file.
3) XGpio_DiscreteRead is also a good way to read the bits.
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3) You can also drive/access the pins directly from custom cores. We do this extensively in the OFDM ref design, to monitor when the PHY is transmitting or receiving a packet. These signals are outputs from the PHY sysgen model, connected to top-level ports in the XPS project and constrained to the debug pins in the UCF file.
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Thanks for the information.
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