You are not logged in.
As soon as the OFDM V15 design is loaded to the FPGA (on Virtex4 FPGA boards v2.2) the voltage regulator U1 is getting very hot and the voltage output (monitored on the MGT_1.2V test point) is quickly dropping from initial 1.2V to ~800mV and then the regulator enters periodic thermal shut-down state (MGT_1.2V output voltage periodically changes between ~800mV and ~200mV). Once in this periodic thermal shut-down DVDD_3.3V bus starts to have periodic noise of ~70mVpp and the period of 700us.
This voltage regulator supplies AVCAUXTX/RX to MGTs (Multi-Gigabit Transceivers) MGT_1.2V bus, and after further checking I don't think this MGT_1.2V should directly affect Tri-Mode Eth MAC or other parts of the design, but for some reason this MGT problem seemed to cause for me unsuccessful, and non-repeatable, BER tests with warpnet example (http://warp.rice.edu/forums/viewtopic.php?id=827).
I have added a heat-sink to this U1 1.2V regulator (Digikey PN: 345-1043-ND), and as well I had to use external fan to keep even this heat-sink from over-heating. Now the voltage on MGT 1.2V test point, still suddenly drops to ~1.1V, as soon as OFDM v15 design is loaded, but at least it seems to stay stable at this value for long time. After this modification on two WARP 2.2 boards, the warpnet BER application seems to work well and stable (the modification seemed to significantly improve the measured BER performance, and to fix the 'request time-out' problems I was observing in topic http://warp.rice.edu/forums/viewtopic.php?id=827).
Although the temporary solution with heat-sink and external fan seems to be working OK for now, I think the MGT protectors design should be revised to reduce the power consumption from AVCAUXTX/RX power bus.
To reduce the consumed power, could we use a much slower clock (instead of 100MHz? fpga_0_clk_board_config_sys_clk) to keep the MGT Protectors running? Any other suggestions?
BTW, we have also observed this over-heating issue with the warplab design, I suppose this design also uses MGT_protectors.
Last edited by rmoraw (2010-Nov-11 11:08:58)
Offline
To answer previous question I tried to use 10x reduced clock speed for GREFCLK of MGT_protector, but I did not notice any significant reduction of current consumption on AVCCAUXTX/RX bus, thus I assume that even with GREFCLK=GND I will not see any current reduction.
In that case I assume the only way to reduce total current on AVCCAUXTX/RX 1.2V bus is to put some of the MGTs (which will never be used, into power-down mode, or simply leave them uninstantiated).
Based on Schematic of WARP FPGA Board v.2.2, the following listed MGTs' have TX and RX ports, which are not connected to any hardware (i.e. the tx/rx pins are left unconnected), thus I assume that these MGTs will never be used on this development board, and consecuently I could be put them in the power-down mode (or simply not instantiated) to reduce the power consumtion on AVCCAUXTX/RX 1.2V bus by approximatelly 50% (or ~2A), which would presumably put total AVCCAUXTX/RX 1.2V current consumtion in the operating range (max 3A) of our currently used voltage regulator.
MGT 101A/B or LOC 0
MGT 103A/B or LOC 2
MGT 105A/B or LOC 3
MGT 106A/B or LOC 4
MGT 109A/B or LOC 9
NOTE: MGT 110A/B (or LOC 8), as well does not have tx/rx ports connected to any hardware, but it has a MGTCLK_P/N_110 pins connected to 300MHz osc., and thus might be needed (?) for potential routing of this 300MHz clock to other MGTs (112, 113, 114, or 102) already connected to external hardware and potentially to be used in the future.
In MGT_protector peripheral IP configuration section (in the Xilinx XPS project), I would like to propose to change the following parameters to:
C_USE_0 false
C_USE_2 false
C_USE_3 false
C_USE_4 false
C_USE_9 false
Any comments if the above would have any adverse effect on the future use, performance or clock configuration of the remaining MGT_protected MGTs?
Offline
Very interesting observations- we have very little experience with the MGTs, and instantiated the protection cores at the suggestion of the Xilinx docs. I'm surprised reducing the clock speed didn't change current draw- maybe it's one of the other MGT clock inputs that is driving the power-hungry logic? In any case, disabling the protectors for MGTs you don't anticipate ever using is probably fine (in all our projects using the hardware, we've never used them; we found they're just too big a hassle).
Offline
Xilinx tech support also confirms that not instantiating MGTs (disabling MGT_protectors) will not affect the remaining (protected) MGTs future performance, however they also mention that due to PLL (in each MGT) which does not shut-down even in power-down mode, we cannot expect 50% savings in total current when only 5 MGTs are in protected mode.
I did some actual current measurements:
- for the designs with all 10 MGTs in the protected mode (as warplab or warp OFDM reference designs) the total current from VCCAUXTXRX supplly was 3.38A, thus over 3.0A limit of presently installed 1.2V MGT voltage regulator (which explains previously described issue).
- for the modified design with only 5 MGTs in the protected mode the total current from VCCAUXTXRX supplly dropped to 2.1A, thus within the range of 3.0A limit.
Note that even with reduced 2.1A current, 1.2V MGT voltage regulator Tj is still very hot ~80degC (with heat-sink installed, but no air flow), thus the forced air flow is really needed for this board. With forced air flow the 1.2V MGT voltage regulator Tj temperature is at reasonable 50degC (assuming 25degC ambient).
Further BER measurements showed that forced air has to be blowing on all the board, not only the voltage regulators. I suppose the clock and RF board ICs are also getting warm and were degrading BER by as much as 5 times.
Offline