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Hi,
The IP Core radio_controller is used by the ppc to control the radio board. I am not aware of the way to generate this ip core, although i can check the generated hdl files. As I know the ofdm tx_rx core is designed and generated by the system generator and also the PLB interface is also automatically generated by the EDP processor. However, I did not find the related system generator based design for this radio controller core. Is this IP core designed and generated manually?
Thanks,
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The radio_controller is a combination of custom Verilog (all the .v files) and a PLB slave template (all the .vhd files) generated by the Create and Import Peripheral Wizard (Start->Programs->...->EDK->Accessories). The radio_bridge core is all custom Verilog.
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