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It was mentioned in one of your e-mails that one of the reasons for long processing time is that PowerPC may be slow and hence to reduce processing time, perhaps one of the options is to move some operations to the FPGA from PowerPC. I want to ask you as to how does one achieve this ie. how to move the operations from PowerPC to the FPGA?
Thank you.
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There is no simple answer to this question; it depends entirely on what software bottleneck you're trying to overcome. For example, in our early MAC code, the packet checksum calculation was implemented in software. This was a very slow operation. We moved this calculation into the PHY hardware model and realized a huge speedup. In this case, we implemented the checksum calculation in the System Generator model for the PHY.
Similar gains were had from using the DMA engine in the Ethernet MAC to handle wired-wireless packet transfers.
A final example is an extension to the packet detector pcore. We needed a way to monitor the medium for idle periods of a certain length (for CMSA). Implementing this in software was very inefficient, requiring repeated calls to the RSSI read function. Instead, the packet detector monitors the RSSI signal (which it monitored anyway, for detecting packets) to track how long the medium is idle, then raises an interrupt to the PowerPC when this period exceeds some threshold. Again, this core is implemented in System Generator and connected to the PowerPC via the OPB (using sysgen2opb and the OPB Export Tool).
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