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Is it possible to use the MCH interface of xps_mch_emc to read from and write to the external SDRAM? I would like to use both the PLB interface and the MCH interface in the same design, thus the FPGA logic can read from and write to SDRAM directly without going through the PLB bus, while the Power PC can still access the SDRAM through PLB interface.
Is there any example on the MCH protocol?
Thanks.
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We've never tried this, but it might be doable.
Are you trying to use the SRAM on a V2P board, or DRAM on a Virtex-4 board? It would be much easier for the SRAM, where the memory controller is very simple, really only responsible for managing the pipeline latency for read/writes. You could instantiate two controllers (one on the PLB, the other tied to custom logic), then wrap these in simple mux'ing logic to select which controller's addess/data/control lines are connected to the IOBs.
For the DRAM on a Virtex-4 kit it would be a lot harder, since the memory controller is responsible for so much more (periodic refreshes, etc.).
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