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The convertor clock on the radio board is wired to the clock board directly via a twisted cable, in stead of using the clock signal from the FPGA.
what's is the purpose for this? Can I use the clock source from the FPGA?
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Clocks generated by the FPGA (especially when generated by a DCM) have much higher jitter than when sourced directly from an oscillator. Higher jitter in a sampling clock translates directly to lower SNR in the signal captured/generated by an ADC/DAC.
It is possible to drive the Radio Board ADC/DAC clocks from the FPGA. However it requires mounting a few 0402 resistors (R77 - R80) on the Radio Board.
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Thanks,
I wonder if I mount 0402 resistors on the radio board, do I need to remove the twisted cable?
and do all the reference designs support the convertor clock source from FPGA?
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I wonder if I mount 0402 resistors on the radio board, do I need to remove the twisted cable?
Yes, definitely. You don't want a drive fight between two clock sources.
and do all the reference designs support the convertor clock source from FPGA?
I believe so. The radio_bridge has two ports- converter_clock_in and converter_clock_out. converter_clock_in is used to clock IO registers for all the signals routed to/from the Radio Board. Typically it's connected to the 40MHz clock fed into the FPGA from the Clock Board. converter_clock_out is a copy of this signal driven to the daughtercard slot.
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I should also mention that the range of valid sampling frequencies is limited by the ADC/DACs on the Radio Board. The ADC operates in [1,65]MSps. The DAC range is wider, but depends on what DAC options you enable (PLL, interpolating filters, etc.). Our default configuration bypasses the DAC's integrated interpolation filters, giving a maximum input data rate of 160MSps. See the AD9777 datasheet for details.
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