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Hi,
I failed to repeat the lab3 - sweepingTx this evening. I actually also downloaded the solution from the website and still got the same result. The board seems not initialized (can not printing out message to the terminal), so I figured it could be the clock board and DCM configuration. I remember when we were doing this lab, we were instructed to change some setup in the bus interface or port window. I wanted to do the same thing but got the following message after I tried a lot of combinations:
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ERROR:PhysDesignRules:740 - Invalid DCM configuration. The DCM comp
dcm_0/dcm_0/Using_Virtex.DCM_INST has CLKFB signal driven by the CLKFX pin
which is not allowed.
ERROR:Pack:1642 - Errors in physical DRC.
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Anyway, could you please tell me how to setup those related signals so that the board can be reset properly? I use an FPGA board v1.1, a radio board v1.4, and no clock board. As indicated in the code and system configuration, I put the radio board onto daughter slot #2. I am not sure if this matters since the FPGA seem can not reset.
Thanks!!
P.S. I also met this compilation error. Do you have any idea why should we build for PPC405_1?
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ERROR:MDT - make failed for target "libs"
ERROR:MDT - Error while running "make" for processor ppc405_1...
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Your current boards don't have a clock board, which means the FPGA must use the 100MHz oscillator on the FPGA board for its internal clock, and for the radio board's sampling clocks. The hardware projects from the most recent workshop are designed for the final WARP hardware configuration, where the clock board provides these clock signals. I suggest looking at the lab exercises from our previous workshop (available here). These labs were built for hardware configured like your current boards.
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Thanks. I can repeat the lab 1 for sure. So that means we built a base system without using the clock board, am I right? I will try the link you gave.
Are we ok to use the WARPLab without the clock board? How about the OFDM reference design? Or should we re-compile all the source using a new base-system without support from clock board? I really appreciate your help.
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OFDM reference design v04 (the one currently posted) will work with your boards. The new reference design, which will require the clock board, will be posted soon.
For Base System Builder, we provide two XBDs. When BSB prompts you to select a board, you'll have two choices: "FPGA 1.2 / Radio 1.4" and "FPGA 1.2 / Radio 1.4 / Clock 1.0". The first will configure a system to use the FPGA's board 100MHz oscillator. The second configures it to use the clock board's 40MHz oscillator.
The WARPLab bitstream currently in the repository requires the clock board. We can generate one that uses the on-board oscillator; let me look into it.
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Thanks very much!
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murphpo wrote:
OFDM reference design v04 (the one currently posted) will work with your boards. The new reference design, which will require the clock board, will be posted soon.
For Base System Builder, we provide two XBDs. When BSB prompts you to select a board, you'll have two choices: "FPGA 1.2 / Radio 1.4" and "FPGA 1.2 / Radio 1.4 / Clock 1.0". The first will configure a system to use the FPGA's board 100MHz oscillator. The second configures it to use the clock board's 40MHz oscillator.
The WARPLab bitstream currently in the repository requires the clock board. We can generate one that uses the on-board oscillator; let me look into it.
When connecting the WARP kit and local computer using RJ45 Ethernet cable, should we connect them through a switch? Or can they be connected directly? I am wondering if we need the special "cross over" cable.
Thanks!
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Please see this previous post.
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The WARPLab bitstream for kits with 50MHz sampling is now in the repository.
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Thanks very much for all your help. I just got out from my screening exam, so I may have more time to play with the board. Right now I am making an effort to measure the sustainable data rate by the reference OFDM hardware PHY layer. Do you have any recommendation where to start? Is WARPLab a better option if I can do some encoding in MATLAB? I am also considering to compile the Sysgen model in ISE so the PAR report may give some number. Please give some advice. Thanks!
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We use iperf for end-to-end throughput tests. We routinely observe UDP streams achieving 60-80% of the raw PHY data rate (12Mbps for QPSK in SISO OFDM).
You can see the PAR reports for EDK projects; just open ./implementation/xflow.log in any EDK project. This file contains the logs for translate/map/par/bitgen, all of which are executed automatically by the EDK via xflow.
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Can I simply modify the modulation rate in csmaMAC.c to change the data rate? Do I need to change others? Thanks.
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In the latest reference designs, you can change the payload modulation scheme in csmamac.c. This affects the modulation rate of the full rate symbols in the packet (read more about the OFDM frame format).
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murphpo wrote:
In the latest reference designs, you can change the payload modulation scheme in csmamac.c. This affects the modulation rate of the full rate symbols in the packet (read more about the OFDM frame format).
Thank you very much!
I am wondering if the alamouti reference design is posted. For the current OFDM Reference Design v04, if we want to use 2 antennas in the spatial multiplexing MIMO way, how should we change the configurations to turn the radio boards on?
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We haven't created a reference design using the Alamouti OFDM core yet. I intend to, but it will probably be sometime after the holidays.
You should be able to enable MIMO mode in the current reference design with a call to warpmac_enableMIMOMode().
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Can I understand that warpmac_enableMIMOMode() activates the MAC layer functionality? Then I am still concerned how to configure the ports and bus interface in the Platform Studio for the MIMO IP core. Do you have a manual or writeup in the repository to tell us about the port property of your IP cores? I could not find one very specific to the OFDM MIMO core. Thanks again!
Happy Holidays!
Last edited by DQ A (2007-Dec-12 17:12:09)
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There is no MAC layer change for MIMO mode. The PHY provides a "bit-pipe" in either SISO or MIMO mode. WARPMAC does need to understand which mode is enabled in order to properly configure the PHY (for example, MIMO packets are shorter in time, since data is multiplexed across antennas). All of this is handled by the enableMIMOMode call.
The only documentation I've written for the OFDM core is already online. It's (obviously) still a work in progress. You can always see the full list of ports by looking at the MPD file for a pcore; /pcores/ofdm_txrx_mimo_vX/data/*.MPD in the case of the OFDM core in the reference design.
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The OFDM reference design v04 worked fine on my old WARP kits without clock board and with only one radio board.
However, the new kits I just got could not work with the reference design v07 and either of the two bit streams coming with the bundled CF (SISOCSMA and 2RADPING, at least I don't know if they are working fine or not). The new kit has a clock board and 2 radios on slot 2 &3. After setting them up as instructed, I ping the other PC. I can see the D3 on FPGA board and D3 on Radio board blinking. But the receiver side doesn't respond. This is similar to the situation another poster (jh) had described in another thread, except I have the new radio board without crystal. BTW the antenna is connected to port 1 on each of the radio board. In light of the problem jh met in his thread (http://warp.rice.edu/forums/viewtopic.php?id=190), I am wondering if my radio board also got configured wrong.
Without knowing if it will help, I copy the tera term pro's display in the following. The two kits behave the same except for the I/Qs are different.
Please give me some advice.
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Initializing WARPMAC...
Initializing controlStruct...complete!
Initializing LEDs...complete!
Initializing Interrupts...complete!
Enabling Exceptions...complete!
Initializing Ethernet...complete!
Initializing WARPPHY...
Initializing Radio Transmitter...
TxDCO: Applied values to radio 2 - I: 132 Q: 34
TxDCO: Applied values to radio 3 - I: 90 Q: 54
complete!
Initializing Radio Receiver...complete
Initializing OFDM Transmitter...complete!
Initializing OFDM Receiver...complete!
Initializing AGC...-19 - 32 - noise_estimate = 44
AGC BITSIN = 6
complete!
Initializing Packet Detection...complete!
end of warpphy init...
Debug Menu:
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I also noticed the difference between my old v1.1 board and the new v1.2 board. In case we use BSB to choose a board, do we have different definition files for them?
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The only differences between the board revisions is the built-in USB JTAG circuit and a few manufacturing-related tweaks. From the perspective of the EDK, the boards are identical.
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Thanks. Then if I plug in the old radio board with crystal on, the whole warp node will work with v04 bitstream, right?
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The v04 reference design will work with radios using local oscillators. This is actually the last reference design that will; every future design will required WARP nodes using the clock board.
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