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Hello,
I am considering AccelDSP for the PHY layer development purpose. In this context AccelDSP will generate synthesizable VHDL or Verilog, and creates a testbench for verification. After this I need to generate bit streams and download into the WARP FPGA platform. Our MAC functionality will be implemented on PPC using Xilinx EDK.
In the above mentioed design flow, do you see any problem or gap?
Along with this I do not find the place where we can use SysGen in our design. Are we making any mistake in our design process? Kindly suggest.
Thanks,
Atanu
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We have very limited experience with AccelDSP. We used it (briefly) after its initial Xilinx-branded release and found it to be extraordinarily frustrating. Ever since, we've stuck to pure Sysgen designs for PHY implementation. I suspect AccelDSP has improved since its release, but I don't know how much.
One thing to keep in mind with any PHY design flow- if you want to partition PHY/MAC between hardware/PPC, you need a PHY design enviornment that supports some kind of bus interface generation. In Sysgen/EDK 9.1 we use our sysgen2opb flow. Starting in version 10.1, Sysgen/EDK are set to support PLB46 peripheral generation directly from Sysgen models.
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