| 1 | ############################################################################
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| 2 | ## This system.ucf file is generated by Base System Builder based on the
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| 3 | ## settings in the selected Xilinx Board Definition file. Please add other
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| 4 | ## user constraints to this file based on customer design specifications.
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| 5 | ############################################################################
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| 6 |
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| 7 | Net sys_clk_pin LOC=AH21;
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| 8 | Net sys_clk_pin IOSTANDARD = LVTTL;
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| 9 | Net sys_rst_pin LOC=AM16;
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| 10 | Net sys_rst_pin IOSTANDARD = LVTTL;
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| 11 | ## System level constraints
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| 12 | Net sys_clk_pin TNM_NET = sys_clk_pin;
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| 13 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
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| 14 | Net sys_rst_pin TIG;
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| 15 | NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
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| 16 | NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
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| 17 | NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
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| 18 | TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;
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| 19 |
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| 20 | ## IO Devices constraints
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| 21 |
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| 22 | #### Module LEDs_4Bit constraints
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| 23 |
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| 24 | Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<0> LOC=AJ14;
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| 25 | Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<0> IOSTANDARD = LVTTL;
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| 26 | Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<1> LOC=AM13;
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| 27 | Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<1> IOSTANDARD = LVTTL;
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| 28 | Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<2> LOC=AR12;
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| 29 | Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<2> IOSTANDARD = LVTTL;
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| 30 | Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<3> LOC=AH13;
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| 31 | Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<3> IOSTANDARD = LVTTL;
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| 32 |
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| 33 | #### Module Push_Buttons_4bit constraints
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| 34 |
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| 35 | Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<0> LOC=AJ22;
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| 36 | Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<0> IOSTANDARD = LVTTL;
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| 37 | Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<1> LOC=AJ15;
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| 38 | Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<1> IOSTANDARD = LVTTL;
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| 39 | Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<2> LOC=AG18;
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| 40 | Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<2> IOSTANDARD = LVTTL;
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| 41 | Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<3> LOC=AG17;
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| 42 | Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<3> IOSTANDARD = LVTTL;
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| 43 |
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| 44 | #### Module RS232 constraints
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| 45 |
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| 46 | Net fpga_0_RS232_RX_pin LOC=AA29;
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| 47 | Net fpga_0_RS232_RX_pin IOSTANDARD = LVTTL;
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| 48 | Net fpga_0_RS232_TX_pin LOC=AA28;
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| 49 | Net fpga_0_RS232_TX_pin IOSTANDARD = LVTTL;
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| 50 |
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