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| 6 | <title>Base System Builder - FPGA Board v1.2</title> |
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| 13 | <a id="logo" href="http://warp.rice.edu/trac/"><img src="http://warp.rice.edu/images/warpLogo.jpg" alt="Rice University WARP - Wireless Open-Access Research Platform" height="45" width="285" /></a> |
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| 19 | </div> |
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| 20 | <div id="LessonContent"> |
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| 21 | <div class="LessonHeader"> |
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| 22 | <h1 class="LessonTitle">Base System Builder - FPGA Board v1.2</h1> |
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| 23 | </div> |
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| 24 | <div class="summary"> |
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| 25 | <p>This section describes the process of launching XPS and creating a simple hardware/software platform using Base System Builder. This section of the tutorial is specifically created for FPGA Board v1.2. Once you complete this section, skip to <strong>XPS Intro - Implementing the hardware design</strong>. Skip this section if you have FPGA Board v2.2.</p> |
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| 26 | </div> |
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| 27 | |
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| 28 | <div id="step_1" class="lessonStep top"> |
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| 29 | |
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| 30 | <div class="image"> |
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| 31 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215322293367.png" width="558" height="211"> |
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| 32 | </div> <p>Launch the Xilinx Platform Studio application.</p> |
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| 33 | </div> |
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| 34 | <div class="clear"></div> |
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| 35 | <div id="step_2" class="lessonStep top"> |
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| 36 | |
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| 37 | <div class="image"> |
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| 38 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215322383765.png" width="369" height="303"> |
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| 39 | </div> <p>Select Base System Builder to create a new project.</p> |
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| 40 | </div> |
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| 41 | <div class="clear"></div> |
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| 42 | <div id="step_3" class="lessonStep top"> |
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| 43 | |
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| 44 | <div class="image"> |
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| 45 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/BSBPath.png" width="407" height="245"> |
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| 46 | </div> <p>Enter a path for your project. Two key requirements:<br /> |
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| 47 | -The project file must be named 'system.xmp'<br /> |
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| 48 | -The project file must be saved to a folder with no spaces in its path - "C:\Documents and Settings\user\" will not work!</p> |
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| 49 | </div> |
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| 50 | <div class="clear"></div> |
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| 51 | <div id="step_4" class="lessonStep top"> |
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| 52 | |
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| 53 | <div class="image"> |
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| 54 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215323301511.png" width="508" height="725"> |
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| 55 | </div> <p>Choose the option for a new design.</p> |
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| 56 | </div> |
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| 57 | <div class="clear"></div> |
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| 58 | <div id="step_5" class="lessonStep top"> |
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| 59 | |
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| 60 | <div class="image"> |
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| 61 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215324564466.png" width="508" height="725"> |
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| 62 | </div> <p>Base System Builder supports many development boards, including the WARP hardware platform. For this exercise, choose the board named 'WARP FPGA Board' and select revision 'FPGA 1.2'.</p> |
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| 63 | </div> |
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| 64 | <div class="clear"></div> |
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| 65 | <div id="step_6" class="lessonStep top"> |
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| 66 | |
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| 67 | <div class="image"> |
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| 68 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215323375118.png" width="509" height="725"> |
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| 69 | </div> <p>The Xilinx EDK supports two embedded processors. The PowerPC processor is a "hard" processor core, embedded in the fabric of the Virtex-II Pro FPGA on the WARP FPGA board. MicroBlaze is a "soft" processor core, implemented in the FPGA fabric itself. For this exercise (and all WARP designs generally), select the PowerPC core.</p> |
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| 70 | </div> |
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| 71 | <div class="clear"></div> |
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| 72 | <div id="step_7" class="lessonStep top"> |
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| 73 | |
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| 74 | <div class="image"> |
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| 75 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/DOCM.png" width="507" height="705"> |
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| 76 | </div> <p>The clocking and memory architectures for EDK designs are very flexible. Base System Builder supports some simple clock/memory configurations. In more sophisticated designs, the clocking and memory options can be further customized by hand. For this exercise, select the clock frequencies and memory sizes shown above. </p> |
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| 77 | </div> |
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| 78 | <div class="clear"></div> |
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| 79 | <div id="step_8" class="lessonStep top"> |
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| 80 | |
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| 81 | <div class="image"> |
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| 82 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215530729043.png" width="509" height="725"> |
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| 83 | </div> <p>The next few screens present a list of available I/O devices. Each device corresponds to an off-chip interface on the WARP FPGA board. Each device can be enaled/disabled using its checkbox. For this exercise, choose the peripherals as follows:</p> |
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| 84 | |
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| 85 | |
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| 86 | <p><strong>Enabled:</strong><br /> |
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| 87 | - User I/O (with 'Use interrupt enabled)<br /> |
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| 88 | - rs232 (configured for 57600 bps)</p> |
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| 89 | |
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| 90 | |
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| 91 | <p><strong>Disabled:</strong><br /> |
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| 92 | - sysace_compactflash<br /> |
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| 93 | - eeprom_controller<br /> |
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| 94 | - Ethernet_MAC<br /> |
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| 95 | - user_io_board_controller_slot1<br /> |
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| 96 | - SRAM0 / SRAM1</p> |
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| 97 | </div> |
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| 98 | <div class="clear"></div> |
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| 99 | <div id="step_9" class="lessonStep top"> |
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| 100 | |
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| 101 | <div class="image"> |
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| 102 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215324622800.png" width="509" height="725"> |
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| 103 | </div> |
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| 104 | </div> |
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| 105 | <div class="clear"></div> |
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| 106 | <div id="step_10" class="lessonStep top"> |
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| 107 | |
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| 108 | <div class="image"> |
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| 109 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215324643209.png" width="507" height="723"> |
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| 110 | </div> <p>After configuring off-chip devices, you now configure on-chip peripheral cores. By default, an internal RAM block is enabled. For this exercise, click 'Remove' to omit this core from the design.</p> |
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| 111 | </div> |
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| 112 | <div class="clear"></div> |
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| 113 | <div id="step_11" class="lessonStep top"> |
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| 114 | |
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| 115 | <div class="image"> |
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| 116 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215631264826.png" width="509" height="725"> |
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| 117 | </div> <p>For user applications running in the PowerPC processor, the EDK tools can map the WARP FPGA board's serial port (the core named 'rs232' here) to the STDIN/STDOUT conventions. This allows funcitons like printf() to work normally, using an external terminal emulator as the PowerPC's display and keyboard.</p> |
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| 118 | |
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| 119 | |
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| 120 | <p>XPS can also create sample software projects which exercise the memory and peripheral devices in your hardware design. For this exercise, disable both example proejcts (you'll create a new software project later).</p> |
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| 121 | </div> |
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| 122 | <div class="clear"></div> |
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| 123 | <div id="step_12" class="lessonStep top"> |
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| 124 | |
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| 125 | <div class="image"> |
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| 126 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215324692690.png" width="507" height="725"> |
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| 127 | </div> <p>Base System Builder assigns default memory addresses to each memory and memory-mapped peripheral device. The addresses in your project may vary from those shown here. In general, the defaults selected by BSB work fine.</p> |
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| 128 | </div> |
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| 129 | <div class="clear"></div> |
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| 130 | <div id="step_13" class="lessonStep top"> |
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| 131 | |
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| 132 | <div class="image"> |
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| 133 | <a href="images/Base_System_Builder_-_FPGA_Board_v1/media_1215631451171_lg.png" class="image" target="_blank"><img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215631451171.png" width="580" height="310"></a> |
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| 134 | <div class="caption"><a href="images/Base_System_Builder_-_FPGA_Board_v1/media_1215631451171_lg.png" target="_blank">Zoom</a></div> |
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| 135 | </div> <p>When Base System Builder finishes, XPS will open the resulting project. The remaining sections of this exercise describe how to use this interface to customize and test your hardware & software platform.</p> |
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| 136 | </div> |
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| 143 | <td class="lessonNav_Left"><a href="Requirements___Setup.html"><< Requirements & Setup</a></td> |
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| 145 | <td class="lessonNav_Right"><a href="Base_System_Builder_-_FPGA_Board_v2.html">Base System Builder - FPGA Board v2.2 >></a> </td> |
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