[1766] | 1 | //---------------------------------------------------------------------------- |
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| 2 | // user_logic.vhd - module |
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| 3 | //---------------------------------------------------------------------------- |
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| 4 | // |
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| 5 | // *************************************************************************** |
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| 6 | // ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. ** |
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| 7 | // ** ** |
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| 8 | // ** Xilinx, Inc. ** |
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| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
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| 22 | // ** ** |
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| 23 | // *************************************************************************** |
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| 24 | // |
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| 25 | //---------------------------------------------------------------------------- |
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| 26 | // Filename: user_logic.vhd |
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| 27 | // Version: 3.00.a |
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| 28 | // Description: User logic module. |
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| 29 | // Date: Wed Jul 04 20:55:56 2012 (by Create and Import Peripheral Wizard) |
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| 30 | // Verilog Standard: Verilog-2001 |
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| 31 | //---------------------------------------------------------------------------- |
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| 32 | // Naming Conventions: |
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| 33 | // active low signals: "*_n" |
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| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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| 35 | // reset signals: "rst", "rst_n" |
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| 36 | // generics: "C_*" |
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| 37 | // user defined types: "*_TYPE" |
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| 38 | // state machine next state: "*_ns" |
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| 39 | // state machine current state: "*_cs" |
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| 40 | // combinatorial signals: "*_com" |
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| 41 | // pipelined or register delay signals: "*_d#" |
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| 42 | // counter signals: "*cnt*" |
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| 43 | // clock enable signals: "*_ce" |
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| 44 | // internal version of output port: "*_i" |
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| 45 | // device pins: "*_pin" |
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| 46 | // ports: "- Names begin with Uppercase" |
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| 47 | // processes: "*_PROCESS" |
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| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 49 | //---------------------------------------------------------------------------- |
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| 50 | |
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| 51 | module user_logic |
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| 52 | ( |
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| 53 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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| 54 | |
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| 55 | //I/O for MAX2829 pins |
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| 56 | output RFA_TxEn, |
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| 57 | output RFB_TxEn, |
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| 58 | output RFC_TxEn, |
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| 59 | output RFD_TxEn, |
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| 60 | |
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| 61 | output RFA_RxEn, |
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| 62 | output RFB_RxEn, |
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| 63 | output RFC_RxEn, |
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| 64 | output RFD_RxEn, |
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| 65 | |
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| 66 | output RFA_RxHP, |
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| 67 | output RFB_RxHP, |
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| 68 | output RFC_RxHP, |
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| 69 | output RFD_RxHP, |
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| 70 | |
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| 71 | output RFA_SHDN, |
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| 72 | output RFB_SHDN, |
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| 73 | output RFC_SHDN, |
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| 74 | output RFD_SHDN, |
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| 75 | |
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| 76 | output RFA_SPI_SCLK, |
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| 77 | output RFB_SPI_SCLK, |
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| 78 | output RFC_SPI_SCLK, |
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| 79 | output RFD_SPI_SCLK, |
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| 80 | |
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| 81 | output RFA_SPI_MOSI, |
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| 82 | output RFB_SPI_MOSI, |
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| 83 | output RFC_SPI_MOSI, |
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| 84 | output RFD_SPI_MOSI, |
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| 85 | |
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| 86 | output RFA_SPI_CSn, |
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| 87 | output RFB_SPI_CSn, |
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| 88 | output RFC_SPI_CSn, |
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| 89 | output RFD_SPI_CSn, |
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| 90 | |
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| 91 | output [0:6] RFA_B, |
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| 92 | output [0:6] RFB_B, |
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| 93 | output [0:6] RFC_B, |
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| 94 | output [0:6] RFD_B, |
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| 95 | |
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| 96 | input RFA_LD, |
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| 97 | input RFB_LD, |
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| 98 | input RFC_LD, |
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| 99 | input RFD_LD, |
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| 100 | |
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| 101 | //Outputs to PA and ant switch pins |
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| 102 | output RFA_PAEn_24, |
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| 103 | output RFB_PAEn_24, |
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| 104 | output RFC_PAEn_24, |
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| 105 | output RFD_PAEn_24, |
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| 106 | |
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| 107 | output RFA_PAEn_5, |
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| 108 | output RFB_PAEn_5, |
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| 109 | output RFC_PAEn_5, |
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| 110 | output RFD_PAEn_5, |
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| 111 | |
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| 112 | output [0:1] RFA_AntSw, |
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| 113 | output [0:1] RFB_AntSw, |
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| 114 | output [0:1] RFC_AntSw, |
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| 115 | output [0:1] RFD_AntSw, |
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| 116 | |
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| 117 | //I/O for user logic to control state from hardware |
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| 118 | input usr_RFA_TxEn, |
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| 119 | input usr_RFB_TxEn, |
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| 120 | input usr_RFC_TxEn, |
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| 121 | input usr_RFD_TxEn, |
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| 122 | |
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| 123 | input usr_RFA_RxEn, |
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| 124 | input usr_RFB_RxEn, |
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| 125 | input usr_RFC_RxEn, |
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| 126 | input usr_RFD_RxEn, |
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| 127 | |
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| 128 | input usr_RFA_RxHP, |
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| 129 | input usr_RFB_RxHP, |
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| 130 | input usr_RFC_RxHP, |
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| 131 | input usr_RFD_RxHP, |
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| 132 | |
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| 133 | input usr_RFA_SHDN, |
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| 134 | input usr_RFB_SHDN, |
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| 135 | input usr_RFC_SHDN, |
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| 136 | input usr_RFD_SHDN, |
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| 137 | |
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| 138 | input [0:1] usr_RFA_RxGainRF, |
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| 139 | input [0:1] usr_RFB_RxGainRF, |
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| 140 | input [0:1] usr_RFC_RxGainRF, |
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| 141 | input [0:1] usr_RFD_RxGainRF, |
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| 142 | |
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| 143 | input [0:4] usr_RFA_RxGainBB, |
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| 144 | input [0:4] usr_RFB_RxGainBB, |
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| 145 | input [0:4] usr_RFC_RxGainBB, |
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| 146 | input [0:4] usr_RFD_RxGainBB, |
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| 147 | |
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| 148 | input [0:5] usr_RFA_TxGain, |
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| 149 | input [0:5] usr_RFB_TxGain, |
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| 150 | input [0:5] usr_RFC_TxGain, |
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| 151 | input [0:5] usr_RFD_TxGain, |
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| 152 | |
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| 153 | input usr_SPI_ctrlSrc, |
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| 154 | input usr_SPI_go, |
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| 155 | output usr_SPI_active, |
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| 156 | input [0: 3] usr_SPI_rfsel, |
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| 157 | input [0: 3] usr_SPI_regaddr, |
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| 158 | input [0:13] usr_SPI_regdata, |
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| 159 | |
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| 160 | output usr_RFA_PHYStart, |
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| 161 | output usr_RFB_PHYStart, |
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| 162 | output usr_RFC_PHYStart, |
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| 163 | output usr_RFD_PHYStart, |
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| 164 | |
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| 165 | output usr_any_PHYStart, |
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| 166 | |
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| 167 | output usr_RFA_statLED_Tx, |
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| 168 | output usr_RFA_statLED_Rx, |
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| 169 | output usr_RFB_statLED_Tx, |
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| 170 | output usr_RFB_statLED_Rx, |
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| 171 | output usr_RFC_statLED_Tx, |
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| 172 | output usr_RFC_statLED_Rx, |
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| 173 | output usr_RFD_statLED_Tx, |
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| 174 | output usr_RFD_statLED_Rx, |
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| 175 | |
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| 176 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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| 177 | |
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| 178 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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| 179 | // -- Bus protocol ports, do not add to or delete |
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| 180 | input Bus2IP_Clk, |
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| 181 | input Bus2IP_Reset, |
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| 182 | input [0 : C_SLV_DWIDTH-1] Bus2IP_Data, |
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| 183 | input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE, |
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| 184 | input [0 : C_NUM_REG-1] Bus2IP_RdCE, |
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| 185 | input [0 : C_NUM_REG-1] Bus2IP_WrCE, |
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| 186 | output [0 : C_SLV_DWIDTH-1] IP2Bus_Data, |
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| 187 | output IP2Bus_RdAck, |
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| 188 | output IP2Bus_WrAck, |
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| 189 | output IP2Bus_Error |
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| 190 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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| 191 | ); // user_logic |
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| 192 | |
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| 193 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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| 194 | // --USER parameters added here |
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| 195 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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| 196 | |
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| 197 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 198 | // -- Bus protocol parameters, do not add to or delete |
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| 199 | parameter C_SLV_DWIDTH = 32; |
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| 200 | parameter C_NUM_REG = 64; |
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| 201 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 202 | |
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| 203 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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| 204 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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| 205 | |
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| 206 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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| 207 | // -- Bus protocol ports, do not add to or delete |
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| 208 | /* |
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| 209 | input Bus2IP_Clk; |
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| 210 | input Bus2IP_Reset; |
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| 211 | input [0 : C_SLV_DWIDTH-1] Bus2IP_Data; |
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| 212 | input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE; |
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| 213 | input [0 : C_NUM_REG-1] Bus2IP_RdCE; |
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| 214 | input [0 : C_NUM_REG-1] Bus2IP_WrCE; |
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| 215 | output [0 : C_SLV_DWIDTH-1] IP2Bus_Data; |
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| 216 | output IP2Bus_RdAck; |
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| 217 | output IP2Bus_WrAck; |
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| 218 | output IP2Bus_Error; |
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| 219 | */ |
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| 220 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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| 221 | |
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| 222 | //---------------------------------------------------------------------------- |
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| 223 | // Implementation |
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| 224 | //---------------------------------------------------------------------------- |
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| 225 | |
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| 226 | // --USER nets declarations added here, as needed for user logic |
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| 227 | `define MAX2829_REG0_ON_RESET 14'b01000101000000 |
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| 228 | `define MAX2829_REG1_ON_RESET 14'b00000011001010 |
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| 229 | `define MAX2829_REG2_ON_RESET 14'b01000000000111 |
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| 230 | `define MAX2829_REG3_ON_RESET 14'b11000010100010 |
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| 231 | `define MAX2829_REG4_ON_RESET 14'b01110111011101 |
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| 232 | `define MAX2829_REG5_ON_RESET 14'b01100000100100 |
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| 233 | `define MAX2829_REG6_ON_RESET 14'b01110000000000 |
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| 234 | `define MAX2829_REG7_ON_RESET 14'b00000000101010 |
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| 235 | `define MAX2829_REG8_ON_RESET 14'b00000000100101 |
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| 236 | `define MAX2829_REG9_ON_RESET 14'b00001000000000 |
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| 237 | `define MAX2829_REGA_ON_RESET 14'b00001111000000 |
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| 238 | `define MAX2829_REGB_ON_RESET 14'b00000001111111 |
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| 239 | `define MAX2829_REGC_ON_RESET 14'b00000000000000 |
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| 240 | |
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| 241 | `define TXTIMING_REG_ON_RESET 32'h401000F0 //Sane default Tx Timing values |
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| 242 | `define TXGAINS_REG_ON_RESET 32'h32323232 //Tx Gain targets = 50 |
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| 243 | `define CLKDIV_GAINTIMING_REG_ON_RESET 32'h00004F22 //Gain step=0xF, time step=4, clk divs = 2 |
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| 244 | |
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| 245 | // Nets for user logic slave model s/w accessible register example |
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| 246 | reg [0 : C_SLV_DWIDTH-1] slv_reg0; |
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| 247 | reg [0 : C_SLV_DWIDTH-1] slv_reg1; |
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| 248 | reg [0 : C_SLV_DWIDTH-1] slv_reg2; |
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| 249 | reg [0 : C_SLV_DWIDTH-1] slv_reg3; |
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| 250 | reg [0 : C_SLV_DWIDTH-1] slv_reg4; |
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| 251 | reg [0 : C_SLV_DWIDTH-1] slv_reg5; |
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| 252 | reg [0 : C_SLV_DWIDTH-1] slv_reg6; |
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| 253 | reg [0 : C_SLV_DWIDTH-1] slv_reg7; |
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| 254 | reg [0 : C_SLV_DWIDTH-1] slv_reg8; |
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| 255 | reg [0 : C_SLV_DWIDTH-1] slv_reg9; |
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| 256 | reg [0 : C_SLV_DWIDTH-1] slv_reg10; |
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| 257 | |
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| 258 | wire [0 : 10] slv_reg_write_sel; |
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| 259 | wire [0 : 63] slv_reg_read_sel; |
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| 260 | reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data; |
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| 261 | wire slv_read_ack; |
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| 262 | wire slv_write_ack; |
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| 263 | integer byte_index, bit_index; |
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| 264 | |
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| 265 | |
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| 266 | wire slv_write_ack_normalRegisters; |
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| 267 | |
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| 268 | wire [0:31] status_reg; |
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| 269 | |
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| 270 | //Use Verilog array-of-arrays syntax for the register banks to mirror MAX2829 internal registers |
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| 271 | // RFx_MAX2829_mirrorRegs[N] maps to MAX2829 reg N, for N=[0x0, 0xC] |
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| 272 | // All registers are 14 bits in the MAX2829 |
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| 273 | reg [0:13] RFA_MAX2829_mirrorRegs [0:12]; |
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| 274 | reg [0:13] RFB_MAX2829_mirrorRegs [0:12]; |
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| 275 | reg [0:13] RFC_MAX2829_mirrorRegs [0:12]; |
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| 276 | reg [0:13] RFD_MAX2829_mirrorRegs [0:12]; |
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| 277 | |
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| 278 | wire RFA_TxEn_ctrlSrc, RFB_TxEn_ctrlSrc, RFC_TxEn_ctrlSrc, RFD_TxEn_ctrlSrc; |
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| 279 | wire RFA_RxEn_ctrlSrc, RFB_RxEn_ctrlSrc, RFC_RxEn_ctrlSrc, RFD_RxEn_ctrlSrc; |
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| 280 | wire RFA_RxHP_ctrlSrc, RFB_RxHP_ctrlSrc, RFC_RxHP_ctrlSrc, RFD_RxHP_ctrlSrc; |
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| 281 | wire RFA_SHDN_ctrlSrc, RFB_SHDN_ctrlSrc, RFC_SHDN_ctrlSrc, RFD_SHDN_ctrlSrc; |
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| 282 | wire RFA_TxGain_ctrlSrc, RFB_TxGain_ctrlSrc, RFC_TxGain_ctrlSrc, RFD_TxGain_ctrlSrc; |
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| 283 | wire RFA_RxGain_ctrlSrc, RFB_RxGain_ctrlSrc, RFC_RxGain_ctrlSrc, RFD_RxGain_ctrlSrc; |
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| 284 | |
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| 285 | wire RFA_TxEn_sw, RFB_TxEn_sw, RFC_TxEn_sw, RFD_TxEn_sw; |
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| 286 | wire RFA_RxEn_sw, RFB_RxEn_sw, RFC_RxEn_sw, RFD_RxEn_sw; |
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| 287 | wire RFA_RxHP_sw, RFB_RxHP_sw, RFC_RxHP_sw, RFD_RxHP_sw; |
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| 288 | wire RFA_SHDN_sw, RFB_SHDN_sw, RFC_SHDN_sw, RFD_SHDN_sw; |
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| 289 | |
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| 290 | wire RFA_PAEn, RFB_PAEn, RFC_PAEn, RFD_PAEn; |
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| 291 | |
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| 292 | wire [0:7] TxTiming_dly_TxGainRamp, TxTiming_dly_PowerAmpEn, TxTiming_dly_TxEn, TxTiming_dly_startPHY; |
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| 293 | |
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| 294 | wire [0:3] TxGainRamp_gainStep, TxGainRamp_timeStep; |
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| 295 | |
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| 296 | wire [0:5] RFA_TxGain_sw, RFB_TxGain_sw, RFC_TxGain_sw, RFD_TxGain_sw; |
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| 297 | wire [0:4] RFA_RxGainBB_sw, RFB_RxGainBB_sw, RFC_RxGainBB_sw, RFD_RxGainBB_sw; |
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| 298 | wire [0:1] RFA_RxGainRF_sw, RFB_RxGainRF_sw, RFC_RxGainRF_sw, RFD_RxGainRF_sw; |
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| 299 | |
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| 300 | wire [0:5] RFA_TxGain_target, RFB_TxGain_target, RFC_TxGain_target, RFD_TxGain_target; |
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| 301 | wire [0:5] RFA_TxGain_ramped, RFB_TxGain_ramped, RFC_TxGain_ramped, RFD_TxGain_ramped; |
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| 302 | |
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| 303 | wire [0:4] RFA_RxGainBB, RFB_RxGainBB, RFC_RxGainBB, RFD_RxGainBB; |
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| 304 | wire [0:1] RFA_RxGainRF, RFB_RxGainRF, RFC_RxGainRF, RFD_RxGainRF; |
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| 305 | |
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| 306 | wire [0:2] spi_clk_div_sel; |
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| 307 | wire [0:1] txTiming_clk_div_sel; |
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| 308 | |
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| 309 | wire [0: 3] spi_rfsel_mask_sw; |
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| 310 | wire [0: 3] spi_rfsel_mask; |
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| 311 | wire [0:13] spi_tx_regdata; |
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| 312 | wire [0: 3] spi_tx_regaddr; |
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| 313 | wire spi_go; |
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| 314 | |
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| 315 | wire spi_tx_reg_write; |
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| 316 | wire spi_xfer_done; |
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| 317 | |
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| 318 | wire RFA_txStart, RFB_txStart, RFC_txStart, RFD_txStart; |
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| 319 | |
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| 320 | wire RFA_MAX2829_Reset, RFB_MAX2829_Reset, RFC_MAX2829_Reset, RFD_MAX2829_Reset; |
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| 321 | |
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| 322 | // Slave register write process; only implemented for RW and WO registers |
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| 323 | always @( posedge Bus2IP_Clk ) |
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| 324 | begin: SLAVE_REG_WRITE_PROC |
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| 325 | if ( Bus2IP_Reset == 1 ) |
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| 326 | begin |
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| 327 | slv_reg0 <= 0; //All zeros on reset- Tx/Rx disabled, SHDN (active low) enabled |
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| 328 | slv_reg1 <= `TXTIMING_REG_ON_RESET; |
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| 329 | slv_reg2 <= `TXGAINS_REG_ON_RESET; |
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| 330 | slv_reg3 <= 0; |
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| 331 | slv_reg4 <= `CLKDIV_GAINTIMING_REG_ON_RESET; |
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| 332 | slv_reg5 <= 0; |
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| 333 | slv_reg6 <= 0; |
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| 334 | slv_reg7 <= 0; |
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| 335 | slv_reg8 <= 0; |
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| 336 | slv_reg9 <= 0; |
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| 337 | slv_reg10 <= 0; |
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| 338 | end |
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| 339 | else |
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| 340 | case ( slv_reg_write_sel ) |
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| 341 | 11'b10000000000 : |
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| 342 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 343 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 344 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 345 | slv_reg0[bit_index] <= Bus2IP_Data[bit_index]; |
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| 346 | 11'b01000000000 : |
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| 347 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 348 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 349 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 350 | slv_reg1[bit_index] <= Bus2IP_Data[bit_index]; |
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| 351 | 11'b00100000000 : |
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| 352 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 353 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 354 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 355 | slv_reg2[bit_index] <= Bus2IP_Data[bit_index]; |
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| 356 | 11'b00010000000 : |
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| 357 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 358 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 359 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 360 | slv_reg3[bit_index] <= Bus2IP_Data[bit_index]; |
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| 361 | 11'b00001000000 : |
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| 362 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 363 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 364 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 365 | slv_reg4[bit_index] <= Bus2IP_Data[bit_index]; |
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| 366 | 11'b00000100000 : |
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| 367 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 368 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 369 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 370 | slv_reg5[bit_index] <= Bus2IP_Data[bit_index]; |
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| 371 | 11'b00000010000 : |
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| 372 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 373 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 374 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 375 | slv_reg6[bit_index] <= Bus2IP_Data[bit_index]; |
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| 376 | 11'b00000001000 : |
---|
| 377 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 378 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 379 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
| 380 | slv_reg7[bit_index] <= Bus2IP_Data[bit_index]; |
---|
| 381 | 11'b00000000100 : |
---|
| 382 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 383 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 384 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
| 385 | slv_reg8[bit_index] <= Bus2IP_Data[bit_index]; |
---|
| 386 | 11'b00000000010 : |
---|
| 387 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 388 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 389 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
| 390 | slv_reg9[bit_index] <= Bus2IP_Data[bit_index]; |
---|
| 391 | 11'b00000000001 : |
---|
| 392 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
---|
| 393 | if ( Bus2IP_BE[byte_index] == 1 ) |
---|
| 394 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
---|
| 395 | slv_reg10[bit_index] <= Bus2IP_Data[bit_index]; |
---|
| 396 | default : ; |
---|
| 397 | endcase |
---|
| 398 | |
---|
| 399 | end // SLAVE_REG_WRITE_PROC |
---|
| 400 | |
---|
| 401 | // Slave model register read mux |
---|
| 402 | // All registers can be read |
---|
| 403 | always @* |
---|
| 404 | begin: SLAVE_REG_READ_PROC |
---|
| 405 | case ( slv_reg_read_sel ) |
---|
| 406 | 64'b1000000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg0; |
---|
| 407 | 64'b0100000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg1; |
---|
| 408 | 64'b0010000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg2; |
---|
| 409 | 64'b0001000000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg3; |
---|
| 410 | 64'b0000100000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg4; |
---|
| 411 | 64'b0000010000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg5; |
---|
| 412 | 64'b0000001000000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg6; |
---|
| 413 | 64'b0000000100000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg7; |
---|
| 414 | 64'b0000000010000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg8; |
---|
| 415 | 64'b0000000001000000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg9; |
---|
| 416 | 64'b0000000000100000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= slv_reg10; |
---|
| 417 | 64'b0000000000010000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= status_reg; |
---|
| 418 | 64'b0000000000001000000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[0]}; |
---|
| 419 | 64'b0000000000000100000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[1]}; |
---|
| 420 | 64'b0000000000000010000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[2]}; |
---|
| 421 | 64'b0000000000000001000000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[3]}; |
---|
| 422 | 64'b0000000000000000100000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[4]}; |
---|
| 423 | 64'b0000000000000000010000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[5]}; |
---|
| 424 | 64'b0000000000000000001000000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[6]}; |
---|
| 425 | 64'b0000000000000000000100000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[7]}; |
---|
| 426 | 64'b0000000000000000000010000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[8]}; |
---|
| 427 | 64'b0000000000000000000001000000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[9]}; |
---|
| 428 | 64'b0000000000000000000000100000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[10]}; |
---|
| 429 | 64'b0000000000000000000000010000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[11]}; |
---|
| 430 | 64'b0000000000000000000000001000000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFA_MAX2829_mirrorRegs[12]}; |
---|
| 431 | 64'b0000000000000000000000000100000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[0]}; |
---|
| 432 | 64'b0000000000000000000000000010000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[1]}; |
---|
| 433 | 64'b0000000000000000000000000001000000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[2]}; |
---|
| 434 | 64'b0000000000000000000000000000100000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[3]}; |
---|
| 435 | 64'b0000000000000000000000000000010000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[4]}; |
---|
| 436 | 64'b0000000000000000000000000000001000000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[5]}; |
---|
| 437 | 64'b0000000000000000000000000000000100000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[6]}; |
---|
| 438 | 64'b0000000000000000000000000000000010000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[7]}; |
---|
| 439 | 64'b0000000000000000000000000000000001000000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[8]}; |
---|
| 440 | 64'b0000000000000000000000000000000000100000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[9]}; |
---|
| 441 | 64'b0000000000000000000000000000000000010000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[10]}; |
---|
| 442 | 64'b0000000000000000000000000000000000001000000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[11]}; |
---|
| 443 | 64'b0000000000000000000000000000000000000100000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFB_MAX2829_mirrorRegs[12]}; |
---|
| 444 | 64'b0000000000000000000000000000000000000010000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[0]}; |
---|
| 445 | 64'b0000000000000000000000000000000000000001000000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[1]}; |
---|
| 446 | 64'b0000000000000000000000000000000000000000100000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[2]}; |
---|
| 447 | 64'b0000000000000000000000000000000000000000010000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[3]}; |
---|
| 448 | 64'b0000000000000000000000000000000000000000001000000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[4]}; |
---|
| 449 | 64'b0000000000000000000000000000000000000000000100000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[5]}; |
---|
| 450 | 64'b0000000000000000000000000000000000000000000010000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[6]}; |
---|
| 451 | 64'b0000000000000000000000000000000000000000000001000000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[7]}; |
---|
| 452 | 64'b0000000000000000000000000000000000000000000000100000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[8]}; |
---|
| 453 | 64'b0000000000000000000000000000000000000000000000010000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[9]}; |
---|
| 454 | 64'b0000000000000000000000000000000000000000000000001000000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[10]}; |
---|
| 455 | 64'b0000000000000000000000000000000000000000000000000100000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[11]}; |
---|
| 456 | 64'b0000000000000000000000000000000000000000000000000010000000000000 : slv_ip2bus_data <= {18'b0, RFC_MAX2829_mirrorRegs[12]}; |
---|
| 457 | 64'b0000000000000000000000000000000000000000000000000001000000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[0]}; |
---|
| 458 | 64'b0000000000000000000000000000000000000000000000000000100000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[1]}; |
---|
| 459 | 64'b0000000000000000000000000000000000000000000000000000010000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[2]}; |
---|
| 460 | 64'b0000000000000000000000000000000000000000000000000000001000000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[3]}; |
---|
| 461 | 64'b0000000000000000000000000000000000000000000000000000000100000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[4]}; |
---|
| 462 | 64'b0000000000000000000000000000000000000000000000000000000010000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[5]}; |
---|
| 463 | 64'b0000000000000000000000000000000000000000000000000000000001000000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[6]}; |
---|
| 464 | 64'b0000000000000000000000000000000000000000000000000000000000100000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[7]}; |
---|
| 465 | 64'b0000000000000000000000000000000000000000000000000000000000010000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[8]}; |
---|
| 466 | 64'b0000000000000000000000000000000000000000000000000000000000001000 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[9]}; |
---|
| 467 | 64'b0000000000000000000000000000000000000000000000000000000000000100 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[10]}; |
---|
| 468 | 64'b0000000000000000000000000000000000000000000000000000000000000010 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[11]}; |
---|
| 469 | 64'b0000000000000000000000000000000000000000000000000000000000000001 : slv_ip2bus_data <= {18'b0, RFD_MAX2829_mirrorRegs[12]}; |
---|
| 470 | default : slv_ip2bus_data <= 0; |
---|
| 471 | endcase |
---|
| 472 | |
---|
| 473 | end // SLAVE_REG_READ_PROC |
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| 474 | |
---|
| 475 | /* Address map: |
---|
| 476 | HDL is coded [MSB:LSB] = [0:31] |
---|
| 477 | regX[ 0] maps to 0x80000000 in C driver |
---|
| 478 | regX[31] maps to 0x00000001 in C driver |
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| 479 | |
---|
| 480 | 0: RW: MAX2829 control signals and control source (sw vs. hw) |
---|
| 481 | Mask for RFA: 0x000000FF |
---|
| 482 | Mask for RFB: 0x0000FF00 |
---|
| 483 | Mask for RFC: 0x00FF0000 |
---|
| 484 | Mask for RFD: 0xFF000000 |
---|
| 485 | [ 0: 3] = RFD Control: {TxEn, RxEn, RxHP, SHDN} |
---|
| 486 | [ 4: 7] = RFD Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) |
---|
| 487 | [ 8:11] = RFC Control: {TxEn, RxEn, RxHP, SHDN} |
---|
| 488 | [12:15] = RFC Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) |
---|
| 489 | [16:19] = RFB Control: {TxEn, RxEn, RxHP, SHDN} |
---|
| 490 | [20:23] = RFB Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) |
---|
| 491 | [24:27] = RFA Control: {TxEn, RxEn, RxHP, SHDN} |
---|
| 492 | [28:31] = RFA Control Source: {TxEn, RxEn, RxHP, SHDN} (0=register, 1=usr_ port) |
---|
| 493 | |
---|
| 494 | 1: RW: Tx Timing |
---|
| 495 | Shared by all RF interfaces |
---|
| 496 | [ 0: 7] = Delay before Tx VGA ramp start 0xFF000000 |
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| 497 | [ 8:15] = Delay before PA enable 0x00FF0000 |
---|
| 498 | [16:23] = Delay before MAX2829 TxEn assertion 0x0000FF00 |
---|
| 499 | [24:31] = Delay before usr_startPHY assertion 0x000000FF |
---|
| 500 | |
---|
| 501 | 2: RW: Tx Gains |
---|
| 502 | [ 0] = RF D Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x80000000 |
---|
| 503 | [ 1] = Reserved |
---|
| 504 | [ 2: 7] = RF D Tx Gain 0x3F000000 |
---|
| 505 | [ 8] = RF C Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00800000 |
---|
| 506 | [ 9] = Reserved |
---|
| 507 | [10:15] = RF C Tx Gain 0x003F0000 |
---|
| 508 | [ 16] = RF B Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00008000 |
---|
| 509 | [ 17] = Reserved |
---|
| 510 | [18:23] = RF B Tx Gain 0x00003F00 |
---|
| 511 | [ 24] = RF A Tx Gain ctrl soruce (0=register, 1=usr_ port) 0x00000080 |
---|
| 512 | [ 25] = Reserved |
---|
| 513 | [26:31] = RF A Tx Gain 0x0000003F |
---|
| 514 | |
---|
| 515 | 3: RW: Rx gains |
---|
| 516 | [ 0] = RFD Rx gain ctrl source (0=register values, 1=usr_ ports) |
---|
| 517 | [ 1: 2] = RFD Rx RF Gain |
---|
| 518 | [ 3: 7] = RFD Rx BB Gain |
---|
| 519 | [ 8] = RFC Rx gain ctrl source (0=register values, 1=usr_ ports) |
---|
| 520 | [ 9:10] = RFC Rx RF Gain |
---|
| 521 | [11:15] = RFC Rx BB Gain |
---|
| 522 | [ 16] = RFB Rx gain ctrl source (0=register values, 1=usr_ ports) |
---|
| 523 | [17:18] = RFB Rx RF Gain |
---|
| 524 | [19:23] = RFB Rx BB Gain |
---|
| 525 | [ 24] = RFA Rx gain ctrl source (0=register values, 1=usr_ ports) |
---|
| 526 | [25:26] = RFA Rx RF Gain |
---|
| 527 | [27:31] = RFA Rx BB Gain |
---|
| 528 | |
---|
| 529 | 4: RW: Clock dividers & Tx gain ramp config |
---|
| 530 | [16:19] = Tx VGA ramp time step 0x0000F000 |
---|
| 531 | [20:23] = Tx VGA ramp gain step 0x00000F00 |
---|
| 532 | [ 24] = Reserved 0x00000080 |
---|
| 533 | [25:27] = SPI clock divider 0x00000070 |
---|
| 534 | [28:29] = Reserved 0x0000000C |
---|
| 535 | [30:31] = TxTiming clock divider 0x00000003 |
---|
| 536 | |
---|
| 537 | 5: WO: SPI write register |
---|
| 538 | Special register: |
---|
| 539 | * Write from software triggers SPI transaction |
---|
| 540 | * IPIF WrACK delayed until SPI is done (i.e. software doesn't have to poll; Xil_Out32 blocks until SPI is done) |
---|
| 541 | * Reads of this register return last SPI word transferred by software (might be stale, if usr_ SPI ports are also used) |
---|
| 542 | [ 0: 3] SPI chip select mask RF[D:A] 0x80000000=RFD, 0x40000000=RFC, 0x20000000=RFB, 0x10000000=RFA |
---|
| 543 | [ 4:11] Reserved 0x0FF00000 |
---|
| 544 | [12:15] Register address to write 0x000F0000 |
---|
| 545 | [16:17] Reserved 0x0000C000 |
---|
| 546 | [18:31] Register value to write 0x00003FFF |
---|
| 547 | |
---|
| 548 | |
---|
| 549 | |
---|
| 550 | 6 to 10: Reserved (RW 32-bit registers implemented; no connection to external hardware) |
---|
| 551 | |
---|
| 552 | 11: RO: Status bits |
---|
| 553 | Same per-RF masks as reg[0], same control signal masks as reg[0] |
---|
| 554 | [ 0: 3] = RFD control status {TxEn, RxEn, RxHP, SHDN} |
---|
| 555 | [ 4] = RFD MAX2829 PLL locked (1=locked) |
---|
| 556 | [ 5] = RFD SPI transfer in progress |
---|
| 557 | [ 6: 7] = Reserved |
---|
| 558 | |
---|
| 559 | [ 8:11] = RFC control status {TxEn, RxEn, RxHP, SHDN} |
---|
| 560 | [ 12] = RFC MAX2829 PLL locked (1=locked) |
---|
| 561 | [ 13] = RFC SPI transfer in progress |
---|
| 562 | [14:15] = Reserved |
---|
| 563 | |
---|
| 564 | [16:19] = RFB control status {TxEn, RxEn, RxHP, SHDN} |
---|
| 565 | [ 20] = RFB MAX2829 PLL locked (1=locked) |
---|
| 566 | [ 21] = RFB SPI transfer in progress |
---|
| 567 | [22:23] = Reserved |
---|
| 568 | |
---|
| 569 | [24:27] = RFA control status {TxEn, RxEn, RxHP, SHDN} |
---|
| 570 | [ 28] = RFA MAX2829 PLL locked (1=locked) |
---|
| 571 | [ 29] = RFA SPI transfer in progress |
---|
| 572 | [30:31] = Reserved |
---|
| 573 | |
---|
| 574 | 12 to 63: RO: Read-only registers which mirror state of MAX2829 internal registers (since MAX2829 SPI is write-only) |
---|
| 575 | * Registers are initialized (on FPGA config and MAX2829 reset) to MAX2829 defaults, to match MAX2829 reset state |
---|
| 576 | * Register values are updated automatically by SPI writes (via reg4 or via usr_ SPI port use) |
---|
| 577 | * Every register is: |
---|
| 578 | [ 0:17] Reserved; returns 0 on read |
---|
| 579 | [18:31] Register value (14 bits) |
---|
| 580 | |
---|
| 581 | 12...24: RO: Local copies of MAX2829 registers for RFA |
---|
| 582 | 12: RFA MAX2829 reg0 |
---|
| 583 | ... |
---|
| 584 | 24: RFA MAX2829 regC |
---|
| 585 | |
---|
| 586 | 25...37: RO: Local copies of MAX2829 registers for RFB |
---|
| 587 | 25: RFB MAX2829 reg0 |
---|
| 588 | ... |
---|
| 589 | 37: RFB MAX2829 regC |
---|
| 590 | |
---|
| 591 | 38...50: RO: Local copies of MAX2829 registers for RFC |
---|
| 592 | 38: RFC MAX2829 reg0 |
---|
| 593 | ... |
---|
| 594 | 50: RFC MAX2829 regC |
---|
| 595 | |
---|
| 596 | 51...63: RO: Local copies of MAX2829 registers for RFD |
---|
| 597 | 51: RFD MAX2829 reg0 |
---|
| 598 | ... |
---|
| 599 | 63: RFD MAX2829 regC |
---|
| 600 | |
---|
| 601 | */ |
---|
| 602 | |
---|
| 603 | //User logic -> IPIF signals |
---|
| 604 | assign IP2Bus_Data = slv_ip2bus_data; |
---|
| 605 | assign IP2Bus_RdAck = slv_read_ack; |
---|
| 606 | assign IP2Bus_Error = 0; |
---|
| 607 | |
---|
| 608 | //spi_tx_reg_write (Bus2IP_WrCE[x]) de-asserts as soon as transaction is ACK'd |
---|
| 609 | // so this mux switches back to the generic ACK as soon as the SPI xfer is done |
---|
| 610 | //Thus, the duration of assertion for spi_xfer_done doesn't really matter |
---|
| 611 | //A bit fast-n-loose, but works ok |
---|
| 612 | assign IP2Bus_WrAck = spi_tx_reg_write ? spi_xfer_done : slv_write_ack_normalRegisters; |
---|
| 613 | |
---|
| 614 | //Original definitions (wizard assumes all registers are RW) |
---|
| 615 | //slv_reg_write_sel = Bus2IP_WrCE[0:63], |
---|
| 616 | //slv_reg_read_sel = Bus2IP_RdCE[0:63], |
---|
| 617 | //slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15] || Bus2IP_RdCE[16] || Bus2IP_RdCE[17] || Bus2IP_RdCE[18] || Bus2IP_RdCE[19] || Bus2IP_RdCE[20] || Bus2IP_RdCE[21] || Bus2IP_RdCE[22] || Bus2IP_RdCE[23] || Bus2IP_RdCE[24] || Bus2IP_RdCE[25] || Bus2IP_RdCE[26] || Bus2IP_RdCE[27] || Bus2IP_RdCE[28] || Bus2IP_RdCE[29] || Bus2IP_RdCE[30] || Bus2IP_RdCE[31] || Bus2IP_RdCE[32] || Bus2IP_RdCE[33] || Bus2IP_RdCE[34] || Bus2IP_RdCE[35] || Bus2IP_RdCE[36] || Bus2IP_RdCE[37] || Bus2IP_RdCE[38] || Bus2IP_RdCE[39] || Bus2IP_RdCE[40] || Bus2IP_RdCE[41] || Bus2IP_RdCE[42] || Bus2IP_RdCE[43] || Bus2IP_RdCE[44] || Bus2IP_RdCE[45] || Bus2IP_RdCE[46] || Bus2IP_RdCE[47] || Bus2IP_RdCE[48] || Bus2IP_RdCE[49] || Bus2IP_RdCE[50] || Bus2IP_RdCE[51] || Bus2IP_RdCE[52] || Bus2IP_RdCE[53] || Bus2IP_RdCE[54] || Bus2IP_RdCE[55] || Bus2IP_RdCE[56] || Bus2IP_RdCE[57] || Bus2IP_RdCE[58] || Bus2IP_RdCE[59] || Bus2IP_RdCE[60] || Bus2IP_RdCE[61] || Bus2IP_RdCE[62] || Bus2IP_RdCE[63]; |
---|
| 618 | //slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15] || Bus2IP_WrCE[16] || Bus2IP_WrCE[17] || Bus2IP_WrCE[18] || Bus2IP_WrCE[19] || Bus2IP_WrCE[20] || Bus2IP_WrCE[21] || Bus2IP_WrCE[22] || Bus2IP_WrCE[23] || Bus2IP_WrCE[24] || Bus2IP_WrCE[25] || Bus2IP_WrCE[26] || Bus2IP_WrCE[27] || Bus2IP_WrCE[28] || Bus2IP_WrCE[29] || Bus2IP_WrCE[30] || Bus2IP_WrCE[31] || Bus2IP_WrCE[32] || Bus2IP_WrCE[33] || Bus2IP_WrCE[34] || Bus2IP_WrCE[35] || Bus2IP_WrCE[36] || Bus2IP_WrCE[37] || Bus2IP_WrCE[38] || Bus2IP_WrCE[39] || Bus2IP_WrCE[40] || Bus2IP_WrCE[41] || Bus2IP_WrCE[42] || Bus2IP_WrCE[43] || Bus2IP_WrCE[44] || Bus2IP_WrCE[45] || Bus2IP_WrCE[46] || Bus2IP_WrCE[47] || Bus2IP_WrCE[48] || Bus2IP_WrCE[49] || Bus2IP_WrCE[50] || Bus2IP_WrCE[51] || Bus2IP_WrCE[52] || Bus2IP_WrCE[53] || Bus2IP_WrCE[54] || Bus2IP_WrCE[55] || Bus2IP_WrCE[56] || Bus2IP_WrCE[57] || Bus2IP_WrCE[58] || Bus2IP_WrCE[59] || Bus2IP_WrCE[60] || Bus2IP_WrCE[61] || Bus2IP_WrCE[62] || Bus2IP_WrCE[63], |
---|
| 619 | |
---|
| 620 | //All registers can be read |
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| 621 | assign slv_reg_read_sel = Bus2IP_RdCE[0:63]; |
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| 622 | assign slv_read_ack = |Bus2IP_RdCE[0:63]; |
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| 623 | |
---|
| 624 | //Only regs 0 to 10 can be written; 12 to 63 are RO |
---|
| 625 | assign slv_reg_write_sel = Bus2IP_WrCE[0:10]; |
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| 626 | |
---|
| 627 | //Write ack for reg5 is delayed by SPI transfer |
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| 628 | assign slv_write_ack_normalRegisters = |{Bus2IP_WrCE[0:4], Bus2IP_WrCE[6:10]}; |
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| 629 | |
---|
| 630 | |
---|
| 631 | //Register 0: MAX2829 control |
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| 632 | assign RFD_TxEn_sw = slv_reg0[ 0]; |
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| 633 | assign RFC_TxEn_sw = slv_reg0[ 8]; |
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| 634 | assign RFB_TxEn_sw = slv_reg0[16]; |
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| 635 | assign RFA_TxEn_sw = slv_reg0[24]; |
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| 636 | |
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| 637 | assign RFD_RxEn_sw = slv_reg0[ 1]; |
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| 638 | assign RFC_RxEn_sw = slv_reg0[ 9]; |
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| 639 | assign RFB_RxEn_sw = slv_reg0[17]; |
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| 640 | assign RFA_RxEn_sw = slv_reg0[25]; |
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| 641 | |
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| 642 | assign RFD_RxHP_sw = slv_reg0[ 2]; |
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| 643 | assign RFC_RxHP_sw = slv_reg0[10]; |
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| 644 | assign RFB_RxHP_sw = slv_reg0[18]; |
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| 645 | assign RFA_RxHP_sw = slv_reg0[26]; |
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| 646 | |
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| 647 | assign RFD_SHDN_sw = slv_reg0[ 3]; |
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| 648 | assign RFC_SHDN_sw = slv_reg0[11]; |
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| 649 | assign RFB_SHDN_sw = slv_reg0[19]; |
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| 650 | assign RFA_SHDN_sw = slv_reg0[27]; |
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| 651 | |
---|
| 652 | assign RFD_TxEn_ctrlSrc = slv_reg0[ 4]; |
---|
| 653 | assign RFC_TxEn_ctrlSrc = slv_reg0[12]; |
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| 654 | assign RFB_TxEn_ctrlSrc = slv_reg0[20]; |
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| 655 | assign RFA_TxEn_ctrlSrc = slv_reg0[28]; |
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| 656 | |
---|
| 657 | assign RFD_RxEn_ctrlSrc = slv_reg0[ 5]; |
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| 658 | assign RFC_RxEn_ctrlSrc = slv_reg0[13]; |
---|
| 659 | assign RFB_RxEn_ctrlSrc = slv_reg0[21]; |
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| 660 | assign RFA_RxEn_ctrlSrc = slv_reg0[29]; |
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| 661 | |
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| 662 | assign RFD_RxHP_ctrlSrc = slv_reg0[ 6]; |
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| 663 | assign RFC_RxHP_ctrlSrc = slv_reg0[14]; |
---|
| 664 | assign RFB_RxHP_ctrlSrc = slv_reg0[22]; |
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| 665 | assign RFA_RxHP_ctrlSrc = slv_reg0[30]; |
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| 666 | |
---|
| 667 | assign RFD_SHDN_ctrlSrc = slv_reg0[ 7]; |
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| 668 | assign RFC_SHDN_ctrlSrc = slv_reg0[15]; |
---|
| 669 | assign RFB_SHDN_ctrlSrc = slv_reg0[23]; |
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| 670 | assign RFA_SHDN_ctrlSrc = slv_reg0[31]; |
---|
| 671 | |
---|
| 672 | //Register 1: Tx timing |
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| 673 | assign TxTiming_dly_TxGainRamp = slv_reg1[ 0: 7]; |
---|
| 674 | assign TxTiming_dly_PowerAmpEn = slv_reg1[ 8:15]; |
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| 675 | assign TxTiming_dly_TxEn = slv_reg1[16:23]; |
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| 676 | assign TxTiming_dly_startPHY = slv_reg1[24:31]; |
---|
| 677 | |
---|
| 678 | //Register 2: Tx gains |
---|
| 679 | assign RFD_TxGain_sw = slv_reg2[ 2: 7]; |
---|
| 680 | assign RFC_TxGain_sw = slv_reg2[10:15]; |
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| 681 | assign RFB_TxGain_sw = slv_reg2[18:23]; |
---|
| 682 | assign RFA_TxGain_sw = slv_reg2[26:31]; |
---|
| 683 | |
---|
| 684 | assign RFD_TxGain_ctrlSrc = slv_reg2[ 0]; |
---|
| 685 | assign RFC_TxGain_ctrlSrc = slv_reg2[ 8]; |
---|
| 686 | assign RFB_TxGain_ctrlSrc = slv_reg2[16]; |
---|
| 687 | assign RFA_TxGain_ctrlSrc = slv_reg2[24]; |
---|
| 688 | |
---|
| 689 | //Register 3: Rx gains |
---|
| 690 | assign RFD_RxGainBB_sw = slv_reg3[ 3: 7]; |
---|
| 691 | assign RFC_RxGainBB_sw = slv_reg3[11:15]; |
---|
| 692 | assign RFB_RxGainBB_sw = slv_reg3[19:23]; |
---|
| 693 | assign RFA_RxGainBB_sw = slv_reg3[27:31]; |
---|
| 694 | |
---|
| 695 | assign RFD_RxGainRF_sw = slv_reg3[ 1: 2]; |
---|
| 696 | assign RFC_RxGainRF_sw = slv_reg3[ 9:10]; |
---|
| 697 | assign RFB_RxGainRF_sw = slv_reg3[17:18]; |
---|
| 698 | assign RFA_RxGainRF_sw = slv_reg3[25:26]; |
---|
| 699 | |
---|
| 700 | assign RFD_RxGain_ctrlSrc = slv_reg3[ 0]; |
---|
| 701 | assign RFC_RxGain_ctrlSrc = slv_reg3[ 8]; |
---|
| 702 | assign RFB_RxGain_ctrlSrc = slv_reg3[16]; |
---|
| 703 | assign RFA_RxGain_ctrlSrc = slv_reg3[24]; |
---|
| 704 | |
---|
| 705 | //Register 4: Clock dividers & Tx gain ramp config |
---|
| 706 | assign TxGainRamp_timeStep = slv_reg4[16:19]; |
---|
| 707 | assign TxGainRamp_gainStep = slv_reg4[20:23]; |
---|
| 708 | assign spi_clk_div_sel = slv_reg4[25:27]; |
---|
| 709 | assign txTiming_clk_div_sel = slv_reg4[30:31]; |
---|
| 710 | |
---|
| 711 | //Register 5: SPI write |
---|
| 712 | assign spi_rfsel_mask_sw = slv_reg5[0:3]; |
---|
| 713 | assign spi_tx_regdata = slv_reg5[18:31]; |
---|
| 714 | assign spi_tx_regaddr = slv_reg5[12:15]; |
---|
| 715 | |
---|
| 716 | //Use the IPIF write-enable for the SPI Tx register as the SPI go |
---|
| 717 | // The bus will be paused until the SPI transfer is finished |
---|
| 718 | assign spi_tx_reg_write = Bus2IP_WrCE[5]; |
---|
| 719 | |
---|
| 720 | //Register 11: Read-only status bits |
---|
| 721 | assign status_reg[ 0: 3] = {RFD_TxEn, RFD_RxEn, RFD_RxHP, RFD_SHDN}; |
---|
| 722 | assign status_reg[ 4: 7] = {RFD_LD, ~RFD_SPI_CSn, RFD_PAEn_24, RFD_PAEn_5}; |
---|
| 723 | |
---|
| 724 | assign status_reg[ 8:11] = {RFC_TxEn, RFC_RxEn, RFC_RxHP, RFC_SHDN}; |
---|
| 725 | assign status_reg[12:15] = {RFC_LD, ~RFC_SPI_CSn, RFC_PAEn_24, RFC_PAEn_5}; |
---|
| 726 | |
---|
| 727 | assign status_reg[16:19] = {RFB_TxEn, RFB_RxEn, RFB_RxHP, RFB_SHDN}; |
---|
| 728 | assign status_reg[20:23] = {RFB_LD, ~RFB_SPI_CSn, RFB_PAEn_24, RFB_PAEn_5}; |
---|
| 729 | |
---|
| 730 | assign status_reg[24:27] = {RFA_TxEn, RFA_RxEn, RFA_RxHP, RFA_SHDN}; |
---|
| 731 | assign status_reg[28:31] = {RFA_LD, ~RFA_SPI_CSn, RFA_PAEn_24, RFA_PAEn_5}; |
---|
| 732 | |
---|
| 733 | //Mux the various control signals between software and hardware control |
---|
| 734 | assign RFA_txStart = RFA_TxEn_ctrlSrc ? usr_RFA_TxEn : RFA_TxEn_sw; |
---|
| 735 | assign RFB_txStart = RFB_TxEn_ctrlSrc ? usr_RFB_TxEn : RFB_TxEn_sw; |
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| 736 | assign RFC_txStart = RFC_TxEn_ctrlSrc ? usr_RFC_TxEn : RFC_TxEn_sw; |
---|
| 737 | assign RFD_txStart = RFD_TxEn_ctrlSrc ? usr_RFD_TxEn : RFD_TxEn_sw; |
---|
| 738 | |
---|
| 739 | assign RFA_RxEn = RFA_RxEn_ctrlSrc ? usr_RFA_RxEn : RFA_RxEn_sw; |
---|
| 740 | assign RFB_RxEn = RFB_RxEn_ctrlSrc ? usr_RFB_RxEn : RFB_RxEn_sw; |
---|
| 741 | assign RFC_RxEn = RFC_RxEn_ctrlSrc ? usr_RFC_RxEn : RFC_RxEn_sw; |
---|
| 742 | assign RFD_RxEn = RFD_RxEn_ctrlSrc ? usr_RFD_RxEn : RFD_RxEn_sw; |
---|
| 743 | |
---|
| 744 | assign RFA_RxHP = RFA_RxHP_ctrlSrc ? usr_RFA_RxHP : RFA_RxHP_sw; |
---|
| 745 | assign RFB_RxHP = RFB_RxHP_ctrlSrc ? usr_RFB_RxHP : RFB_RxHP_sw; |
---|
| 746 | assign RFC_RxHP = RFC_RxHP_ctrlSrc ? usr_RFC_RxHP : RFC_RxHP_sw; |
---|
| 747 | assign RFD_RxHP = RFD_RxHP_ctrlSrc ? usr_RFD_RxHP : RFD_RxHP_sw; |
---|
| 748 | |
---|
| 749 | assign RFA_SHDN = RFA_SHDN_ctrlSrc ? usr_RFA_SHDN : RFA_SHDN_sw; |
---|
| 750 | assign RFB_SHDN = RFB_SHDN_ctrlSrc ? usr_RFB_SHDN : RFB_SHDN_sw; |
---|
| 751 | assign RFC_SHDN = RFC_SHDN_ctrlSrc ? usr_RFC_SHDN : RFC_SHDN_sw; |
---|
| 752 | assign RFD_SHDN = RFD_SHDN_ctrlSrc ? usr_RFD_SHDN : RFD_SHDN_sw; |
---|
| 753 | |
---|
| 754 | assign RFA_TxGain_target = RFA_TxGain_ctrlSrc ? usr_RFA_TxGain : RFA_TxGain_sw; |
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| 755 | assign RFB_TxGain_target = RFB_TxGain_ctrlSrc ? usr_RFB_TxGain : RFB_TxGain_sw; |
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| 756 | assign RFC_TxGain_target = RFC_TxGain_ctrlSrc ? usr_RFC_TxGain : RFC_TxGain_sw; |
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| 757 | assign RFD_TxGain_target = RFD_TxGain_ctrlSrc ? usr_RFD_TxGain : RFD_TxGain_sw; |
---|
| 758 | |
---|
| 759 | assign RFA_RxGainBB = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainBB : RFA_RxGainBB_sw; |
---|
| 760 | assign RFB_RxGainBB = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainBB : RFB_RxGainBB_sw; |
---|
| 761 | assign RFC_RxGainBB = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainBB : RFC_RxGainBB_sw; |
---|
| 762 | assign RFD_RxGainBB = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainBB : RFD_RxGainBB_sw; |
---|
| 763 | |
---|
| 764 | assign RFA_RxGainRF = RFA_RxGain_ctrlSrc ? usr_RFA_RxGainRF : RFA_RxGainRF_sw; |
---|
| 765 | assign RFB_RxGainRF = RFB_RxGain_ctrlSrc ? usr_RFB_RxGainRF : RFB_RxGainRF_sw; |
---|
| 766 | assign RFC_RxGainRF = RFC_RxGain_ctrlSrc ? usr_RFC_RxGainRF : RFC_RxGainRF_sw; |
---|
| 767 | assign RFD_RxGainRF = RFD_RxGain_ctrlSrc ? usr_RFD_RxGainRF : RFD_RxGainRF_sw; |
---|
| 768 | |
---|
| 769 | |
---|
| 770 | //Output OR'd PHYStart signal (most PHYs use this, so any TxEnable will start the PHY) |
---|
| 771 | // Individual PHYStarts are provided in case user has multiple PHYs connected to different RF paths |
---|
| 772 | assign usr_any_PHYStart = usr_RFA_PHYStart || usr_RFB_PHYStart || usr_RFC_PHYStart || usr_RFD_PHYStart; |
---|
| 773 | |
---|
| 774 | //SKY13370 needs 100-250nsec to settle, so make the switch as soon as we know Tx process is starting |
---|
| 775 | //2-bit control signal in hardware, but only two valid states: |
---|
| 776 | // [V1 V2] = [1 0] => Rx path connected to SMA, Tx path terminated to 50 ohms (PA must be off!) |
---|
| 777 | // [V1 V2] = [0 1] => Tx path connected to SMA, Rx path terminated to 50 ohms |
---|
| 778 | //RFx_AntSw[0] = SKY13370.V1, RFx_AntSw[1] = SKY13370.V2 |
---|
| 779 | assign RFA_AntSw[0:1] = {~RFA_txStart, RFA_txStart}; |
---|
| 780 | assign RFB_AntSw[0:1] = {~RFB_txStart, RFB_txStart}; |
---|
| 781 | assign RFC_AntSw[0:1] = {~RFC_txStart, RFC_txStart}; |
---|
| 782 | assign RFD_AntSw[0:1] = {~RFD_txStart, RFD_txStart}; |
---|
| 783 | |
---|
| 784 | //PAs are enabled by single wire per band |
---|
| 785 | // One path's 2.4 and 5GHz PAs should never be enabled simultaneously |
---|
| 786 | //2.4GHz PA is on when: |
---|
| 787 | // TxTiming state machine asserts PAEn AND |
---|
| 788 | // MAX2829.reg5[0] == 0 (indicating MAX2829 is tuned to 2.4GHz band) |
---|
| 789 | //5GHz PA is on when: |
---|
| 790 | // TxTiming state machine asserts PAEn AND |
---|
| 791 | // MAX2829.reg5[0] == 1 (indicating MAX2829 is tuned to 5GHz band) |
---|
| 792 | //RFx_MAX2829_mirrorRegs are indexed [MSB:LSB]=[0:13] to match other busses in this core, |
---|
| 793 | // so the LSB (bit [0] in MAX2829 datasheet) is RFA_MAX2829_mirrorRegs[x][13] here |
---|
| 794 | assign RFA_PAEn_24 = (RFA_PAEn & ~(RFA_MAX2829_mirrorRegs[5][13])); |
---|
| 795 | assign RFB_PAEn_24 = (RFB_PAEn & ~(RFB_MAX2829_mirrorRegs[5][13])); |
---|
| 796 | assign RFC_PAEn_24 = (RFC_PAEn & ~(RFC_MAX2829_mirrorRegs[5][13])); |
---|
| 797 | assign RFD_PAEn_24 = (RFD_PAEn & ~(RFD_MAX2829_mirrorRegs[5][13])); |
---|
| 798 | |
---|
| 799 | assign RFA_PAEn_5 = (RFA_PAEn & (RFA_MAX2829_mirrorRegs[5][13])); |
---|
| 800 | assign RFB_PAEn_5 = (RFB_PAEn & (RFB_MAX2829_mirrorRegs[5][13])); |
---|
| 801 | assign RFC_PAEn_5 = (RFC_PAEn & (RFC_MAX2829_mirrorRegs[5][13])); |
---|
| 802 | assign RFD_PAEn_5 = (RFD_PAEn & (RFD_MAX2829_mirrorRegs[5][13])); |
---|
| 803 | |
---|
| 804 | |
---|
| 805 | //MAX2829 gain control bus |
---|
| 806 | // radio_controller.RFx_B[6:0] maps to MAX2829.B[7:1] |
---|
| 807 | // radio_controller.RFx_B[6] is MSB, radio_controller.RFx_B[0] is LSB |
---|
| 808 | // MAX2829.B7 is MSB, MAX2829.B1 is LSB |
---|
| 809 | // Note the RFx_B port is endian swapped relative to other busses in this core |
---|
| 810 | // to match the MAX2829 B port |
---|
| 811 | //When SPI gain control is disabled: |
---|
| 812 | // In Tx mode: |
---|
| 813 | // MAX2829.B[7] is don't care |
---|
| 814 | // MAX2829.B[6:1] = Tx RF VGA (6'd63 is max gain, 6'd0 is min gain (approx max-30dB)) |
---|
| 815 | // In Rx mode: |
---|
| 816 | // MAX2829.B[7:6] = Rx RF LNA (2'd3 is max gain (30dB), 2'd1 is min gain (0dB), 2'd0 is invalid) |
---|
| 817 | // MAX2829.B[5:1] = Rx BB VGA (5'd31 is max gain (approx 62dB), 5'd0 is min gain (approx 0dB) |
---|
| 818 | assign {RFA_B[6], RFA_B[5], RFA_B[4], RFA_B[3], RFA_B[2], RFA_B[1], RFA_B[0]} = RFA_txStart ? {1'b0, RFA_TxGain_ramped} : {RFA_RxGainRF, RFA_RxGainBB}; |
---|
| 819 | assign {RFB_B[6], RFB_B[5], RFB_B[4], RFB_B[3], RFB_B[2], RFB_B[1], RFB_B[0]} = RFB_txStart ? {1'b0, RFB_TxGain_ramped} : {RFB_RxGainRF, RFB_RxGainBB}; |
---|
| 820 | assign {RFC_B[6], RFC_B[5], RFC_B[4], RFC_B[3], RFC_B[2], RFC_B[1], RFC_B[0]} = RFC_txStart ? {1'b0, RFC_TxGain_ramped} : {RFC_RxGainRF, RFC_RxGainBB}; |
---|
| 821 | assign {RFD_B[6], RFD_B[5], RFD_B[4], RFD_B[3], RFD_B[2], RFD_B[1], RFD_B[0]} = RFD_txStart ? {1'b0, RFD_TxGain_ramped} : {RFD_RxGainRF, RFD_RxGainBB}; |
---|
| 822 | |
---|
| 823 | |
---|
| 824 | //Simple state machines for fixed timing of Tx events (MAX2829 TxEn, PA enable and PHY start) |
---|
| 825 | // One per RF path, to handle case of user designs which do Tx/Rx asychronously across paths |
---|
| 826 | // All use same timing values, as these are really tuned to the hardware, not the Tx signal |
---|
| 827 | radio_controller_TxTiming RFA_txTiming ( |
---|
| 828 | .clk(Bus2IP_Clk), |
---|
| 829 | .reset(Bus2IP_Reset), |
---|
| 830 | |
---|
| 831 | .clk_div(txTiming_clk_div_sel), |
---|
| 832 | |
---|
| 833 | .sw_start(RFA_txStart), |
---|
| 834 | |
---|
| 835 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
---|
| 836 | .dly_TxEn(TxTiming_dly_TxEn), |
---|
| 837 | .dly_PHYStart(TxTiming_dly_startPHY), |
---|
| 838 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
---|
| 839 | |
---|
| 840 | .gainRamp_TxGainTarget(RFA_TxGain_target), |
---|
| 841 | .gainRamp_GainStep(TxGainRamp_gainStep), |
---|
| 842 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
---|
| 843 | .gainRamp_TxGainOut(RFA_TxGain_ramped), |
---|
| 844 | |
---|
| 845 | .TxEn(RFA_TxEn), |
---|
| 846 | .PAEn(RFA_PAEn), |
---|
| 847 | .PHYStart(usr_RFA_PHYStart) |
---|
| 848 | ); |
---|
| 849 | radio_controller_TxTiming RFB_txTiming ( |
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| 850 | .clk(Bus2IP_Clk), |
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| 851 | .reset(Bus2IP_Reset), |
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| 852 | |
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| 853 | .clk_div(txTiming_clk_div_sel), |
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| 854 | |
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| 855 | .sw_start(RFB_txStart), |
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| 856 | |
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| 857 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
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| 858 | .dly_TxEn(TxTiming_dly_TxEn), |
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| 859 | .dly_PHYStart(TxTiming_dly_startPHY), |
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| 860 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
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| 861 | |
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| 862 | .gainRamp_TxGainTarget(RFB_TxGain_target), |
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| 863 | .gainRamp_GainStep(TxGainRamp_gainStep), |
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| 864 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
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| 865 | .gainRamp_TxGainOut(RFB_TxGain_ramped), |
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| 866 | |
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| 867 | .TxEn(RFB_TxEn), |
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| 868 | .PAEn(RFB_PAEn), |
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| 869 | .PHYStart(usr_RFB_PHYStart) |
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| 870 | ); |
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| 871 | radio_controller_TxTiming RFC_txTiming ( |
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| 872 | .clk(Bus2IP_Clk), |
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| 873 | .reset(Bus2IP_Reset), |
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| 874 | |
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| 875 | .clk_div(txTiming_clk_div_sel), |
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| 876 | |
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| 877 | .sw_start(RFC_txStart), |
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| 878 | |
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| 879 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
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| 880 | .dly_TxEn(TxTiming_dly_TxEn), |
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| 881 | .dly_PHYStart(TxTiming_dly_startPHY), |
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| 882 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
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| 883 | |
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| 884 | .gainRamp_TxGainTarget(RFC_TxGain_target), |
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| 885 | .gainRamp_GainStep(TxGainRamp_gainStep), |
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| 886 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
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| 887 | .gainRamp_TxGainOut(RFC_TxGain_ramped), |
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| 888 | |
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| 889 | .TxEn(RFC_TxEn), |
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| 890 | .PAEn(RFC_PAEn), |
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| 891 | .PHYStart(usr_RFC_PHYStart) |
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| 892 | ); |
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| 893 | radio_controller_TxTiming RFD_txTiming ( |
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| 894 | .clk(Bus2IP_Clk), |
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| 895 | .reset(Bus2IP_Reset), |
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| 896 | |
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| 897 | .clk_div(txTiming_clk_div_sel), |
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| 898 | |
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| 899 | .sw_start(RFD_txStart), |
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| 900 | |
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| 901 | .dly_GainRamp(TxTiming_dly_TxGainRamp), |
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| 902 | .dly_TxEn(TxTiming_dly_TxEn), |
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| 903 | .dly_PHYStart(TxTiming_dly_startPHY), |
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| 904 | .dly_PowerAmpEn(TxTiming_dly_PowerAmpEn), |
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| 905 | |
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| 906 | .gainRamp_TxGainTarget(RFD_TxGain_target), |
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| 907 | .gainRamp_GainStep(TxGainRamp_gainStep), |
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| 908 | .gainRamp_TimeStep(TxGainRamp_timeStep), |
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| 909 | .gainRamp_TxGainOut(RFD_TxGain_ramped), |
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| 910 | |
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| 911 | .TxEn(RFD_TxEn), |
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| 912 | .PAEn(RFD_PAEn), |
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| 913 | .PHYStart(usr_RFD_PHYStart) |
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| 914 | ); |
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| 915 | |
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| 916 | //Signals to detect when MAX2829 hardware reset occurs (TxEn=1, RxEn=1, SHDN=0) |
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| 917 | // Reset can be triggered by hardware or software, depending on the user config |
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| 918 | assign RFA_MAX2829_Reset = (RFA_TxEn & RFA_RxEn & ~RFA_SHDN); |
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| 919 | assign RFB_MAX2829_Reset = (RFB_TxEn & RFB_RxEn & ~RFB_SHDN); |
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| 920 | assign RFC_MAX2829_Reset = (RFC_TxEn & RFC_RxEn & ~RFC_SHDN); |
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| 921 | assign RFD_MAX2829_Reset = (RFD_TxEn & RFD_RxEn & ~RFD_SHDN); |
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| 922 | |
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| 923 | //Use a counter to generate a blinking error signal to indicate a radio in standby that hasn't yet locked |
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| 924 | reg [23:0] error_blink_counter = 24'b0; |
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| 925 | always @(posedge Bus2IP_Clk) |
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| 926 | error_blink_counter <= error_blink_counter + 1; |
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| 927 | |
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| 928 | assign usr_RFA_statLED_Tx = RFA_SHDN ? (RFA_TxEn | ((~RFA_LD) & error_blink_counter[23])) : 1'b0; |
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| 929 | assign usr_RFA_statLED_Rx = RFA_SHDN ? (RFA_RxEn | ((~RFA_LD) & error_blink_counter[23])) : 1'b0;; |
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| 930 | |
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| 931 | assign usr_RFB_statLED_Tx = RFB_SHDN ? (RFB_TxEn | ((~RFB_LD) & error_blink_counter[23])) : 1'b0; |
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| 932 | assign usr_RFB_statLED_Rx = RFB_SHDN ? (RFB_RxEn | ((~RFB_LD) & error_blink_counter[23])) : 1'b0;; |
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| 933 | |
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| 934 | assign usr_RFC_statLED_Tx = RFC_SHDN ? (RFC_TxEn | ((~RFC_LD) & error_blink_counter[23])) : 1'b0; |
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| 935 | assign usr_RFC_statLED_Rx = RFC_SHDN ? (RFC_RxEn | ((~RFC_LD) & error_blink_counter[23])) : 1'b0;; |
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| 936 | |
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| 937 | assign usr_RFD_statLED_Tx = RFD_SHDN ? (RFD_TxEn | ((~RFD_LD) & error_blink_counter[23])) : 1'b0; |
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| 938 | assign usr_RFD_statLED_Rx = RFD_SHDN ? (RFD_RxEn | ((~RFD_LD) & error_blink_counter[23])) : 1'b0;; |
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| 939 | |
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| 940 | |
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| 941 | //Mask per-RF path to enable SPI transactions |
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| 942 | // Driven by register for software control, usr_ port for hardware control |
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| 943 | assign spi_rfsel_mask = usr_SPI_ctrlSrc ? usr_SPI_rfsel : spi_rfsel_mask_sw; |
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| 944 | |
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| 945 | |
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| 946 | //Processes to update mirror registers following SPI write |
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| 947 | // Note these registers are *not* changed by a software reset |
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| 948 | // The only reset condition is the MAX2829 hardware reset (TxEn=1, RxEn=1, SHDN=0) |
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| 949 | always @(posedge Bus2IP_Clk) |
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| 950 | begin |
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| 951 | if(RFA_MAX2829_Reset) |
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| 952 | begin |
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| 953 | RFA_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
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| 954 | RFA_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
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| 955 | RFA_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
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| 956 | RFA_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
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| 957 | RFA_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
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| 958 | RFA_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
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| 959 | RFA_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
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| 960 | RFA_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
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| 961 | RFA_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
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| 962 | RFA_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
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| 963 | RFA_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
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| 964 | RFA_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
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| 965 | RFA_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
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| 966 | end |
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| 967 | else if(spi_go) |
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| 968 | begin |
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| 969 | if(spi_rfsel_mask & 4'b0001) //RFA selected |
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| 970 | RFA_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata; |
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| 971 | end |
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| 972 | end |
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| 973 | |
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| 974 | always @(posedge Bus2IP_Clk) |
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| 975 | begin |
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| 976 | if(RFB_MAX2829_Reset) |
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| 977 | begin |
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| 978 | RFB_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
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| 979 | RFB_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
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| 980 | RFB_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
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| 981 | RFB_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
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| 982 | RFB_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
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| 983 | RFB_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
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| 984 | RFB_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
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| 985 | RFB_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
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| 986 | RFB_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
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| 987 | RFB_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
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| 988 | RFB_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
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| 989 | RFB_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
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| 990 | RFB_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
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| 991 | end |
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| 992 | else if(spi_go) |
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| 993 | begin |
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| 994 | if(spi_rfsel_mask & 4'b0010) //RFB selected |
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| 995 | RFB_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata; |
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| 996 | end |
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| 997 | end |
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| 998 | |
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| 999 | always @(posedge Bus2IP_Clk) |
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| 1000 | begin |
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| 1001 | if(RFC_MAX2829_Reset) |
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| 1002 | begin |
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| 1003 | RFC_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
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| 1004 | RFC_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
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| 1005 | RFC_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
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| 1006 | RFC_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
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| 1007 | RFC_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
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| 1008 | RFC_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
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| 1009 | RFC_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
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| 1010 | RFC_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
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| 1011 | RFC_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
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| 1012 | RFC_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
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| 1013 | RFC_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
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| 1014 | RFC_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
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| 1015 | RFC_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
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| 1016 | end |
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| 1017 | else if(spi_go) |
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| 1018 | begin |
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| 1019 | if(spi_rfsel_mask & 4'b0100) //RFC selected |
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| 1020 | RFC_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata; |
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| 1021 | end |
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| 1022 | end |
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| 1023 | |
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| 1024 | always @(posedge Bus2IP_Clk) |
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| 1025 | begin |
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| 1026 | if(RFD_MAX2829_Reset) |
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| 1027 | begin |
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| 1028 | RFD_MAX2829_mirrorRegs[0] <= `MAX2829_REG0_ON_RESET; |
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| 1029 | RFD_MAX2829_mirrorRegs[1] <= `MAX2829_REG1_ON_RESET; |
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| 1030 | RFD_MAX2829_mirrorRegs[2] <= `MAX2829_REG2_ON_RESET; |
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| 1031 | RFD_MAX2829_mirrorRegs[3] <= `MAX2829_REG3_ON_RESET; |
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| 1032 | RFD_MAX2829_mirrorRegs[4] <= `MAX2829_REG4_ON_RESET; |
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| 1033 | RFD_MAX2829_mirrorRegs[5] <= `MAX2829_REG5_ON_RESET; |
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| 1034 | RFD_MAX2829_mirrorRegs[6] <= `MAX2829_REG6_ON_RESET; |
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| 1035 | RFD_MAX2829_mirrorRegs[7] <= `MAX2829_REG7_ON_RESET; |
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| 1036 | RFD_MAX2829_mirrorRegs[8] <= `MAX2829_REG8_ON_RESET; |
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| 1037 | RFD_MAX2829_mirrorRegs[9] <= `MAX2829_REG9_ON_RESET; |
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| 1038 | RFD_MAX2829_mirrorRegs[10] <= `MAX2829_REGA_ON_RESET; |
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| 1039 | RFD_MAX2829_mirrorRegs[11] <= `MAX2829_REGB_ON_RESET; |
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| 1040 | RFD_MAX2829_mirrorRegs[12] <= `MAX2829_REGC_ON_RESET; |
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| 1041 | end |
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| 1042 | else if(spi_go) |
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| 1043 | begin |
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| 1044 | if(spi_rfsel_mask & 4'b1000) //RFD selected |
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| 1045 | RFD_MAX2829_mirrorRegs[spi_tx_regaddr] <= spi_tx_regdata; |
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| 1046 | end |
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| 1047 | end |
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| 1048 | |
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| 1049 | //MAX2829 CS is active-low; warp_spi_io.spi_cs is active high |
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| 1050 | assign RFA_SPI_CSn = ~(spi_rfsel_mask[3] & spi_cs); |
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| 1051 | assign RFB_SPI_CSn = ~(spi_rfsel_mask[2] & spi_cs); |
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| 1052 | assign RFC_SPI_CSn = ~(spi_rfsel_mask[1] & spi_cs); |
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| 1053 | assign RFD_SPI_CSn = ~(spi_rfsel_mask[0] & spi_cs); |
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| 1054 | |
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| 1055 | assign RFA_SPI_MOSI = spi_mosi; |
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| 1056 | assign RFB_SPI_MOSI = spi_mosi; |
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| 1057 | assign RFC_SPI_MOSI = spi_mosi; |
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| 1058 | assign RFD_SPI_MOSI = spi_mosi; |
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| 1059 | |
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| 1060 | //Mask each SCLK output by the corresponding CS |
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| 1061 | // No point toggling SCLKs that will be ignored |
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| 1062 | assign RFA_SPI_SCLK = (spi_sclk & spi_rfsel_mask[3]); |
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| 1063 | assign RFB_SPI_SCLK = (spi_sclk & spi_rfsel_mask[2]); |
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| 1064 | assign RFC_SPI_SCLK = (spi_sclk & spi_rfsel_mask[1]); |
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| 1065 | assign RFD_SPI_SCLK = (spi_sclk & spi_rfsel_mask[0]); |
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| 1066 | |
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| 1067 | //MAX2829 SPI uses 18-bit transfers, formatted as {regData[0:13] regAddr[0:3]}, data and addr both transfer MSB first |
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| 1068 | wire [0:17] spi_tx_data_word; |
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| 1069 | assign spi_tx_data_word[0:17] = usr_SPI_ctrlSrc ? {usr_SPI_regdata, usr_SPI_regaddr} : {spi_tx_regdata, spi_tx_regaddr}; |
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| 1070 | |
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| 1071 | assign spi_go = usr_SPI_ctrlSrc ? usr_SPI_go : spi_tx_reg_write; |
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| 1072 | |
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| 1073 | assign usr_SPI_active = spi_cs; |
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| 1074 | |
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| 1075 | warp_spi_io #(.SPI_XFER_LEN(18)) spi_io ( |
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| 1076 | .sys_clk(Bus2IP_Clk), |
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| 1077 | .reset(Bus2IP_Reset), |
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| 1078 | .go(spi_go), |
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| 1079 | .done(spi_xfer_done), |
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| 1080 | .clkDiv(spi_clk_div_sel), |
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| 1081 | |
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| 1082 | .currBitNum(), |
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| 1083 | |
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| 1084 | .txData({14'b0, spi_tx_data_word}), |
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| 1085 | |
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| 1086 | .rxData1(), |
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| 1087 | .rxData2(), |
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| 1088 | .rxData3(), |
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| 1089 | .rxData4(), |
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| 1090 | |
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| 1091 | .spi_cs(spi_cs), |
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| 1092 | .spi_sclk(spi_sclk), |
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| 1093 | |
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| 1094 | .spi_mosi(spi_mosi), |
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| 1095 | |
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| 1096 | .spi_miso1(1'b0), |
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| 1097 | .spi_miso2(1'b0), |
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| 1098 | .spi_miso3(1'b0), |
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| 1099 | .spi_miso4(1'b0) |
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| 1100 | ); |
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| 1101 | endmodule |
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| 1102 | |
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| 1103 | |
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| 1104 | |
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| 1105 | |
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| 1106 | |
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