1 | module at_boot_reg_writer |
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2 | ( |
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3 | input clk, |
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4 | input clk_valid, |
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5 | |
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6 | input clk_src_sel, //1=on-board, 0=off-board |
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7 | |
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8 | output spi_running, |
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9 | |
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10 | output spi_mosi, |
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11 | output spi_sclk, |
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12 | output reg spi_csn = 1 |
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13 | ); |
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14 | |
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15 | parameter INCLUDE_IBUFGDS = 1; |
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16 | parameter NUM_REGS = 3; |
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17 | |
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18 | //AD9512 registers are 8 bits each, addressed by 7 bit addresses |
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19 | |
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20 | //reg45[0]: clock src sel (0=CLK2=off-board, 1=CLK1=on-board) |
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21 | parameter ADDR0 = 7'h45; |
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22 | parameter DATA0 = 8'b0000_0000; //LSB to be overwritten by config input |
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23 | |
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24 | //reg51[7]: bypass divider for OUT3 (1=bypass) |
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25 | parameter ADDR1 = 7'h51; |
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26 | parameter DATA1 = 8'b1000_0000; |
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27 | |
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28 | //reg5A[0]: self-clearing reg update flag |
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29 | parameter ADDR2 = 7'h5A; |
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30 | parameter DATA2 = 8'b0000_0001; |
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31 | |
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32 | reg [0:2] cnt_reg = 3'h0; |
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33 | reg [0:4] cnt_bit = 5'h0; |
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34 | reg [0:3] cnt_clk_en = 4'h0; |
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35 | |
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36 | wire done; |
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37 | |
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38 | wire clk_en; |
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39 | assign clk_en = (cnt_clk_en == 4'hf); |
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40 | |
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41 | reg [0:24*3-1] spi_shift_reg = {9'b0, ADDR0, DATA0, 9'b0, ADDR1, DATA1, 9'b0, ADDR2, DATA2}; |
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42 | //reg [0:24*3-1] spi_shift_reg = {24'h800001, 24'h800001, 24'h800001};//sim test vector |
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43 | //reg [0:24*3-1] spi_shift_reg = {24'h800002, 24'h800003, 24'h800004};//sim test vector |
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44 | |
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45 | always @(posedge clk) begin |
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46 | |
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47 | if(!done & clk_en) begin |
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48 | |
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49 | cnt_bit <= cnt_bit + 1; |
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50 | |
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51 | if(cnt_bit == 5'h1f) begin |
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52 | cnt_bit <= 5'h00; |
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53 | cnt_reg <= cnt_reg + 1; |
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54 | end |
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55 | |
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56 | if( (cnt_bit >= 4) && (cnt_bit < 28) ) begin |
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57 | spi_csn <= 1'b0; |
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58 | end |
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59 | else begin |
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60 | spi_csn <= 1'b1; |
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61 | end |
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62 | |
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63 | if( (cnt_bit > 4) && (cnt_bit <= 28) ) begin |
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64 | spi_shift_reg[0:24*NUM_REGS-1] <= {spi_shift_reg[1:24*NUM_REGS-1], 1'b0}; |
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65 | end |
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66 | else begin |
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67 | spi_shift_reg <= spi_shift_reg; |
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68 | end |
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69 | end |
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70 | end |
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71 | |
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72 | assign done = ((cnt_bit == 5'h1f) && (cnt_reg == NUM_REGS-1)); |
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73 | |
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74 | //assign spi_mosi = (cnt_bit == 16 && cnt_reg == 0) ? (~clk_src_sel) : spi_shift_reg[0]; |
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75 | assign spi_mosi = (cnt_bit == 28 && cnt_reg == 0) ? (clk_src_sel) : spi_shift_reg[0]; |
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76 | assign spi_sclk = cnt_clk_en[0]; |
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77 | assign spi_running = (!done) || (cnt_reg==5'h0); |
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78 | |
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79 | always @(posedge clk) begin |
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80 | if((!done) && clk_valid) |
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81 | cnt_clk_en = cnt_clk_en + 1; |
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82 | end |
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83 | |
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84 | endmodule |
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