source:
PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| ../ | |||||
| picoblaze_src | 4326 | 9 years | murphpo | Comment-only update to picoblaze assembly | |
| at_boot_clk_config.v | 9.0 KB | 4303 | 9 years | murphpo | More pipeline regs in picoblaze periph connections |
| kcpsm6.v | 80.9 KB | 4287 | 9 years | murphpo | First version of clock controller pcore with support for cm-pll module |
| prog_clk_config_boot.v | 254.6 KB | 4295 | 9 years | murphpo | First working version of eeprom-enabled cm-pll-supporting clock config core |
| uart_tx6.v | 11.4 KB | 4287 | 9 years | murphpo | First version of clock controller pcore with support for cm-pll module |
| user_logic.v | 20.4 KB | 4295 | 9 years | murphpo | First working version of eeprom-enabled cm-pll-supporting clock config core |
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