source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_v3_01_b/doc/html/api/group__user__functions.html

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26   <div id="projectname">w3_clock_controller Driver
27   </div>
28   <div id="projectbrief">Driver for WARP v3 AD9512 clock buffer controller core (w3_clock_controller_v3_00_b)</div>
29  </td>
30 </tr>
31 </tbody>
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57<div class="header">
58  <div class="summary">
59<a href="#func-members">Functions</a>  </div>
60  <div class="headertitle">
61<div class="title">Functions</div>  </div>
62</div><!--header-->
63<div class="contents">
64<table class="memberdecls">
65<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
66Functions</h2></td></tr>
67<tr class="memitem:ga6a17b6d143e2d820f0c5ae4283496ac7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga6a17b6d143e2d820f0c5ae4283496ac7">clk_init</a> (u32 baseaddr, u8 clkDiv)</td></tr>
68<tr class="separator:ga6a17b6d143e2d820f0c5ae4283496ac7"><td class="memSeparator" colspan="2">&#160;</td></tr>
69<tr class="memitem:ga509f9e41d2bac1b3dbf1541709d1179c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c">clk_config_outputs</a> (u32 baseaddr, u8 clkOutMode, u32 clkOutSel)</td></tr>
70<tr class="separator:ga509f9e41d2bac1b3dbf1541709d1179c"><td class="memSeparator" colspan="2">&#160;</td></tr>
71<tr class="memitem:ga18b3cfc8fd63d3f9534de4278c1c8fe2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga18b3cfc8fd63d3f9534de4278c1c8fe2">clk_config_input_rf_ref</a> (u32 baseaddr, u8 clkInSel)</td></tr>
72<tr class="separator:ga18b3cfc8fd63d3f9534de4278c1c8fe2"><td class="memSeparator" colspan="2">&#160;</td></tr>
73<tr class="memitem:ga5a678cc334473f774450c0c5399f9dc3"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga5a678cc334473f774450c0c5399f9dc3">clk_config_read_clkmod_status</a> (u32 baseaddr)</td></tr>
74<tr class="separator:ga5a678cc334473f774450c0c5399f9dc3"><td class="memSeparator" colspan="2">&#160;</td></tr>
75<tr class="memitem:ga58355f82b91625951cad329e82e3e2a6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga58355f82b91625951cad329e82e3e2a6">clk_config_dividers</a> (u32 baseaddr, u8 clkDiv, u32 clkOutSel)</td></tr>
76<tr class="separator:ga58355f82b91625951cad329e82e3e2a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
77<tr class="memitem:ga0769cba992797225f0e3f8f58d9b6b1a"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga0769cba992797225f0e3f8f58d9b6b1a">clk_spi_read</a> (u32 baseaddr, u32 csMask, u8 regAddr)</td></tr>
78<tr class="separator:ga0769cba992797225f0e3f8f58d9b6b1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
79<tr class="memitem:ga35a167edcce1415775ea854c165408d4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__user__functions.html#ga35a167edcce1415775ea854c165408d4">clk_spi_write</a> (u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte)</td></tr>
80<tr class="separator:ga35a167edcce1415775ea854c165408d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
81</table>
82<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
83<p>Example: </p>
84<div class="fragment"><div class="line"><span class="comment">//Assumes user code sets CLK_BASEADDR to base address of w3_clock_controller core, as set in xparameters.h</span></div>
85<div class="line"></div>
86<div class="line"><span class="comment">//Initialize the AD9512 clock buffers</span></div>
87<div class="line">ad_init(CLK_BASEADDR, 3);</div>
88<div class="line"></div>
89<div class="line"><span class="comment">//Enable clock outputs to FMC slot</span></div>
90<div class="line"><a class="code" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c" title="Configures which outputs are en/disabled in both AD9512 clock buffers.">clk_config_outputs</a>(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC | CLK_RFREF_OUTSEL_FMC));</div>
91<div class="line"></div>
92<div class="line"><span class="comment">//Disable clock outputs to clock module header</span></div>
93<div class="line"><a class="code" href="group__user__functions.html#ga509f9e41d2bac1b3dbf1541709d1179c" title="Configures which outputs are en/disabled in both AD9512 clock buffers.">clk_config_outputs</a>(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));</div>
94<div class="line"></div>
95<div class="line"><span class="comment">//Set clock to AD chips to 40MHz (80MHz source divided by 2)</span></div>
96<div class="line"><a class="code" href="group__user__functions.html#ga58355f82b91625951cad329e82e3e2a6" title="Configures output dividers in both AD9512 clock buffers.">clk_config_dividers</a>(CLK_BASEADDR, 2, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));</div>
97</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
98<a class="anchor" id="ga6a17b6d143e2d820f0c5ae4283496ac7"></a>
99<div class="memitem">
100<div class="memproto">
101      <table class="memname">
102        <tr>
103          <td class="memname">int clk_init </td>
104          <td>(</td>
105          <td class="paramtype">u32&#160;</td>
106          <td class="paramname"><em>baseaddr</em>, </td>
107        </tr>
108        <tr>
109          <td class="paramkey"></td>
110          <td></td>
111          <td class="paramtype">u8&#160;</td>
112          <td class="paramname"><em>clkDiv</em>&#160;</td>
113        </tr>
114        <tr>
115          <td></td>
116          <td>)</td>
117          <td></td><td></td>
118        </tr>
119      </table>
120</div><div class="memdoc">
121
122<p>Initializes the clock controller. This function must be called once at boot before any AD or RF operations will work. Default config is: </p>
123<ul>
124<li>On board 80MHz TCXO used as source for sampling and RF ref clock buffers</li>
125<li>80MHz clock driven to FPGA, RF A and RF B ADC/DACs</li>
126<li>40MHz clock driven to RF A and B transceivers</li>
127<li>FMC and clock module header clocks disabled <dl class="params"><dt>Parameters</dt><dd>
128  <table class="params">
129    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
130    <tr><td class="paramname">clkDiv</td><td>Clock divider for SPI serial clock (set to 3 for 160MHz bus) </td></tr>
131  </table>
132  </dd>
133</dl>
134</li>
135</ul>
136
137</div>
138</div>
139<a class="anchor" id="ga509f9e41d2bac1b3dbf1541709d1179c"></a>
140<div class="memitem">
141<div class="memproto">
142      <table class="memname">
143        <tr>
144          <td class="memname">int clk_config_outputs </td>
145          <td>(</td>
146          <td class="paramtype">u32&#160;</td>
147          <td class="paramname"><em>baseaddr</em>, </td>
148        </tr>
149        <tr>
150          <td class="paramkey"></td>
151          <td></td>
152          <td class="paramtype">u8&#160;</td>
153          <td class="paramname"><em>clkOutMode</em>, </td>
154        </tr>
155        <tr>
156          <td class="paramkey"></td>
157          <td></td>
158          <td class="paramtype">u32&#160;</td>
159          <td class="paramname"><em>clkOutSel</em>&#160;</td>
160        </tr>
161        <tr>
162          <td></td>
163          <td>)</td>
164          <td></td><td></td>
165        </tr>
166      </table>
167</div><div class="memdoc">
168
169<p>Configures which outputs are en/disabled in both AD9512 clock buffers. </p>
170<dl class="params"><dt>Parameters</dt><dd>
171  <table class="params">
172    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
173    <tr><td class="paramname">clkOutMode</td><td>New mode for selected clock outputs; must be CLK_OUTPUT_ON or CLK_OUTPUT_OFF </td></tr>
174    <tr><td class="paramname">clkOutSel</td><td>Masks to select which clock outputs to affect; must be OR'd combination of: <table class="doxtable">
175<tr>
176<th>Mask </th><th>Selected Output</th></tr>
177<tr>
178<td>CLK_SAMP_OUTSEL_FMC </td><td>Sampling clock buffer to FMC slot </td></tr>
179<tr>
180<td>CLK_SAMP_OUTSEL_CLKMODHDR </td><td>Sampling clock buffer to clock module header </td></tr>
181<tr>
182<td>CLK_SAMP_OUTSEL_FPGA </td><td>Sampling clock buffer to FPGA </td></tr>
183<tr>
184<td>CLK_SAMP_OUTSEL_AD_RFA </td><td>Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) </td></tr>
185<tr>
186<td>CLK_SAMP_OUTSEL_AD_RFB </td><td>Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) </td></tr>
187<tr>
188<td>CLK_RFREF_OUTSEL_FMC </td><td>RF ref clock buffer to FMC </td></tr>
189<tr>
190<td>CLK_RFREF_OUTSEL_CLKMODHDR </td><td>RF ref clock buffer to clock module header </td></tr>
191<tr>
192<td>CLK_RFREF_OUTSEL_RFAB </td><td>RF ref clock buffer to RF A and B transceivers </td></tr>
193</table>
194</td></tr>
195  </table>
196  </dd>
197</dl>
198<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl>
199
200</div>
201</div>
202<a class="anchor" id="ga18b3cfc8fd63d3f9534de4278c1c8fe2"></a>
203<div class="memitem">
204<div class="memproto">
205      <table class="memname">
206        <tr>
207          <td class="memname">int clk_config_input_rf_ref </td>
208          <td>(</td>
209          <td class="paramtype">u32&#160;</td>
210          <td class="paramname"><em>baseaddr</em>, </td>
211        </tr>
212        <tr>
213          <td class="paramkey"></td>
214          <td></td>
215          <td class="paramtype">u8&#160;</td>
216          <td class="paramname"><em>clkInSel</em>&#160;</td>
217        </tr>
218        <tr>
219          <td></td>
220          <td>)</td>
221          <td></td><td></td>
222        </tr>
223      </table>
224</div><div class="memdoc">
225
226<p>Configures whether the RF Reference Buffer uses the on-board or off-board clock source. </p>
227<dl class="params"><dt>Parameters</dt><dd>
228  <table class="params">
229    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
230    <tr><td class="paramname">clkInSel</td><td>Clock source mask, must be either CLK_INSEL_ONBOARD (for on-board oscillator) or CLK_INSEL_CLKMOD (for off-board clock via clock module header) <table class="doxtable">
231<tr>
232<th>Mask </th><th>Selected Input</th></tr>
233<tr>
234<td>CLK_INSEL_ONBOARD </td><td>Selects on-board TCXO as RF Reference clock source (AD9512 CLK1/CLK1B port) </td></tr>
235<tr>
236<td>CLK_INSEL_CLKMOD </td><td>Selects off-board clock from clock module header as RF Reference clock source (AD9512 CLK2/CLK2B port) </td></tr>
237</table>
238</td></tr>
239  </table>
240  </dd>
241</dl>
242<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl>
243
244</div>
245</div>
246<a class="anchor" id="ga5a678cc334473f774450c0c5399f9dc3"></a>
247<div class="memitem">
248<div class="memproto">
249      <table class="memname">
250        <tr>
251          <td class="memname">u16 clk_config_read_clkmod_status </td>
252          <td>(</td>
253          <td class="paramtype">u32&#160;</td>
254          <td class="paramname"><em>baseaddr</em></td><td>)</td>
255          <td></td>
256        </tr>
257      </table>
258</div><div class="memdoc">
259
260<p>Reads the status pins of the currently installed clock module. </p>
261<dl class="params"><dt>Parameters</dt><dd>
262  <table class="params">
263    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
264  </table>
265  </dd>
266</dl>
267<dl class="section return"><dt>Returns</dt><dd>Returns a 16-bit value for the clock module status; the meaning of the status bits depends on the currently installed module. For CM-MMCX the 2 LSB of the return are set by the 2-bit SIP switch, where an asserted switch (actuator down, towards the mounting bolt) returns 0. Reading the SIP switch when no CM-MMCX is installed will return 0x3 (both switches = 1). </dd></dl>
268
269</div>
270</div>
271<a class="anchor" id="ga58355f82b91625951cad329e82e3e2a6"></a>
272<div class="memitem">
273<div class="memproto">
274      <table class="memname">
275        <tr>
276          <td class="memname">int clk_config_dividers </td>
277          <td>(</td>
278          <td class="paramtype">u32&#160;</td>
279          <td class="paramname"><em>baseaddr</em>, </td>
280        </tr>
281        <tr>
282          <td class="paramkey"></td>
283          <td></td>
284          <td class="paramtype">u8&#160;</td>
285          <td class="paramname"><em>clkDiv</em>, </td>
286        </tr>
287        <tr>
288          <td class="paramkey"></td>
289          <td></td>
290          <td class="paramtype">u32&#160;</td>
291          <td class="paramname"><em>clkOutSel</em>&#160;</td>
292        </tr>
293        <tr>
294          <td></td>
295          <td>)</td>
296          <td></td><td></td>
297        </tr>
298      </table>
299</div><div class="memdoc">
300
301<p>Configures output dividers in both AD9512 clock buffers. </p>
302<dl class="params"><dt>Parameters</dt><dd>
303  <table class="params">
304    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
305    <tr><td class="paramname">clkDiv</td><td>Divider value to set; must be 1 or even integer in [2,32] </td></tr>
306    <tr><td class="paramname">clkOutSel</td><td>Masks to select which clock outputs to affect; must be OR'd combination of: <table class="doxtable">
307<tr>
308<th>Mask </th><th>Selected Output</th></tr>
309<tr>
310<td>CLK_SAMP_OUTSEL_FMC </td><td>Sampling clock buffer to FMC slot </td></tr>
311<tr>
312<td>CLK_SAMP_OUTSEL_CLKMODHDR </td><td>Sampling clock buffer to clock module header </td></tr>
313<tr>
314<td>CLK_SAMP_OUTSEL_FPGA </td><td>Sampling clock buffer to FPGA </td></tr>
315<tr>
316<td>CLK_SAMP_OUTSEL_AD_RFA </td><td>Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) </td></tr>
317<tr>
318<td>CLK_SAMP_OUTSEL_AD_RFB </td><td>Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) </td></tr>
319<tr>
320<td>CLK_RFREF_OUTSEL_FMC </td><td>RF ref clock buffer to FMC </td></tr>
321<tr>
322<td>CLK_RFREF_OUTSEL_CLKMODHDR </td><td>RF ref clock buffer to clock module header </td></tr>
323<tr>
324<td>CLK_RFREF_OUTSEL_RFAB </td><td>RF ref clock buffer to RF A and B transceivers </td></tr>
325</table>
326</td></tr>
327  </table>
328  </dd>
329</dl>
330<dl class="section return"><dt>Returns</dt><dd>Returns 0 on success, -1 for invalid parameters </dd></dl>
331
332</div>
333</div>
334<a class="anchor" id="ga0769cba992797225f0e3f8f58d9b6b1a"></a>
335<div class="memitem">
336<div class="memproto">
337      <table class="memname">
338        <tr>
339          <td class="memname">u32 clk_spi_read </td>
340          <td>(</td>
341          <td class="paramtype">u32&#160;</td>
342          <td class="paramname"><em>baseaddr</em>, </td>
343        </tr>
344        <tr>
345          <td class="paramkey"></td>
346          <td></td>
347          <td class="paramtype">u32&#160;</td>
348          <td class="paramname"><em>csMask</em>, </td>
349        </tr>
350        <tr>
351          <td class="paramkey"></td>
352          <td></td>
353          <td class="paramtype">u8&#160;</td>
354          <td class="paramname"><em>regAddr</em>&#160;</td>
355        </tr>
356        <tr>
357          <td></td>
358          <td>)</td>
359          <td></td><td></td>
360        </tr>
361      </table>
362</div><div class="memdoc">
363
364<p>Reads the specified register from both AD9963s. </p>
365<dl class="params"><dt>Parameters</dt><dd>
366  <table class="params">
367    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
368    <tr><td class="paramname">csMask</td><td>OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS </td></tr>
369    <tr><td class="paramname">regAddr</td><td>Address of register to read, in [0x00, 0x5A] </td></tr>
370  </table>
371  </dd>
372</dl>
373<dl class="section return"><dt>Returns</dt><dd>Returns concatenation of current values of the specified register for both AD9512s (if selected); samp clock buffer is LSB </dd></dl>
374
375</div>
376</div>
377<a class="anchor" id="ga35a167edcce1415775ea854c165408d4"></a>
378<div class="memitem">
379<div class="memproto">
380      <table class="memname">
381        <tr>
382          <td class="memname">void clk_spi_write </td>
383          <td>(</td>
384          <td class="paramtype">u32&#160;</td>
385          <td class="paramname"><em>baseaddr</em>, </td>
386        </tr>
387        <tr>
388          <td class="paramkey"></td>
389          <td></td>
390          <td class="paramtype">u32&#160;</td>
391          <td class="paramname"><em>csMask</em>, </td>
392        </tr>
393        <tr>
394          <td class="paramkey"></td>
395          <td></td>
396          <td class="paramtype">u8&#160;</td>
397          <td class="paramname"><em>regAddr</em>, </td>
398        </tr>
399        <tr>
400          <td class="paramkey"></td>
401          <td></td>
402          <td class="paramtype">u8&#160;</td>
403          <td class="paramname"><em>txByte</em>&#160;</td>
404        </tr>
405        <tr>
406          <td></td>
407          <td>)</td>
408          <td></td><td></td>
409        </tr>
410      </table>
411</div><div class="memdoc">
412
413<p>Writes the specified register value to the selected AD9512 clock buffers. </p>
414<dl class="params"><dt>Parameters</dt><dd>
415  <table class="params">
416    <tr><td class="paramname">baseaddr</td><td>Base memory address of w3_clock_controller pcore </td></tr>
417    <tr><td class="paramname">csMask</td><td>OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS </td></tr>
418    <tr><td class="paramname">regAddr</td><td>Address of register to write, in [0x00, 0x5A] </td></tr>
419    <tr><td class="paramname">txByte</td><td>8-bit value to write </td></tr>
420  </table>
421  </dd>
422</dl>
423
424</div>
425</div>
426</div><!-- contents -->
427</div><!-- doc-content -->
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430  <ul>
431    <li class="footer">Generated on Tue Feb 26 2013 10:41:31 for w3_clock_controller Driver by doxygen v1.8.3</li>
432  </ul>
433</div>
434</body>
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