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int | clk_init (u32 baseaddr, u8 clkDiv) |
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int | clk_config_outputs (u32 baseaddr, u8 clkOutMode, u32 clkOutSel) |
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int | clk_config_input_rf_ref (u32 baseaddr, u8 clkInSel) |
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u16 | clk_config_read_clkmod_status (u32 baseaddr) |
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int | clk_config_dividers (u32 baseaddr, u8 clkDiv, u32 clkOutSel) |
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u32 | clk_spi_read (u32 baseaddr, u32 csMask, u8 regAddr) |
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void | clk_spi_write (u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte) |
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Example:
ad_init(CLK_BASEADDR, 3);
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC | CLK_RFREF_OUTSEL_FMC));
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
int clk_init |
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u32 |
baseaddr, |
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u8 |
clkDiv |
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) |
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Initializes the clock controller. This function must be called once at boot before any AD or RF operations will work. Default config is:
- On board 80MHz TCXO used as source for sampling and RF ref clock buffers
- 80MHz clock driven to FPGA, RF A and RF B ADC/DACs
- 40MHz clock driven to RF A and B transceivers
- FMC and clock module header clocks disabled
- Parameters
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baseaddr | Base memory address of w3_clock_controller pcore |
clkDiv | Clock divider for SPI serial clock (set to 3 for 160MHz bus) |
int clk_config_outputs |
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u32 |
baseaddr, |
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u8 |
clkOutMode, |
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u32 |
clkOutSel |
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) |
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Configures which outputs are en/disabled in both AD9512 clock buffers.
- Parameters
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baseaddr | Base memory address of w3_clock_controller pcore |
clkOutMode | New mode for selected clock outputs; must be CLK_OUTPUT_ON or CLK_OUTPUT_OFF |
clkOutSel | Masks to select which clock outputs to affect; must be OR'd combination of:
Mask | Selected Output |
CLK_SAMP_OUTSEL_FMC | Sampling clock buffer to FMC slot |
CLK_SAMP_OUTSEL_CLKMODHDR | Sampling clock buffer to clock module header |
CLK_SAMP_OUTSEL_FPGA | Sampling clock buffer to FPGA |
CLK_SAMP_OUTSEL_AD_RFA | Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) |
CLK_SAMP_OUTSEL_AD_RFB | Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) |
CLK_RFREF_OUTSEL_FMC | RF ref clock buffer to FMC |
CLK_RFREF_OUTSEL_CLKMODHDR | RF ref clock buffer to clock module header |
CLK_RFREF_OUTSEL_RFAB | RF ref clock buffer to RF A and B transceivers |
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- Returns
- Returns 0 on success, -1 for invalid parameters
int clk_config_input_rf_ref |
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u32 |
baseaddr, |
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u8 |
clkInSel |
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) |
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Configures whether the RF Reference Buffer uses the on-board or off-board clock source.
- Parameters
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baseaddr | Base memory address of w3_clock_controller pcore |
clkInSel | Clock source mask, must be either CLK_INSEL_ONBOARD (for on-board oscillator) or CLK_INSEL_CLKMOD (for off-board clock via clock module header)
Mask | Selected Input |
CLK_INSEL_ONBOARD | Selects on-board TCXO as RF Reference clock source (AD9512 CLK1/CLK1B port) |
CLK_INSEL_CLKMOD | Selects off-board clock from clock module header as RF Reference clock source (AD9512 CLK2/CLK2B port) |
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- Returns
- Returns 0 on success, -1 for invalid parameters
u16 clk_config_read_clkmod_status |
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u32 |
baseaddr | ) |
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Reads the status pins of the currently installed clock module.
- Parameters
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baseaddr | Base memory address of w3_clock_controller pcore |
- Returns
- Returns a 16-bit value for the clock module status; the meaning of the status bits depends on the currently installed module. For CM-MMCX the 2 LSB of the return are set by the 2-bit SIP switch, where an asserted switch (actuator down, towards the mounting bolt) returns 0. Reading the SIP switch when no CM-MMCX is installed will return 0x3 (both switches = 1).
int clk_config_dividers |
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u32 |
baseaddr, |
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u8 |
clkDiv, |
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u32 |
clkOutSel |
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) |
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Configures output dividers in both AD9512 clock buffers.
- Parameters
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baseaddr | Base memory address of w3_clock_controller pcore |
clkDiv | Divider value to set; must be 1 or even integer in [2,32] |
clkOutSel | Masks to select which clock outputs to affect; must be OR'd combination of:
Mask | Selected Output |
CLK_SAMP_OUTSEL_FMC | Sampling clock buffer to FMC slot |
CLK_SAMP_OUTSEL_CLKMODHDR | Sampling clock buffer to clock module header |
CLK_SAMP_OUTSEL_FPGA | Sampling clock buffer to FPGA |
CLK_SAMP_OUTSEL_AD_RFA | Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) |
CLK_SAMP_OUTSEL_AD_RFB | Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) |
CLK_RFREF_OUTSEL_FMC | RF ref clock buffer to FMC |
CLK_RFREF_OUTSEL_CLKMODHDR | RF ref clock buffer to clock module header |
CLK_RFREF_OUTSEL_RFAB | RF ref clock buffer to RF A and B transceivers |
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- Returns
- Returns 0 on success, -1 for invalid parameters
u32 clk_spi_read |
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u32 |
baseaddr, |
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u32 |
csMask, |
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u8 |
regAddr |
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) |
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Reads the specified register from both AD9963s.
- Parameters
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baseaddr | Base memory address of w3_clock_controller pcore |
csMask | OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS |
regAddr | Address of register to read, in [0x00, 0x5A] |
- Returns
- Returns concatenation of current values of the specified register for both AD9512s (if selected); samp clock buffer is LSB
void clk_spi_write |
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u32 |
baseaddr, |
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u32 |
csMask, |
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u8 |
regAddr, |
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u8 |
txByte |
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) |
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Writes the specified register value to the selected AD9512 clock buffers.
- Parameters
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baseaddr | Base memory address of w3_clock_controller pcore |
csMask | OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS |
regAddr | Address of register to write, in [0x00, 0x5A] |
txByte | 8-bit value to write |