source: PlatformSupport/CustomPeripherals/pcores/w3_userio_axi_v1_02_a/doc/html/api/group__dbg__hdr.html

Last change on this file was 5544, checked in by murphpo, 8 years ago

updating API docs for userio core
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1<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
2<html xmlns="http://www.w3.org/1999/xhtml">
3<head>
4<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
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6<title>w3_userio driver: Debug Header I/O</title>
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24 <tbody>
25 <tr style="height: 56px;">
26  <td style="padding-left: 0.5em;">
27   <div id="projectname">w3_userio driver
28   </div>
29   <div id="projectbrief">Driver for WARP v3 user IO control core (w3_userio_axi_v1_02_a)</div>
30  </td>
31 </tr>
32 </tbody>
33</table>
34</div>
35<!-- end header part -->
36<!-- Generated by Doxygen 1.8.11 -->
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38    <ul class="tablist">
39      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
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50  <div id="splitbar" style="-moz-user-select:none;" 
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53</div>
54<script type="text/javascript">
55$(document).ready(function(){initNavTree('group__dbg__hdr.html','');});
56</script>
57<div id="doc-content">
58<div class="header">
59  <div class="summary">
60<a href="#define-members">Macros</a>  </div>
61  <div class="headertitle">
62<div class="title">Debug Header I/O</div>  </div>
63</div><!--header-->
64<div class="contents">
65<table class="memberdecls">
66<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
67Macros</h2></td></tr>
68<tr class="memitem:ga90810e0ed839c6465d55c6de5a63091a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#ga90810e0ed839c6465d55c6de5a63091a">W3_USERIO_DBG_HDR_DIR_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
69<tr class="separator:ga90810e0ed839c6465d55c6de5a63091a"><td class="memSeparator" colspan="2">&#160;</td></tr>
70<tr class="memitem:ga694b8eca6c09da3ffd6f350abbb18493"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
71<tr class="separator:ga694b8eca6c09da3ffd6f350abbb18493"><td class="memSeparator" colspan="2">&#160;</td></tr>
72<tr class="memitem:gadfa8d6176393d6717bd71b7a4e7acef2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#gadfa8d6176393d6717bd71b7a4e7acef2">DBG_HDR_DIR_OUTPUT</a>&#160;&#160;&#160;0x0</td></tr>
73<tr class="separator:gadfa8d6176393d6717bd71b7a4e7acef2"><td class="memSeparator" colspan="2">&#160;</td></tr>
74<tr class="memitem:ga8e3b44c9af8ba8394957dd3aeabc499a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#ga8e3b44c9af8ba8394957dd3aeabc499a">DBG_HDR_DIR_INPUT</a>&#160;&#160;&#160;0x1</td></tr>
75<tr class="separator:ga8e3b44c9af8ba8394957dd3aeabc499a"><td class="memSeparator" colspan="2">&#160;</td></tr>
76<tr class="memitem:ga1dbb3c46f5d55a69f9322ec5d9c2a749"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#ga1dbb3c46f5d55a69f9322ec5d9c2a749">userio_set_dbg_hdr_io_dir</a>(baseaddr,  dir,  pin_mask)</td></tr>
77<tr class="separator:ga1dbb3c46f5d55a69f9322ec5d9c2a749"><td class="memSeparator" colspan="2">&#160;</td></tr>
78<tr class="memitem:ga2483beeadb03db2a0bf29fd41e9e1e4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#ga2483beeadb03db2a0bf29fd41e9e1e4d">userio_set_dbg_hdr_out</a>(baseaddr,  pin_mask)</td></tr>
79<tr class="separator:ga2483beeadb03db2a0bf29fd41e9e1e4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
80<tr class="memitem:ga4cf0e090e17c0aa1c2e772c448ee7a66"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#ga4cf0e090e17c0aa1c2e772c448ee7a66">userio_clear_dbg_hdr_out</a>(baseaddr,  pin_mask)</td></tr>
81<tr class="separator:ga4cf0e090e17c0aa1c2e772c448ee7a66"><td class="memSeparator" colspan="2">&#160;</td></tr>
82<tr class="memitem:ga89fae3b08f3fcec4cef5384bedd1d8b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#ga89fae3b08f3fcec4cef5384bedd1d8b9">userio_write_dbg_hdr_out</a>(baseaddr,  val)</td></tr>
83<tr class="separator:ga89fae3b08f3fcec4cef5384bedd1d8b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
84<tr class="memitem:gab99a80935a05df4539f6bee32de5248a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dbg__hdr.html#gab99a80935a05df4539f6bee32de5248a">userio_read_dbg_hdr_io</a>(baseaddr)&#160;&#160;&#160;(Xil_In32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET) &amp; <a class="el" href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a>)</td></tr>
85<tr class="separator:gab99a80935a05df4539f6bee32de5248a"><td class="memSeparator" colspan="2">&#160;</td></tr>
86</table>
87<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
88<p>The userio core implements an array of bi-directional buffers that can be routed to the WARP v3 board's debug header. The direction of each pin is configured at run time. This is similar to the Xilinx axi_gpio core. However the w3_userio implmenetaiton supports reading the current value of both inputs (like axi_gpi) and outputs (unlike axi_gpio). This allows read-modify-write of output bits, permitting simultaneous use of the debug header pins from multiple CPUs. </p>
89<h2 class="groupheader">Macro Definition Documentation</h2>
90<a class="anchor" id="ga90810e0ed839c6465d55c6de5a63091a"></a>
91<div class="memitem">
92<div class="memproto">
93      <table class="memname">
94        <tr>
95          <td class="memname">#define W3_USERIO_DBG_HDR_DIR_MASK&#160;&#160;&#160;0xFFFF0000</td>
96        </tr>
97      </table>
98</div><div class="memdoc">
99
100<p>Mask for IOB direction control bits (1 per pin) </p>
101
102</div>
103</div>
104<a class="anchor" id="ga694b8eca6c09da3ffd6f350abbb18493"></a>
105<div class="memitem">
106<div class="memproto">
107      <table class="memname">
108        <tr>
109          <td class="memname">#define W3_USERIO_DBG_HDR_VAL_MASK&#160;&#160;&#160;0x0000FFFF</td>
110        </tr>
111      </table>
112</div><div class="memdoc">
113
114<p>Mask for IOB data value bits (1 per pin) </p>
115
116</div>
117</div>
118<a class="anchor" id="gadfa8d6176393d6717bd71b7a4e7acef2"></a>
119<div class="memitem">
120<div class="memproto">
121      <table class="memname">
122        <tr>
123          <td class="memname">#define DBG_HDR_DIR_OUTPUT&#160;&#160;&#160;0x0</td>
124        </tr>
125      </table>
126</div><div class="memdoc">
127
128<p>Value for dir argument to <a class="el" href="group__dbg__hdr.html#ga1dbb3c46f5d55a69f9322ec5d9c2a749" title="Sets direction (DBG_HDR_DIR_OUTPUT or DBG_HDR_DIR_INPUT) of pins specified in pin_mask. ">userio_set_dbg_hdr_io_dir()</a> to set IOB as Output. </p>
129
130</div>
131</div>
132<a class="anchor" id="ga8e3b44c9af8ba8394957dd3aeabc499a"></a>
133<div class="memitem">
134<div class="memproto">
135      <table class="memname">
136        <tr>
137          <td class="memname">#define DBG_HDR_DIR_INPUT&#160;&#160;&#160;0x1</td>
138        </tr>
139      </table>
140</div><div class="memdoc">
141
142<p>Value for dir argument to <a class="el" href="group__dbg__hdr.html#ga1dbb3c46f5d55a69f9322ec5d9c2a749" title="Sets direction (DBG_HDR_DIR_OUTPUT or DBG_HDR_DIR_INPUT) of pins specified in pin_mask. ">userio_set_dbg_hdr_io_dir()</a> to set IOB as Input. </p>
143
144</div>
145</div>
146<a class="anchor" id="ga1dbb3c46f5d55a69f9322ec5d9c2a749"></a>
147<div class="memitem">
148<div class="memproto">
149      <table class="memname">
150        <tr>
151          <td class="memname">#define userio_set_dbg_hdr_io_dir</td>
152          <td>(</td>
153          <td class="paramtype">&#160;</td>
154          <td class="paramname">baseaddr, </td>
155        </tr>
156        <tr>
157          <td class="paramkey"></td>
158          <td></td>
159          <td class="paramtype">&#160;</td>
160          <td class="paramname">dir, </td>
161        </tr>
162        <tr>
163          <td class="paramkey"></td>
164          <td></td>
165          <td class="paramtype">&#160;</td>
166          <td class="paramname">pin_mask&#160;</td>
167        </tr>
168        <tr>
169          <td></td>
170          <td>)</td>
171          <td></td><td></td>
172        </tr>
173      </table>
174</div><div class="memdoc">
175<b>Value:</b><div class="fragment"><div class="line">Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \</div><div class="line">        (dir) ? \</div><div class="line">        (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) |  (((pin_mask) &lt;&lt; 16) &amp; <a class="code" href="group__dbg__hdr.html#ga90810e0ed839c6465d55c6de5a63091a">W3_USERIO_DBG_HDR_DIR_MASK</a>)) : \</div><div class="line">        (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) &amp; ~(((pin_mask) &lt;&lt; 16) &amp; <a class="code" href="group__dbg__hdr.html#ga90810e0ed839c6465d55c6de5a63091a">W3_USERIO_DBG_HDR_DIR_MASK</a>)))</div><div class="ttc" id="group__dbg__hdr_html_ga90810e0ed839c6465d55c6de5a63091a"><div class="ttname"><a href="group__dbg__hdr.html#ga90810e0ed839c6465d55c6de5a63091a">W3_USERIO_DBG_HDR_DIR_MASK</a></div><div class="ttdeci">#define W3_USERIO_DBG_HDR_DIR_MASK</div><div class="ttdoc">Mask for IOB direction control bits (1 per pin) </div><div class="ttdef"><b>Definition:</b> w3_userio.h:325</div></div>
176</div><!-- fragment -->
177<p>Sets direction (DBG_HDR_DIR_OUTPUT or DBG_HDR_DIR_INPUT) of pins specified in pin_mask. </p>
178
179</div>
180</div>
181<a class="anchor" id="ga2483beeadb03db2a0bf29fd41e9e1e4d"></a>
182<div class="memitem">
183<div class="memproto">
184      <table class="memname">
185        <tr>
186          <td class="memname">#define userio_set_dbg_hdr_out</td>
187          <td>(</td>
188          <td class="paramtype">&#160;</td>
189          <td class="paramname">baseaddr, </td>
190        </tr>
191        <tr>
192          <td class="paramkey"></td>
193          <td></td>
194          <td class="paramtype">&#160;</td>
195          <td class="paramname">pin_mask&#160;</td>
196        </tr>
197        <tr>
198          <td></td>
199          <td>)</td>
200          <td></td><td></td>
201        </tr>
202      </table>
203</div><div class="memdoc">
204<b>Value:</b><div class="fragment"><div class="line">Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \</div><div class="line">        (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) | ((pin_mask) &amp; <a class="code" href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a>)))</div><div class="ttc" id="group__dbg__hdr_html_ga694b8eca6c09da3ffd6f350abbb18493"><div class="ttname"><a href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a></div><div class="ttdeci">#define W3_USERIO_DBG_HDR_VAL_MASK</div><div class="ttdoc">Mask for IOB data value bits (1 per pin) </div><div class="ttdef"><b>Definition:</b> w3_userio.h:326</div></div>
205</div><!-- fragment -->
206<p>Asserts selected output pins. </p>
207
208</div>
209</div>
210<a class="anchor" id="ga4cf0e090e17c0aa1c2e772c448ee7a66"></a>
211<div class="memitem">
212<div class="memproto">
213      <table class="memname">
214        <tr>
215          <td class="memname">#define userio_clear_dbg_hdr_out</td>
216          <td>(</td>
217          <td class="paramtype">&#160;</td>
218          <td class="paramname">baseaddr, </td>
219        </tr>
220        <tr>
221          <td class="paramkey"></td>
222          <td></td>
223          <td class="paramtype">&#160;</td>
224          <td class="paramname">pin_mask&#160;</td>
225        </tr>
226        <tr>
227          <td></td>
228          <td>)</td>
229          <td></td><td></td>
230        </tr>
231      </table>
232</div><div class="memdoc">
233<b>Value:</b><div class="fragment"><div class="line">Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \</div><div class="line">        (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) &amp; ~((pin_mask) &amp; <a class="code" href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a>)))</div><div class="ttc" id="group__dbg__hdr_html_ga694b8eca6c09da3ffd6f350abbb18493"><div class="ttname"><a href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a></div><div class="ttdeci">#define W3_USERIO_DBG_HDR_VAL_MASK</div><div class="ttdoc">Mask for IOB data value bits (1 per pin) </div><div class="ttdef"><b>Definition:</b> w3_userio.h:326</div></div>
234</div><!-- fragment -->
235<p>De-asserts selected output pins. </p>
236
237</div>
238</div>
239<a class="anchor" id="ga89fae3b08f3fcec4cef5384bedd1d8b9"></a>
240<div class="memitem">
241<div class="memproto">
242      <table class="memname">
243        <tr>
244          <td class="memname">#define userio_write_dbg_hdr_out</td>
245          <td>(</td>
246          <td class="paramtype">&#160;</td>
247          <td class="paramname">baseaddr, </td>
248        </tr>
249        <tr>
250          <td class="paramkey"></td>
251          <td></td>
252          <td class="paramtype">&#160;</td>
253          <td class="paramname">val&#160;</td>
254        </tr>
255        <tr>
256          <td></td>
257          <td>)</td>
258          <td></td><td></td>
259        </tr>
260      </table>
261</div><div class="memdoc">
262<b>Value:</b><div class="fragment"><div class="line">Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \</div><div class="line">        ((Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) &amp; ~<a class="code" href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a>) | ((pin_mask) &amp; <a class="code" href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a>)))</div><div class="ttc" id="group__dbg__hdr_html_ga694b8eca6c09da3ffd6f350abbb18493"><div class="ttname"><a href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a></div><div class="ttdeci">#define W3_USERIO_DBG_HDR_VAL_MASK</div><div class="ttdoc">Mask for IOB data value bits (1 per pin) </div><div class="ttdef"><b>Definition:</b> w3_userio.h:326</div></div>
263</div><!-- fragment -->
264<p>Writes all output pins. </p>
265
266</div>
267</div>
268<a class="anchor" id="gab99a80935a05df4539f6bee32de5248a"></a>
269<div class="memitem">
270<div class="memproto">
271      <table class="memname">
272        <tr>
273          <td class="memname">#define userio_read_dbg_hdr_io</td>
274          <td>(</td>
275          <td class="paramtype">&#160;</td>
276          <td class="paramname">baseaddr</td><td>)</td>
277          <td>&#160;&#160;&#160;(Xil_In32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET) &amp; <a class="el" href="group__dbg__hdr.html#ga694b8eca6c09da3ffd6f350abbb18493">W3_USERIO_DBG_HDR_VAL_MASK</a>)</td>
278        </tr>
279      </table>
280</div><div class="memdoc">
281
282<p>Reads state of all pins (inputs and outputs) </p>
283
284</div>
285</div>
286</div><!-- contents -->
287</div><!-- doc-content -->
288<!-- start footer part -->
289<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
290  <ul>
291    <li class="footer">Generated on Wed Jun 29 2016 15:00:03 for w3_userio driver by doxygen v1.8.11</li>
292  </ul>
293</div>
294</body>
295</html>
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