Debug Header I/O

Macros
#define	W3_USERIO_DBG_HDR_DIR_MASK   0xFFFF0000
#define	W3_USERIO_DBG_HDR_VAL_MASK   0x0000FFFF
#define	DBG_HDR_DIR_OUTPUT   0x0
#define	DBG_HDR_DIR_INPUT   0x1
#define	userio_set_dbg_hdr_io_dir(baseaddr, dir, pin_mask)
#define	userio_set_dbg_hdr_out(baseaddr, pin_mask)
#define	userio_clear_dbg_hdr_out(baseaddr, pin_mask)
#define	userio_write_dbg_hdr_out(baseaddr, val)
#define	userio_read_dbg_hdr_io(baseaddr)   (Xil_In32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET) & W3_USERIO_DBG_HDR_VAL_MASK)

Detailed Description

The userio core implements an array of bi-directional buffers that can be routed to the WARP v3 board's debug header. The direction of each pin is configured at run time. This is similar to the Xilinx axi_gpio core. However the w3_userio implmenetaiton supports reading the current value of both inputs (like axi_gpi) and outputs (unlike axi_gpio). This allows read-modify-write of output bits, permitting simultaneous use of the debug header pins from multiple CPUs.

Macro Definition Documentation

#define W3_USERIO_DBG_HDR_DIR_MASK   0xFFFF0000

Mask for IOB direction control bits (1 per pin)

#define W3_USERIO_DBG_HDR_VAL_MASK   0x0000FFFF

Mask for IOB data value bits (1 per pin)

#define DBG_HDR_DIR_OUTPUT   0x0

Value for dir argument to userio_set_dbg_hdr_io_dir() to set IOB as Output.

#define DBG_HDR_DIR_INPUT   0x1

Value for dir argument to userio_set_dbg_hdr_io_dir() to set IOB as Input.

#define userio_set_dbg_hdr_io_dir	(		baseaddr,
			dir,
			pin_mask
	)

Value:

Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \
        (dir) ? \
        (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) |  (((pin_mask) << 16) & W3_USERIO_DBG_HDR_DIR_MASK)) : \
        (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~(((pin_mask) << 16) & W3_USERIO_DBG_HDR_DIR_MASK)))

Sets direction (DBG_HDR_DIR_OUTPUT or DBG_HDR_DIR_INPUT) of pins specified in pin_mask.

#define userio_set_dbg_hdr_out	(		baseaddr,
			pin_mask
	)

Value:

Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \
        (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) | ((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK)))

Asserts selected output pins.

#define userio_clear_dbg_hdr_out	(		baseaddr,
			pin_mask
	)

Value:

Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \
        (Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK)))

De-asserts selected output pins.

#define userio_write_dbg_hdr_out	(		baseaddr,
			val
	)

Value:

Xil_Out32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET, \
        ((Xil_In32(baseaddr + W3_USERIO_SLV_REG13_OFFSET) & ~W3_USERIO_DBG_HDR_VAL_MASK) | ((pin_mask) & W3_USERIO_DBG_HDR_VAL_MASK)))

Writes all output pins.

#define userio_read_dbg_hdr_io

(

baseaddr

)

(Xil_In32((baseaddr)+W3_USERIO_SLV_REG13_OFFSET) & W3_USERIO_DBG_HDR_VAL_MASK)

Reads state of all pins (inputs and outputs)