source: PlatformSupport/CustomPeripherals/pcores/w3_userio_axi_v1_02_a/doc/html/api/group__dna__read.html

Last change on this file was 5544, checked in by murphpo, 8 years ago

updating API docs for userio core
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1<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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6<title>w3_userio driver: Reading FPGA DNA</title>
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27   <div id="projectname">w3_userio driver
28   </div>
29   <div id="projectbrief">Driver for WARP v3 user IO control core (w3_userio_axi_v1_02_a)</div>
30  </td>
31 </tr>
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57<div id="doc-content">
58<div class="header">
59  <div class="summary">
60<a href="#define-members">Macros</a>  </div>
61  <div class="headertitle">
62<div class="title">Reading FPGA DNA</div>  </div>
63</div><!--header-->
64<div class="contents">
65<table class="memberdecls">
66<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
67Macros</h2></td></tr>
68<tr class="memitem:ga7ff5a375c154bd1a5b89cb2322060f5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dna__read.html#ga7ff5a375c154bd1a5b89cb2322060f5c">userio_read_fpga_dna_lsb</a>(baseaddr)&#160;&#160;&#160;Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET)</td></tr>
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70<tr class="memitem:ga4f964b56e8daa6afb8a4d26e42237b59"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dna__read.html#ga4f964b56e8daa6afb8a4d26e42237b59">userio_read_fpga_dna_msb</a>(baseaddr)&#160;&#160;&#160;Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET)</td></tr>
71<tr class="separator:ga4f964b56e8daa6afb8a4d26e42237b59"><td class="memSeparator" colspan="2">&#160;</td></tr>
72</table>
73<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
74<p>Every Virtex-6 FPGA has a unique "DNA" value embedded in the device. The w3_userio core implements logic to read this value into software-accessible registers. The DNA value is 56 bits, so two 32-bit registers are used to store the full value.</p>
75<p><b>Hardware requirements:</b> </p><ul>
76<li>
77A clock signal slower than 100MHz must be connected to the w3_userio core DNA_Port_Clk port </li>
78<li>
79The w3_userio core parameter INCLUDE_DNA_READ_LOGIC must be enabled </li>
80</ul>
81<p>If both requirements aren't met the DNA register values are undefined.</p>
82<p>The FPGA DNA value is also stored in the WARP v3 board EEPROM. Refer to the user guide EEPROM page for details. </p>
83<h2 class="groupheader">Macro Definition Documentation</h2>
84<a class="anchor" id="ga7ff5a375c154bd1a5b89cb2322060f5c"></a>
85<div class="memitem">
86<div class="memproto">
87      <table class="memname">
88        <tr>
89          <td class="memname">#define userio_read_fpga_dna_lsb</td>
90          <td>(</td>
91          <td class="paramtype">&#160;</td>
92          <td class="paramname">baseaddr</td><td>)</td>
93          <td>&#160;&#160;&#160;Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET)</td>
94        </tr>
95      </table>
96</div><div class="memdoc">
97
98<p>Returns the 32 LSB of the FPGA DNA. </p>
99
100</div>
101</div>
102<a class="anchor" id="ga4f964b56e8daa6afb8a4d26e42237b59"></a>
103<div class="memitem">
104<div class="memproto">
105      <table class="memname">
106        <tr>
107          <td class="memname">#define userio_read_fpga_dna_msb</td>
108          <td>(</td>
109          <td class="paramtype">&#160;</td>
110          <td class="paramname">baseaddr</td><td>)</td>
111          <td>&#160;&#160;&#160;Xil_In32(baseaddr+W3_USERIO_SLV_REG12_OFFSET)</td>
112        </tr>
113      </table>
114</div><div class="memdoc">
115
116<p>Returns the 24 MSB of the FPGA DNA. </p>
117
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