[1042] | 1 | -------------------------------------------------------------------------------- |
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| 2 | -- This file is owned and controlled by Xilinx and must be used -- |
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| 3 | -- solely for design, simulation, implementation and creation of -- |
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| 4 | -- design files limited to Xilinx devices or technologies. Use -- |
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| 5 | -- with non-Xilinx devices or technologies is expressly prohibited -- |
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| 6 | -- and immediately terminates your license. -- |
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| 7 | -- -- |
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| 8 | -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- |
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| 9 | -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- |
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| 10 | -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- |
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| 11 | -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- |
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| 12 | -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- |
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| 13 | -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- |
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| 14 | -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- |
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| 15 | -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- |
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| 16 | -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- |
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| 17 | -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- |
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| 18 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- |
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| 19 | -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
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| 20 | -- FOR A PARTICULAR PURPOSE. -- |
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| 21 | -- -- |
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| 22 | -- Xilinx products are not intended for use in life support -- |
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| 23 | -- appliances, devices, or systems. Use in such applications are -- |
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| 24 | -- expressly prohibited. -- |
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| 25 | -- -- |
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| 26 | -- (c) Copyright 1995-2007 Xilinx, Inc. -- |
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| 27 | -- All rights reserved. -- |
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| 28 | -------------------------------------------------------------------------------- |
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| 29 | -- You must compile the wrapper file adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e.vhd when simulating |
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| 30 | -- the core, adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e. When compiling the wrapper file, be sure to |
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| 31 | -- reference the XilinxCoreLib VHDL simulation library. For detailed |
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| 32 | -- instructions, please refer to the "CORE Generator Help". |
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| 33 | |
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| 34 | -- The synthesis directives "translate_off/translate_on" specified |
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| 35 | -- below are supported by Xilinx, Mentor Graphics and Synplicity |
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| 36 | -- synthesis tools. Ensure they are correct for your synthesis tool(s). |
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| 37 | |
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| 38 | LIBRARY ieee; |
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| 39 | USE ieee.std_logic_1164.ALL; |
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| 40 | -- synthesis translate_off |
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| 41 | Library XilinxCoreLib; |
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| 42 | -- synthesis translate_on |
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| 43 | ENTITY adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e IS |
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| 44 | port ( |
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| 45 | A: IN std_logic_VECTOR(32 downto 0); |
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| 46 | B: IN std_logic_VECTOR(32 downto 0); |
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| 47 | S: OUT std_logic_VECTOR(32 downto 0)); |
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| 48 | END adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e; |
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| 49 | |
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| 50 | ARCHITECTURE adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e_a OF adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e IS |
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| 51 | -- synthesis translate_off |
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| 52 | component wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e |
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| 53 | port ( |
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| 54 | A: IN std_logic_VECTOR(32 downto 0); |
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| 55 | B: IN std_logic_VECTOR(32 downto 0); |
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| 56 | S: OUT std_logic_VECTOR(32 downto 0)); |
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| 57 | end component; |
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| 58 | |
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| 59 | -- Configuration specification |
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| 60 | for all : wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e use entity XilinxCoreLib.C_ADDSUB_V7_0(behavioral) |
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| 61 | generic map( |
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| 62 | c_has_bypass_with_cin => 0, |
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| 63 | c_a_type => 0, |
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| 64 | c_has_sclr => 0, |
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| 65 | c_sync_priority => 1, |
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| 66 | c_has_aset => 0, |
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| 67 | c_has_b_out => 0, |
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| 68 | c_has_s => 1, |
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| 69 | c_has_q => 0, |
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| 70 | c_bypass_enable => 0, |
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| 71 | c_b_constant => 0, |
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| 72 | c_has_ovfl => 0, |
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| 73 | c_high_bit => 32, |
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| 74 | c_latency => 0, |
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| 75 | c_sinit_val => "0", |
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| 76 | c_has_bypass => 0, |
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| 77 | c_pipe_stages => 1, |
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| 78 | c_has_sset => 0, |
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| 79 | c_has_ainit => 0, |
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| 80 | c_has_a_signed => 0, |
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| 81 | c_has_q_c_out => 0, |
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| 82 | c_b_type => 0, |
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| 83 | c_has_add => 0, |
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| 84 | c_has_sinit => 0, |
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| 85 | c_has_b_in => 0, |
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| 86 | c_has_b_signed => 0, |
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| 87 | c_bypass_low => 0, |
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| 88 | c_enable_rlocs => 1, |
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| 89 | c_b_value => "0", |
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| 90 | c_add_mode => 1, |
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| 91 | c_has_aclr => 0, |
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| 92 | c_out_width => 33, |
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| 93 | c_ainit_val => "0000", |
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| 94 | c_low_bit => 0, |
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| 95 | c_has_q_ovfl => 0, |
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| 96 | c_has_q_b_out => 0, |
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| 97 | c_has_c_out => 0, |
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| 98 | c_b_width => 33, |
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| 99 | c_a_width => 33, |
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| 100 | c_sync_enable => 0, |
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| 101 | c_has_ce => 1, |
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| 102 | c_has_c_in => 0); |
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| 103 | -- synthesis translate_on |
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| 104 | BEGIN |
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| 105 | -- synthesis translate_off |
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| 106 | U0 : wrapped_adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e |
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| 107 | port map ( |
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| 108 | A => A, |
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| 109 | B => B, |
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| 110 | S => S); |
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| 111 | -- synthesis translate_on |
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| 112 | |
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| 113 | END adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e_a; |
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| 114 | |
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| 115 | -------------------------------------------------------------------------------- |
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| 116 | -- This file is owned and controlled by Xilinx and must be used -- |
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| 117 | -- solely for design, simulation, implementation and creation of -- |
---|
| 118 | -- design files limited to Xilinx devices or technologies. Use -- |
---|
| 119 | -- with non-Xilinx devices or technologies is expressly prohibited -- |
---|
| 120 | -- and immediately terminates your license. -- |
---|
| 121 | -- -- |
---|
| 122 | -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- |
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| 123 | -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- |
---|
| 124 | -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- |
---|
| 125 | -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- |
---|
| 126 | -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- |
---|
| 127 | -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- |
---|
| 128 | -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- |
---|
| 129 | -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- |
---|
| 130 | -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- |
---|
| 131 | -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- |
---|
| 132 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- |
---|
| 133 | -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
---|
| 134 | -- FOR A PARTICULAR PURPOSE. -- |
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| 135 | -- -- |
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| 136 | -- Xilinx products are not intended for use in life support -- |
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| 137 | -- appliances, devices, or systems. Use in such applications are -- |
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| 138 | -- expressly prohibited. -- |
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| 139 | -- -- |
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| 140 | -- (c) Copyright 1995-2007 Xilinx, Inc. -- |
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| 141 | -- All rights reserved. -- |
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| 142 | -------------------------------------------------------------------------------- |
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| 143 | -- You must compile the wrapper file binary_counter_virtex2p_7_0_b57302a6bcbb6876.vhd when simulating |
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| 144 | -- the core, binary_counter_virtex2p_7_0_b57302a6bcbb6876. When compiling the wrapper file, be sure to |
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| 145 | -- reference the XilinxCoreLib VHDL simulation library. For detailed |
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| 146 | -- instructions, please refer to the "CORE Generator Help". |
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| 147 | |
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| 148 | -- The synthesis directives "translate_off/translate_on" specified |
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| 149 | -- below are supported by Xilinx, Mentor Graphics and Synplicity |
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| 150 | -- synthesis tools. Ensure they are correct for your synthesis tool(s). |
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| 151 | |
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| 152 | LIBRARY ieee; |
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| 153 | USE ieee.std_logic_1164.ALL; |
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| 154 | -- synthesis translate_off |
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| 155 | Library XilinxCoreLib; |
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| 156 | -- synthesis translate_on |
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| 157 | ENTITY binary_counter_virtex2p_7_0_b57302a6bcbb6876 IS |
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| 158 | port ( |
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| 159 | Q: OUT std_logic_VECTOR(31 downto 0); |
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| 160 | CLK: IN std_logic; |
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| 161 | CE: IN std_logic; |
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| 162 | SINIT: IN std_logic); |
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| 163 | END binary_counter_virtex2p_7_0_b57302a6bcbb6876; |
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| 164 | |
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| 165 | ARCHITECTURE binary_counter_virtex2p_7_0_b57302a6bcbb6876_a OF binary_counter_virtex2p_7_0_b57302a6bcbb6876 IS |
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| 166 | -- synthesis translate_off |
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| 167 | component wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876 |
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| 168 | port ( |
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| 169 | Q: OUT std_logic_VECTOR(31 downto 0); |
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| 170 | CLK: IN std_logic; |
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| 171 | CE: IN std_logic; |
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| 172 | SINIT: IN std_logic); |
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| 173 | end component; |
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| 174 | |
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| 175 | -- Configuration specification |
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| 176 | for all : wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876 use entity XilinxCoreLib.C_COUNTER_BINARY_V7_0(behavioral) |
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| 177 | generic map( |
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| 178 | c_count_mode => 0, |
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| 179 | c_load_enable => 1, |
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| 180 | c_has_aset => 0, |
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| 181 | c_load_low => 0, |
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| 182 | c_count_to => "1111111111111111", |
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| 183 | c_sync_priority => 1, |
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| 184 | c_has_iv => 0, |
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| 185 | c_restrict_count => 0, |
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| 186 | c_has_sclr => 0, |
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| 187 | c_width => 32, |
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| 188 | c_has_q_thresh1 => 0, |
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| 189 | c_enable_rlocs => 0, |
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| 190 | c_has_q_thresh0 => 0, |
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| 191 | c_thresh1_value => "1111111111111111", |
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| 192 | c_has_load => 0, |
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| 193 | c_thresh_early => 1, |
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| 194 | c_has_up => 0, |
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| 195 | c_has_thresh1 => 0, |
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| 196 | c_has_thresh0 => 0, |
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| 197 | c_ainit_val => "0000", |
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| 198 | c_has_ce => 1, |
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| 199 | c_pipe_stages => 0, |
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| 200 | c_has_aclr => 0, |
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| 201 | c_sync_enable => 0, |
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| 202 | c_has_ainit => 0, |
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| 203 | c_sinit_val => "0000", |
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| 204 | c_has_sset => 0, |
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| 205 | c_has_sinit => 1, |
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| 206 | c_count_by => "0001", |
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| 207 | c_has_l => 0, |
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| 208 | c_thresh0_value => "1111111111111111"); |
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| 209 | -- synthesis translate_on |
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| 210 | BEGIN |
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| 211 | -- synthesis translate_off |
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| 212 | U0 : wrapped_binary_counter_virtex2p_7_0_b57302a6bcbb6876 |
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| 213 | port map ( |
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| 214 | Q => Q, |
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| 215 | CLK => CLK, |
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| 216 | CE => CE, |
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| 217 | SINIT => SINIT); |
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| 218 | -- synthesis translate_on |
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| 219 | |
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| 220 | END binary_counter_virtex2p_7_0_b57302a6bcbb6876_a; |
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| 221 | |
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| 222 | |
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| 223 | ------------------------------------------------------------------- |
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| 224 | -- System Generator version 10.1.2 VHDL source file. |
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| 225 | -- |
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| 226 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
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| 227 | -- text/file contains proprietary, confidential information of Xilinx, |
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| 228 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
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| 229 | -- copied and/or disclosed only pursuant to the terms of a valid license |
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| 230 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
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| 231 | -- this text/file solely for design, simulation, implementation and |
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| 232 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 233 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 234 | -- and immediately terminates your license unless covered by a separate |
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| 235 | -- agreement. |
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| 236 | -- |
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| 237 | -- Xilinx is providing this design, code, or information "as is" solely |
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| 238 | -- for use in developing programs and solutions for Xilinx devices. By |
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| 239 | -- providing this design, code, or information as one possible |
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| 240 | -- implementation of this feature, application or standard, Xilinx is |
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| 241 | -- making no representation that this implementation is free from any |
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| 242 | -- claims of infringement. You are responsible for obtaining any rights |
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| 243 | -- you may require for your implementation. Xilinx expressly disclaims |
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| 244 | -- any warranty whatsoever with respect to the adequacy of the |
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| 245 | -- implementation, including but not limited to warranties of |
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| 246 | -- merchantability or fitness for a particular purpose. |
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| 247 | -- |
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| 248 | -- Xilinx products are not intended for use in life support appliances, |
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| 249 | -- devices, or systems. Use in such applications is expressly prohibited. |
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| 250 | -- |
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| 251 | -- Any modifications that are made to the source code are done at the user's |
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| 252 | -- sole risk and will be unsupported. |
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| 253 | -- |
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| 254 | -- This copyright and support notice must be retained as part of this |
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| 255 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
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| 256 | -- reserved. |
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| 257 | ------------------------------------------------------------------- |
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| 258 | library IEEE; |
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| 259 | use IEEE.std_logic_1164.all; |
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| 260 | use IEEE.numeric_std.all; |
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| 261 | package conv_pkg is |
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| 262 | constant simulating : boolean := false |
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| 263 | -- synopsys translate_off |
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| 264 | or true |
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| 265 | -- synopsys translate_on |
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| 266 | ; |
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| 267 | constant xlUnsigned : integer := 1; |
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| 268 | constant xlSigned : integer := 2; |
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| 269 | constant xlWrap : integer := 1; |
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| 270 | constant xlSaturate : integer := 2; |
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| 271 | constant xlTruncate : integer := 1; |
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| 272 | constant xlRound : integer := 2; |
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| 273 | constant xlRoundBanker : integer := 3; |
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| 274 | constant xlAddMode : integer := 1; |
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| 275 | constant xlSubMode : integer := 2; |
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| 276 | attribute black_box : boolean; |
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| 277 | attribute syn_black_box : boolean; |
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| 278 | attribute fpga_dont_touch: string; |
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| 279 | attribute box_type : string; |
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| 280 | attribute keep : string; |
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| 281 | attribute syn_keep : boolean; |
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| 282 | function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned; |
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| 283 | function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector; |
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| 284 | function std_logic_vector_to_signed(inp : std_logic_vector) return signed; |
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| 285 | function signed_to_std_logic_vector(inp : signed) return std_logic_vector; |
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| 286 | function unsigned_to_signed(inp : unsigned) return signed; |
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| 287 | function signed_to_unsigned(inp : signed) return unsigned; |
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| 288 | function pos(inp : std_logic_vector; arith : INTEGER) return boolean; |
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| 289 | function all_same(inp: std_logic_vector) return boolean; |
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| 290 | function all_zeros(inp: std_logic_vector) return boolean; |
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| 291 | function is_point_five(inp: std_logic_vector) return boolean; |
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| 292 | function all_ones(inp: std_logic_vector) return boolean; |
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| 293 | function convert_type (inp : std_logic_vector; old_width, old_bin_pt, |
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| 294 | old_arith, new_width, new_bin_pt, new_arith, |
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| 295 | quantization, overflow : INTEGER) |
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| 296 | return std_logic_vector; |
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| 297 | function cast (inp : std_logic_vector; old_bin_pt, |
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| 298 | new_width, new_bin_pt, new_arith : INTEGER) |
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| 299 | return std_logic_vector; |
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| 300 | function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) |
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| 301 | return std_logic_vector; |
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| 302 | function s2u_slice (inp : signed; upper, lower : INTEGER) |
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| 303 | return unsigned; |
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| 304 | function u2u_slice (inp : unsigned; upper, lower : INTEGER) |
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| 305 | return unsigned; |
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| 306 | function s2s_cast (inp : signed; old_bin_pt, |
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| 307 | new_width, new_bin_pt : INTEGER) |
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| 308 | return signed; |
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| 309 | function u2s_cast (inp : unsigned; old_bin_pt, |
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| 310 | new_width, new_bin_pt : INTEGER) |
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| 311 | return signed; |
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| 312 | function s2u_cast (inp : signed; old_bin_pt, |
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| 313 | new_width, new_bin_pt : INTEGER) |
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| 314 | return unsigned; |
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| 315 | function u2u_cast (inp : unsigned; old_bin_pt, |
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| 316 | new_width, new_bin_pt : INTEGER) |
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| 317 | return unsigned; |
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| 318 | function u2v_cast (inp : unsigned; old_bin_pt, |
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| 319 | new_width, new_bin_pt : INTEGER) |
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| 320 | return std_logic_vector; |
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| 321 | function s2v_cast (inp : signed; old_bin_pt, |
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| 322 | new_width, new_bin_pt : INTEGER) |
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| 323 | return std_logic_vector; |
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| 324 | function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, |
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| 325 | new_width, new_bin_pt, new_arith : INTEGER) |
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| 326 | return std_logic_vector; |
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| 327 | function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, |
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| 328 | old_arith, new_width, new_bin_pt, |
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| 329 | new_arith : INTEGER) return std_logic_vector; |
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| 330 | function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, |
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| 331 | old_arith, new_width, new_bin_pt, |
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| 332 | new_arith : INTEGER) return std_logic_vector; |
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| 333 | function max_signed(width : INTEGER) return std_logic_vector; |
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| 334 | function min_signed(width : INTEGER) return std_logic_vector; |
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| 335 | function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, |
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| 336 | old_arith, new_width, new_bin_pt, new_arith |
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| 337 | : INTEGER) return std_logic_vector; |
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| 338 | function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, |
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| 339 | old_arith, new_width, new_bin_pt, new_arith : INTEGER) |
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| 340 | return std_logic_vector; |
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| 341 | function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER; |
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| 342 | function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) |
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| 343 | return INTEGER; |
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| 344 | function sign_ext(inp : std_logic_vector; new_width : INTEGER) |
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| 345 | return std_logic_vector; |
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| 346 | function zero_ext(inp : std_logic_vector; new_width : INTEGER) |
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| 347 | return std_logic_vector; |
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| 348 | function zero_ext(inp : std_logic; new_width : INTEGER) |
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| 349 | return std_logic_vector; |
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| 350 | function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) |
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| 351 | return std_logic_vector; |
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| 352 | function align_input(inp : std_logic_vector; old_width, delta, new_arith, |
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| 353 | new_width: INTEGER) |
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| 354 | return std_logic_vector; |
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| 355 | function pad_LSB(inp : std_logic_vector; new_width: integer) |
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| 356 | return std_logic_vector; |
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| 357 | function pad_LSB(inp : std_logic_vector; new_width, arith : integer) |
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| 358 | return std_logic_vector; |
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| 359 | function max(L, R: INTEGER) return INTEGER; |
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| 360 | function min(L, R: INTEGER) return INTEGER; |
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| 361 | function "="(left,right: STRING) return boolean; |
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| 362 | function boolean_to_signed (inp : boolean; width: integer) |
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| 363 | return signed; |
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| 364 | function boolean_to_unsigned (inp : boolean; width: integer) |
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| 365 | return unsigned; |
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| 366 | function boolean_to_vector (inp : boolean) |
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| 367 | return std_logic_vector; |
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| 368 | function std_logic_to_vector (inp : std_logic) |
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| 369 | return std_logic_vector; |
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| 370 | function integer_to_std_logic_vector (inp : integer; width, arith : integer) |
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| 371 | return std_logic_vector; |
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| 372 | function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) |
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| 373 | return integer; |
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| 374 | function std_logic_to_integer(constant inp : std_logic := '0') |
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| 375 | return integer; |
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| 376 | function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) |
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| 377 | return std_logic_vector; |
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| 378 | function bin_string_to_std_logic_vector (inp : string) |
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| 379 | return std_logic_vector; |
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| 380 | function hex_string_to_std_logic_vector (inp : string; width : integer) |
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| 381 | return std_logic_vector; |
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| 382 | function makeZeroBinStr (width : integer) return STRING; |
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| 383 | function and_reduce(inp: std_logic_vector) return std_logic; |
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| 384 | -- synopsys translate_off |
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| 385 | function is_binary_string_invalid (inp : string) |
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| 386 | return boolean; |
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| 387 | function is_binary_string_undefined (inp : string) |
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| 388 | return boolean; |
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| 389 | function is_XorU(inp : std_logic_vector) |
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| 390 | return boolean; |
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| 391 | function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) |
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| 392 | return real; |
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| 393 | function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) |
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| 394 | return real; |
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| 395 | function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) |
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| 396 | return std_logic_vector; |
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| 397 | function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) |
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| 398 | return std_logic_vector; |
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| 399 | constant display_precision : integer := 20; |
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| 400 | function real_to_string (inp : real) return string; |
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| 401 | function valid_bin_string(inp : string) return boolean; |
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| 402 | function std_logic_vector_to_bin_string(inp : std_logic_vector) return string; |
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| 403 | function std_logic_to_bin_string(inp : std_logic) return string; |
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| 404 | function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) |
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| 405 | return string; |
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| 406 | function real_to_bin_string(inp : real; width, bin_pt, arith : integer) |
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| 407 | return string; |
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| 408 | type stdlogic_to_char_t is array(std_logic) of character; |
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| 409 | constant to_char : stdlogic_to_char_t := ( |
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| 410 | 'U' => 'U', |
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| 411 | 'X' => 'X', |
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| 412 | '0' => '0', |
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| 413 | '1' => '1', |
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| 414 | 'Z' => 'Z', |
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| 415 | 'W' => 'W', |
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| 416 | 'L' => 'L', |
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| 417 | 'H' => 'H', |
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| 418 | '-' => '-'); |
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| 419 | -- synopsys translate_on |
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| 420 | end conv_pkg; |
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| 421 | package body conv_pkg is |
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| 422 | function std_logic_vector_to_unsigned(inp : std_logic_vector) |
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| 423 | return unsigned |
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| 424 | is |
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| 425 | begin |
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| 426 | return unsigned (inp); |
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| 427 | end; |
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| 428 | function unsigned_to_std_logic_vector(inp : unsigned) |
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| 429 | return std_logic_vector |
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| 430 | is |
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| 431 | begin |
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| 432 | return std_logic_vector(inp); |
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| 433 | end; |
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| 434 | function std_logic_vector_to_signed(inp : std_logic_vector) |
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| 435 | return signed |
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| 436 | is |
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| 437 | begin |
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| 438 | return signed (inp); |
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| 439 | end; |
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| 440 | function signed_to_std_logic_vector(inp : signed) |
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| 441 | return std_logic_vector |
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| 442 | is |
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| 443 | begin |
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| 444 | return std_logic_vector(inp); |
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| 445 | end; |
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| 446 | function unsigned_to_signed (inp : unsigned) |
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| 447 | return signed |
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| 448 | is |
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| 449 | begin |
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| 450 | return signed(std_logic_vector(inp)); |
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| 451 | end; |
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| 452 | function signed_to_unsigned (inp : signed) |
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| 453 | return unsigned |
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| 454 | is |
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| 455 | begin |
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| 456 | return unsigned(std_logic_vector(inp)); |
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| 457 | end; |
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| 458 | function pos(inp : std_logic_vector; arith : INTEGER) |
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| 459 | return boolean |
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| 460 | is |
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| 461 | constant width : integer := inp'length; |
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| 462 | variable vec : std_logic_vector(width-1 downto 0); |
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| 463 | begin |
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| 464 | vec := inp; |
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| 465 | if arith = xlUnsigned then |
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| 466 | return true; |
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| 467 | else |
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| 468 | if vec(width-1) = '0' then |
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| 469 | return true; |
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| 470 | else |
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| 471 | return false; |
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| 472 | end if; |
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| 473 | end if; |
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| 474 | return true; |
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| 475 | end; |
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| 476 | function max_signed(width : INTEGER) |
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| 477 | return std_logic_vector |
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| 478 | is |
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| 479 | variable ones : std_logic_vector(width-2 downto 0); |
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| 480 | variable result : std_logic_vector(width-1 downto 0); |
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| 481 | begin |
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| 482 | ones := (others => '1'); |
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| 483 | result(width-1) := '0'; |
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| 484 | result(width-2 downto 0) := ones; |
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| 485 | return result; |
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| 486 | end; |
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| 487 | function min_signed(width : INTEGER) |
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| 488 | return std_logic_vector |
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| 489 | is |
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| 490 | variable zeros : std_logic_vector(width-2 downto 0); |
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| 491 | variable result : std_logic_vector(width-1 downto 0); |
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| 492 | begin |
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| 493 | zeros := (others => '0'); |
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| 494 | result(width-1) := '1'; |
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| 495 | result(width-2 downto 0) := zeros; |
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| 496 | return result; |
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| 497 | end; |
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| 498 | function and_reduce(inp: std_logic_vector) return std_logic |
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| 499 | is |
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| 500 | variable result: std_logic; |
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| 501 | constant width : integer := inp'length; |
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| 502 | variable vec : std_logic_vector(width-1 downto 0); |
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| 503 | begin |
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| 504 | vec := inp; |
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| 505 | result := vec(0); |
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| 506 | if width > 1 then |
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| 507 | for i in 1 to width-1 loop |
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| 508 | result := result and vec(i); |
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| 509 | end loop; |
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| 510 | end if; |
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| 511 | return result; |
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| 512 | end; |
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| 513 | function all_same(inp: std_logic_vector) return boolean |
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| 514 | is |
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| 515 | variable result: boolean; |
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| 516 | constant width : integer := inp'length; |
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| 517 | variable vec : std_logic_vector(width-1 downto 0); |
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| 518 | begin |
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| 519 | vec := inp; |
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| 520 | result := true; |
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| 521 | if width > 0 then |
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| 522 | for i in 1 to width-1 loop |
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| 523 | if vec(i) /= vec(0) then |
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| 524 | result := false; |
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| 525 | end if; |
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| 526 | end loop; |
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| 527 | end if; |
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| 528 | return result; |
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| 529 | end; |
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| 530 | function all_zeros(inp: std_logic_vector) |
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| 531 | return boolean |
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| 532 | is |
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| 533 | constant width : integer := inp'length; |
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| 534 | variable vec : std_logic_vector(width-1 downto 0); |
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| 535 | variable zero : std_logic_vector(width-1 downto 0); |
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| 536 | variable result : boolean; |
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| 537 | begin |
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| 538 | zero := (others => '0'); |
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| 539 | vec := inp; |
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| 540 | -- synopsys translate_off |
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| 541 | if (is_XorU(vec)) then |
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| 542 | return false; |
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| 543 | end if; |
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| 544 | -- synopsys translate_on |
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| 545 | if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then |
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| 546 | result := true; |
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| 547 | else |
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| 548 | result := false; |
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| 549 | end if; |
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| 550 | return result; |
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| 551 | end; |
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| 552 | function is_point_five(inp: std_logic_vector) |
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| 553 | return boolean |
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| 554 | is |
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| 555 | constant width : integer := inp'length; |
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| 556 | variable vec : std_logic_vector(width-1 downto 0); |
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| 557 | variable result : boolean; |
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| 558 | begin |
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| 559 | vec := inp; |
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| 560 | -- synopsys translate_off |
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| 561 | if (is_XorU(vec)) then |
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| 562 | return false; |
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| 563 | end if; |
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| 564 | -- synopsys translate_on |
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| 565 | if (width > 1) then |
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| 566 | if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then |
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| 567 | result := true; |
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| 568 | else |
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| 569 | result := false; |
---|
| 570 | end if; |
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| 571 | else |
---|
| 572 | if (vec(width-1) = '1') then |
---|
| 573 | result := true; |
---|
| 574 | else |
---|
| 575 | result := false; |
---|
| 576 | end if; |
---|
| 577 | end if; |
---|
| 578 | return result; |
---|
| 579 | end; |
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| 580 | function all_ones(inp: std_logic_vector) |
---|
| 581 | return boolean |
---|
| 582 | is |
---|
| 583 | constant width : integer := inp'length; |
---|
| 584 | variable vec : std_logic_vector(width-1 downto 0); |
---|
| 585 | variable one : std_logic_vector(width-1 downto 0); |
---|
| 586 | variable result : boolean; |
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| 587 | begin |
---|
| 588 | one := (others => '1'); |
---|
| 589 | vec := inp; |
---|
| 590 | -- synopsys translate_off |
---|
| 591 | if (is_XorU(vec)) then |
---|
| 592 | return false; |
---|
| 593 | end if; |
---|
| 594 | -- synopsys translate_on |
---|
| 595 | if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then |
---|
| 596 | result := true; |
---|
| 597 | else |
---|
| 598 | result := false; |
---|
| 599 | end if; |
---|
| 600 | return result; |
---|
| 601 | end; |
---|
| 602 | function full_precision_num_width(quantization, overflow, old_width, |
---|
| 603 | old_bin_pt, old_arith, |
---|
| 604 | new_width, new_bin_pt, new_arith : INTEGER) |
---|
| 605 | return integer |
---|
| 606 | is |
---|
| 607 | variable result : integer; |
---|
| 608 | begin |
---|
| 609 | result := old_width + 2; |
---|
| 610 | return result; |
---|
| 611 | end; |
---|
| 612 | function quantized_num_width(quantization, overflow, old_width, old_bin_pt, |
---|
| 613 | old_arith, new_width, new_bin_pt, new_arith |
---|
| 614 | : INTEGER) |
---|
| 615 | return integer |
---|
| 616 | is |
---|
| 617 | variable right_of_dp, left_of_dp, result : integer; |
---|
| 618 | begin |
---|
| 619 | right_of_dp := max(new_bin_pt, old_bin_pt); |
---|
| 620 | left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt)); |
---|
| 621 | result := (old_width + 2) + (new_bin_pt - old_bin_pt); |
---|
| 622 | return result; |
---|
| 623 | end; |
---|
| 624 | function convert_type (inp : std_logic_vector; old_width, old_bin_pt, |
---|
| 625 | old_arith, new_width, new_bin_pt, new_arith, |
---|
| 626 | quantization, overflow : INTEGER) |
---|
| 627 | return std_logic_vector |
---|
| 628 | is |
---|
| 629 | constant fp_width : integer := |
---|
| 630 | full_precision_num_width(quantization, overflow, old_width, |
---|
| 631 | old_bin_pt, old_arith, new_width, |
---|
| 632 | new_bin_pt, new_arith); |
---|
| 633 | constant fp_bin_pt : integer := old_bin_pt; |
---|
| 634 | constant fp_arith : integer := old_arith; |
---|
| 635 | variable full_precision_result : std_logic_vector(fp_width-1 downto 0); |
---|
| 636 | constant q_width : integer := |
---|
| 637 | quantized_num_width(quantization, overflow, old_width, old_bin_pt, |
---|
| 638 | old_arith, new_width, new_bin_pt, new_arith); |
---|
| 639 | constant q_bin_pt : integer := new_bin_pt; |
---|
| 640 | constant q_arith : integer := old_arith; |
---|
| 641 | variable quantized_result : std_logic_vector(q_width-1 downto 0); |
---|
| 642 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 643 | begin |
---|
| 644 | result := (others => '0'); |
---|
| 645 | full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt, |
---|
| 646 | fp_arith); |
---|
| 647 | if (quantization = xlRound) then |
---|
| 648 | quantized_result := round_towards_inf(full_precision_result, |
---|
| 649 | fp_width, fp_bin_pt, |
---|
| 650 | fp_arith, q_width, q_bin_pt, |
---|
| 651 | q_arith); |
---|
| 652 | elsif (quantization = xlRoundBanker) then |
---|
| 653 | quantized_result := round_towards_even(full_precision_result, |
---|
| 654 | fp_width, fp_bin_pt, |
---|
| 655 | fp_arith, q_width, q_bin_pt, |
---|
| 656 | q_arith); |
---|
| 657 | else |
---|
| 658 | quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt, |
---|
| 659 | fp_arith, q_width, q_bin_pt, q_arith); |
---|
| 660 | end if; |
---|
| 661 | if (overflow = xlSaturate) then |
---|
| 662 | result := saturation_arith(quantized_result, q_width, q_bin_pt, |
---|
| 663 | q_arith, new_width, new_bin_pt, new_arith); |
---|
| 664 | else |
---|
| 665 | result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith, |
---|
| 666 | new_width, new_bin_pt, new_arith); |
---|
| 667 | end if; |
---|
| 668 | return result; |
---|
| 669 | end; |
---|
| 670 | function cast (inp : std_logic_vector; old_bin_pt, new_width, |
---|
| 671 | new_bin_pt, new_arith : INTEGER) |
---|
| 672 | return std_logic_vector |
---|
| 673 | is |
---|
| 674 | constant old_width : integer := inp'length; |
---|
| 675 | constant left_of_dp : integer := (new_width - new_bin_pt) |
---|
| 676 | - (old_width - old_bin_pt); |
---|
| 677 | constant right_of_dp : integer := (new_bin_pt - old_bin_pt); |
---|
| 678 | variable vec : std_logic_vector(old_width-1 downto 0); |
---|
| 679 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 680 | variable j : integer; |
---|
| 681 | begin |
---|
| 682 | vec := inp; |
---|
| 683 | for i in new_width-1 downto 0 loop |
---|
| 684 | j := i - right_of_dp; |
---|
| 685 | if ( j > old_width-1) then |
---|
| 686 | if (new_arith = xlUnsigned) then |
---|
| 687 | result(i) := '0'; |
---|
| 688 | else |
---|
| 689 | result(i) := vec(old_width-1); |
---|
| 690 | end if; |
---|
| 691 | elsif ( j >= 0) then |
---|
| 692 | result(i) := vec(j); |
---|
| 693 | else |
---|
| 694 | result(i) := '0'; |
---|
| 695 | end if; |
---|
| 696 | end loop; |
---|
| 697 | return result; |
---|
| 698 | end; |
---|
| 699 | function vec_slice (inp : std_logic_vector; upper, lower : INTEGER) |
---|
| 700 | return std_logic_vector |
---|
| 701 | is |
---|
| 702 | begin |
---|
| 703 | return inp(upper downto lower); |
---|
| 704 | end; |
---|
| 705 | function s2u_slice (inp : signed; upper, lower : INTEGER) |
---|
| 706 | return unsigned |
---|
| 707 | is |
---|
| 708 | begin |
---|
| 709 | return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); |
---|
| 710 | end; |
---|
| 711 | function u2u_slice (inp : unsigned; upper, lower : INTEGER) |
---|
| 712 | return unsigned |
---|
| 713 | is |
---|
| 714 | begin |
---|
| 715 | return unsigned(vec_slice(std_logic_vector(inp), upper, lower)); |
---|
| 716 | end; |
---|
| 717 | function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER) |
---|
| 718 | return signed |
---|
| 719 | is |
---|
| 720 | begin |
---|
| 721 | return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); |
---|
| 722 | end; |
---|
| 723 | function s2u_cast (inp : signed; old_bin_pt, new_width, |
---|
| 724 | new_bin_pt : INTEGER) |
---|
| 725 | return unsigned |
---|
| 726 | is |
---|
| 727 | begin |
---|
| 728 | return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned)); |
---|
| 729 | end; |
---|
| 730 | function u2s_cast (inp : unsigned; old_bin_pt, new_width, |
---|
| 731 | new_bin_pt : INTEGER) |
---|
| 732 | return signed |
---|
| 733 | is |
---|
| 734 | begin |
---|
| 735 | return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); |
---|
| 736 | end; |
---|
| 737 | function u2u_cast (inp : unsigned; old_bin_pt, new_width, |
---|
| 738 | new_bin_pt : INTEGER) |
---|
| 739 | return unsigned |
---|
| 740 | is |
---|
| 741 | begin |
---|
| 742 | return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned)); |
---|
| 743 | end; |
---|
| 744 | function u2v_cast (inp : unsigned; old_bin_pt, new_width, |
---|
| 745 | new_bin_pt : INTEGER) |
---|
| 746 | return std_logic_vector |
---|
| 747 | is |
---|
| 748 | begin |
---|
| 749 | return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned); |
---|
| 750 | end; |
---|
| 751 | function s2v_cast (inp : signed; old_bin_pt, new_width, |
---|
| 752 | new_bin_pt : INTEGER) |
---|
| 753 | return std_logic_vector |
---|
| 754 | is |
---|
| 755 | begin |
---|
| 756 | return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned); |
---|
| 757 | end; |
---|
| 758 | function boolean_to_signed (inp : boolean; width : integer) |
---|
| 759 | return signed |
---|
| 760 | is |
---|
| 761 | variable result : signed(width - 1 downto 0); |
---|
| 762 | begin |
---|
| 763 | result := (others => '0'); |
---|
| 764 | if inp then |
---|
| 765 | result(0) := '1'; |
---|
| 766 | else |
---|
| 767 | result(0) := '0'; |
---|
| 768 | end if; |
---|
| 769 | return result; |
---|
| 770 | end; |
---|
| 771 | function boolean_to_unsigned (inp : boolean; width : integer) |
---|
| 772 | return unsigned |
---|
| 773 | is |
---|
| 774 | variable result : unsigned(width - 1 downto 0); |
---|
| 775 | begin |
---|
| 776 | result := (others => '0'); |
---|
| 777 | if inp then |
---|
| 778 | result(0) := '1'; |
---|
| 779 | else |
---|
| 780 | result(0) := '0'; |
---|
| 781 | end if; |
---|
| 782 | return result; |
---|
| 783 | end; |
---|
| 784 | function boolean_to_vector (inp : boolean) |
---|
| 785 | return std_logic_vector |
---|
| 786 | is |
---|
| 787 | variable result : std_logic_vector(1 - 1 downto 0); |
---|
| 788 | begin |
---|
| 789 | result := (others => '0'); |
---|
| 790 | if inp then |
---|
| 791 | result(0) := '1'; |
---|
| 792 | else |
---|
| 793 | result(0) := '0'; |
---|
| 794 | end if; |
---|
| 795 | return result; |
---|
| 796 | end; |
---|
| 797 | function std_logic_to_vector (inp : std_logic) |
---|
| 798 | return std_logic_vector |
---|
| 799 | is |
---|
| 800 | variable result : std_logic_vector(1 - 1 downto 0); |
---|
| 801 | begin |
---|
| 802 | result(0) := inp; |
---|
| 803 | return result; |
---|
| 804 | end; |
---|
| 805 | function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith, |
---|
| 806 | new_width, new_bin_pt, new_arith : INTEGER) |
---|
| 807 | return std_logic_vector |
---|
| 808 | is |
---|
| 809 | constant right_of_dp : integer := (old_bin_pt - new_bin_pt); |
---|
| 810 | variable vec : std_logic_vector(old_width-1 downto 0); |
---|
| 811 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 812 | begin |
---|
| 813 | vec := inp; |
---|
| 814 | if right_of_dp >= 0 then |
---|
| 815 | if new_arith = xlUnsigned then |
---|
| 816 | result := zero_ext(vec(old_width-1 downto right_of_dp), new_width); |
---|
| 817 | else |
---|
| 818 | result := sign_ext(vec(old_width-1 downto right_of_dp), new_width); |
---|
| 819 | end if; |
---|
| 820 | else |
---|
| 821 | if new_arith = xlUnsigned then |
---|
| 822 | result := zero_ext(pad_LSB(vec, old_width + |
---|
| 823 | abs(right_of_dp)), new_width); |
---|
| 824 | else |
---|
| 825 | result := sign_ext(pad_LSB(vec, old_width + |
---|
| 826 | abs(right_of_dp)), new_width); |
---|
| 827 | end if; |
---|
| 828 | end if; |
---|
| 829 | return result; |
---|
| 830 | end; |
---|
| 831 | function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt, |
---|
| 832 | old_arith, new_width, new_bin_pt, new_arith |
---|
| 833 | : INTEGER) |
---|
| 834 | return std_logic_vector |
---|
| 835 | is |
---|
| 836 | constant right_of_dp : integer := (old_bin_pt - new_bin_pt); |
---|
| 837 | constant expected_new_width : integer := old_width - right_of_dp + 1; |
---|
| 838 | variable vec : std_logic_vector(old_width-1 downto 0); |
---|
| 839 | variable one_or_zero : std_logic_vector(new_width-1 downto 0); |
---|
| 840 | variable truncated_val : std_logic_vector(new_width-1 downto 0); |
---|
| 841 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 842 | begin |
---|
| 843 | vec := inp; |
---|
| 844 | if right_of_dp >= 0 then |
---|
| 845 | if new_arith = xlUnsigned then |
---|
| 846 | truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), |
---|
| 847 | new_width); |
---|
| 848 | else |
---|
| 849 | truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), |
---|
| 850 | new_width); |
---|
| 851 | end if; |
---|
| 852 | else |
---|
| 853 | if new_arith = xlUnsigned then |
---|
| 854 | truncated_val := zero_ext(pad_LSB(vec, old_width + |
---|
| 855 | abs(right_of_dp)), new_width); |
---|
| 856 | else |
---|
| 857 | truncated_val := sign_ext(pad_LSB(vec, old_width + |
---|
| 858 | abs(right_of_dp)), new_width); |
---|
| 859 | end if; |
---|
| 860 | end if; |
---|
| 861 | one_or_zero := (others => '0'); |
---|
| 862 | if (new_arith = xlSigned) then |
---|
| 863 | if (vec(old_width-1) = '0') then |
---|
| 864 | one_or_zero(0) := '1'; |
---|
| 865 | end if; |
---|
| 866 | if (right_of_dp >= 2) and (right_of_dp <= old_width) then |
---|
| 867 | if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then |
---|
| 868 | one_or_zero(0) := '1'; |
---|
| 869 | end if; |
---|
| 870 | end if; |
---|
| 871 | if (right_of_dp >= 1) and (right_of_dp <= old_width) then |
---|
| 872 | if vec(right_of_dp-1) = '0' then |
---|
| 873 | one_or_zero(0) := '0'; |
---|
| 874 | end if; |
---|
| 875 | else |
---|
| 876 | one_or_zero(0) := '0'; |
---|
| 877 | end if; |
---|
| 878 | else |
---|
| 879 | if (right_of_dp >= 1) and (right_of_dp <= old_width) then |
---|
| 880 | one_or_zero(0) := vec(right_of_dp-1); |
---|
| 881 | end if; |
---|
| 882 | end if; |
---|
| 883 | if new_arith = xlSigned then |
---|
| 884 | result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + |
---|
| 885 | std_logic_vector_to_signed(one_or_zero)); |
---|
| 886 | else |
---|
| 887 | result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + |
---|
| 888 | std_logic_vector_to_unsigned(one_or_zero)); |
---|
| 889 | end if; |
---|
| 890 | return result; |
---|
| 891 | end; |
---|
| 892 | function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt, |
---|
| 893 | old_arith, new_width, new_bin_pt, new_arith |
---|
| 894 | : INTEGER) |
---|
| 895 | return std_logic_vector |
---|
| 896 | is |
---|
| 897 | constant right_of_dp : integer := (old_bin_pt - new_bin_pt); |
---|
| 898 | constant expected_new_width : integer := old_width - right_of_dp + 1; |
---|
| 899 | variable vec : std_logic_vector(old_width-1 downto 0); |
---|
| 900 | variable one_or_zero : std_logic_vector(new_width-1 downto 0); |
---|
| 901 | variable truncated_val : std_logic_vector(new_width-1 downto 0); |
---|
| 902 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 903 | begin |
---|
| 904 | vec := inp; |
---|
| 905 | if right_of_dp >= 0 then |
---|
| 906 | if new_arith = xlUnsigned then |
---|
| 907 | truncated_val := zero_ext(vec(old_width-1 downto right_of_dp), |
---|
| 908 | new_width); |
---|
| 909 | else |
---|
| 910 | truncated_val := sign_ext(vec(old_width-1 downto right_of_dp), |
---|
| 911 | new_width); |
---|
| 912 | end if; |
---|
| 913 | else |
---|
| 914 | if new_arith = xlUnsigned then |
---|
| 915 | truncated_val := zero_ext(pad_LSB(vec, old_width + |
---|
| 916 | abs(right_of_dp)), new_width); |
---|
| 917 | else |
---|
| 918 | truncated_val := sign_ext(pad_LSB(vec, old_width + |
---|
| 919 | abs(right_of_dp)), new_width); |
---|
| 920 | end if; |
---|
| 921 | end if; |
---|
| 922 | one_or_zero := (others => '0'); |
---|
| 923 | if (right_of_dp >= 1) and (right_of_dp <= old_width) then |
---|
| 924 | if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then |
---|
| 925 | one_or_zero(0) := vec(right_of_dp-1); |
---|
| 926 | else |
---|
| 927 | one_or_zero(0) := vec(right_of_dp); |
---|
| 928 | end if; |
---|
| 929 | end if; |
---|
| 930 | if new_arith = xlSigned then |
---|
| 931 | result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) + |
---|
| 932 | std_logic_vector_to_signed(one_or_zero)); |
---|
| 933 | else |
---|
| 934 | result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) + |
---|
| 935 | std_logic_vector_to_unsigned(one_or_zero)); |
---|
| 936 | end if; |
---|
| 937 | return result; |
---|
| 938 | end; |
---|
| 939 | function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt, |
---|
| 940 | old_arith, new_width, new_bin_pt, new_arith |
---|
| 941 | : INTEGER) |
---|
| 942 | return std_logic_vector |
---|
| 943 | is |
---|
| 944 | constant left_of_dp : integer := (old_width - old_bin_pt) - |
---|
| 945 | (new_width - new_bin_pt); |
---|
| 946 | variable vec : std_logic_vector(old_width-1 downto 0); |
---|
| 947 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 948 | variable overflow : boolean; |
---|
| 949 | begin |
---|
| 950 | vec := inp; |
---|
| 951 | overflow := true; |
---|
| 952 | result := (others => '0'); |
---|
| 953 | if (new_width >= old_width) then |
---|
| 954 | overflow := false; |
---|
| 955 | end if; |
---|
| 956 | if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then |
---|
| 957 | if all_same(vec(old_width-1 downto new_width-1)) then |
---|
| 958 | overflow := false; |
---|
| 959 | end if; |
---|
| 960 | end if; |
---|
| 961 | if (old_arith = xlSigned and new_arith = xlUnsigned) then |
---|
| 962 | if (old_width > new_width) then |
---|
| 963 | if all_zeros(vec(old_width-1 downto new_width)) then |
---|
| 964 | overflow := false; |
---|
| 965 | end if; |
---|
| 966 | else |
---|
| 967 | if (old_width = new_width) then |
---|
| 968 | if (vec(new_width-1) = '0') then |
---|
| 969 | overflow := false; |
---|
| 970 | end if; |
---|
| 971 | end if; |
---|
| 972 | end if; |
---|
| 973 | end if; |
---|
| 974 | if (old_arith = xlUnsigned and new_arith = xlUnsigned) then |
---|
| 975 | if (old_width > new_width) then |
---|
| 976 | if all_zeros(vec(old_width-1 downto new_width)) then |
---|
| 977 | overflow := false; |
---|
| 978 | end if; |
---|
| 979 | else |
---|
| 980 | if (old_width = new_width) then |
---|
| 981 | overflow := false; |
---|
| 982 | end if; |
---|
| 983 | end if; |
---|
| 984 | end if; |
---|
| 985 | if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then |
---|
| 986 | if all_same(vec(old_width-1 downto new_width-1)) then |
---|
| 987 | overflow := false; |
---|
| 988 | end if; |
---|
| 989 | end if; |
---|
| 990 | if overflow then |
---|
| 991 | if new_arith = xlSigned then |
---|
| 992 | if vec(old_width-1) = '0' then |
---|
| 993 | result := max_signed(new_width); |
---|
| 994 | else |
---|
| 995 | result := min_signed(new_width); |
---|
| 996 | end if; |
---|
| 997 | else |
---|
| 998 | if ((old_arith = xlSigned) and vec(old_width-1) = '1') then |
---|
| 999 | result := (others => '0'); |
---|
| 1000 | else |
---|
| 1001 | result := (others => '1'); |
---|
| 1002 | end if; |
---|
| 1003 | end if; |
---|
| 1004 | else |
---|
| 1005 | if (old_arith = xlSigned) and (new_arith = xlUnsigned) then |
---|
| 1006 | if (vec(old_width-1) = '1') then |
---|
| 1007 | vec := (others => '0'); |
---|
| 1008 | end if; |
---|
| 1009 | end if; |
---|
| 1010 | if new_width <= old_width then |
---|
| 1011 | result := vec(new_width-1 downto 0); |
---|
| 1012 | else |
---|
| 1013 | if new_arith = xlUnsigned then |
---|
| 1014 | result := zero_ext(vec, new_width); |
---|
| 1015 | else |
---|
| 1016 | result := sign_ext(vec, new_width); |
---|
| 1017 | end if; |
---|
| 1018 | end if; |
---|
| 1019 | end if; |
---|
| 1020 | return result; |
---|
| 1021 | end; |
---|
| 1022 | function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt, |
---|
| 1023 | old_arith, new_width, new_bin_pt, new_arith : INTEGER) |
---|
| 1024 | return std_logic_vector |
---|
| 1025 | is |
---|
| 1026 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 1027 | variable result_arith : integer; |
---|
| 1028 | begin |
---|
| 1029 | if (old_arith = xlSigned) and (new_arith = xlUnsigned) then |
---|
| 1030 | result_arith := xlSigned; |
---|
| 1031 | end if; |
---|
| 1032 | result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith); |
---|
| 1033 | return result; |
---|
| 1034 | end; |
---|
| 1035 | function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is |
---|
| 1036 | begin |
---|
| 1037 | return max(a_bin_pt, b_bin_pt); |
---|
| 1038 | end; |
---|
| 1039 | function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER) |
---|
| 1040 | return INTEGER is |
---|
| 1041 | begin |
---|
| 1042 | return max(a_width - a_bin_pt, b_width - b_bin_pt); |
---|
| 1043 | end; |
---|
| 1044 | function pad_LSB(inp : std_logic_vector; new_width: integer) |
---|
| 1045 | return STD_LOGIC_VECTOR |
---|
| 1046 | is |
---|
| 1047 | constant orig_width : integer := inp'length; |
---|
| 1048 | variable vec : std_logic_vector(orig_width-1 downto 0); |
---|
| 1049 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 1050 | variable pos : integer; |
---|
| 1051 | constant pad_pos : integer := new_width - orig_width - 1; |
---|
| 1052 | begin |
---|
| 1053 | vec := inp; |
---|
| 1054 | pos := new_width-1; |
---|
| 1055 | if (new_width >= orig_width) then |
---|
| 1056 | for i in orig_width-1 downto 0 loop |
---|
| 1057 | result(pos) := vec(i); |
---|
| 1058 | pos := pos - 1; |
---|
| 1059 | end loop; |
---|
| 1060 | if pad_pos >= 0 then |
---|
| 1061 | for i in pad_pos downto 0 loop |
---|
| 1062 | result(i) := '0'; |
---|
| 1063 | end loop; |
---|
| 1064 | end if; |
---|
| 1065 | end if; |
---|
| 1066 | return result; |
---|
| 1067 | end; |
---|
| 1068 | function sign_ext(inp : std_logic_vector; new_width : INTEGER) |
---|
| 1069 | return std_logic_vector |
---|
| 1070 | is |
---|
| 1071 | constant old_width : integer := inp'length; |
---|
| 1072 | variable vec : std_logic_vector(old_width-1 downto 0); |
---|
| 1073 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 1074 | begin |
---|
| 1075 | vec := inp; |
---|
| 1076 | if new_width >= old_width then |
---|
| 1077 | result(old_width-1 downto 0) := vec; |
---|
| 1078 | if new_width-1 >= old_width then |
---|
| 1079 | for i in new_width-1 downto old_width loop |
---|
| 1080 | result(i) := vec(old_width-1); |
---|
| 1081 | end loop; |
---|
| 1082 | end if; |
---|
| 1083 | else |
---|
| 1084 | result(new_width-1 downto 0) := vec(new_width-1 downto 0); |
---|
| 1085 | end if; |
---|
| 1086 | return result; |
---|
| 1087 | end; |
---|
| 1088 | function zero_ext(inp : std_logic_vector; new_width : INTEGER) |
---|
| 1089 | return std_logic_vector |
---|
| 1090 | is |
---|
| 1091 | constant old_width : integer := inp'length; |
---|
| 1092 | variable vec : std_logic_vector(old_width-1 downto 0); |
---|
| 1093 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 1094 | begin |
---|
| 1095 | vec := inp; |
---|
| 1096 | if new_width >= old_width then |
---|
| 1097 | result(old_width-1 downto 0) := vec; |
---|
| 1098 | if new_width-1 >= old_width then |
---|
| 1099 | for i in new_width-1 downto old_width loop |
---|
| 1100 | result(i) := '0'; |
---|
| 1101 | end loop; |
---|
| 1102 | end if; |
---|
| 1103 | else |
---|
| 1104 | result(new_width-1 downto 0) := vec(new_width-1 downto 0); |
---|
| 1105 | end if; |
---|
| 1106 | return result; |
---|
| 1107 | end; |
---|
| 1108 | function zero_ext(inp : std_logic; new_width : INTEGER) |
---|
| 1109 | return std_logic_vector |
---|
| 1110 | is |
---|
| 1111 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 1112 | begin |
---|
| 1113 | result(0) := inp; |
---|
| 1114 | for i in new_width-1 downto 1 loop |
---|
| 1115 | result(i) := '0'; |
---|
| 1116 | end loop; |
---|
| 1117 | return result; |
---|
| 1118 | end; |
---|
| 1119 | function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER) |
---|
| 1120 | return std_logic_vector |
---|
| 1121 | is |
---|
| 1122 | constant orig_width : integer := inp'length; |
---|
| 1123 | variable vec : std_logic_vector(orig_width-1 downto 0); |
---|
| 1124 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 1125 | begin |
---|
| 1126 | vec := inp; |
---|
| 1127 | if arith = xlUnsigned then |
---|
| 1128 | result := zero_ext(vec, new_width); |
---|
| 1129 | else |
---|
| 1130 | result := sign_ext(vec, new_width); |
---|
| 1131 | end if; |
---|
| 1132 | return result; |
---|
| 1133 | end; |
---|
| 1134 | function pad_LSB(inp : std_logic_vector; new_width, arith: integer) |
---|
| 1135 | return STD_LOGIC_VECTOR |
---|
| 1136 | is |
---|
| 1137 | constant orig_width : integer := inp'length; |
---|
| 1138 | variable vec : std_logic_vector(orig_width-1 downto 0); |
---|
| 1139 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 1140 | variable pos : integer; |
---|
| 1141 | begin |
---|
| 1142 | vec := inp; |
---|
| 1143 | pos := new_width-1; |
---|
| 1144 | if (arith = xlUnsigned) then |
---|
| 1145 | result(pos) := '0'; |
---|
| 1146 | pos := pos - 1; |
---|
| 1147 | else |
---|
| 1148 | result(pos) := vec(orig_width-1); |
---|
| 1149 | pos := pos - 1; |
---|
| 1150 | end if; |
---|
| 1151 | if (new_width >= orig_width) then |
---|
| 1152 | for i in orig_width-1 downto 0 loop |
---|
| 1153 | result(pos) := vec(i); |
---|
| 1154 | pos := pos - 1; |
---|
| 1155 | end loop; |
---|
| 1156 | if pos >= 0 then |
---|
| 1157 | for i in pos downto 0 loop |
---|
| 1158 | result(i) := '0'; |
---|
| 1159 | end loop; |
---|
| 1160 | end if; |
---|
| 1161 | end if; |
---|
| 1162 | return result; |
---|
| 1163 | end; |
---|
| 1164 | function align_input(inp : std_logic_vector; old_width, delta, new_arith, |
---|
| 1165 | new_width: INTEGER) |
---|
| 1166 | return std_logic_vector |
---|
| 1167 | is |
---|
| 1168 | variable vec : std_logic_vector(old_width-1 downto 0); |
---|
| 1169 | variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0); |
---|
| 1170 | variable result : std_logic_vector(new_width-1 downto 0); |
---|
| 1171 | begin |
---|
| 1172 | vec := inp; |
---|
| 1173 | if delta > 0 then |
---|
| 1174 | padded_inp := pad_LSB(vec, old_width+delta); |
---|
| 1175 | result := extend_MSB(padded_inp, new_width, new_arith); |
---|
| 1176 | else |
---|
| 1177 | result := extend_MSB(vec, new_width, new_arith); |
---|
| 1178 | end if; |
---|
| 1179 | return result; |
---|
| 1180 | end; |
---|
| 1181 | function max(L, R: INTEGER) return INTEGER is |
---|
| 1182 | begin |
---|
| 1183 | if L > R then |
---|
| 1184 | return L; |
---|
| 1185 | else |
---|
| 1186 | return R; |
---|
| 1187 | end if; |
---|
| 1188 | end; |
---|
| 1189 | function min(L, R: INTEGER) return INTEGER is |
---|
| 1190 | begin |
---|
| 1191 | if L < R then |
---|
| 1192 | return L; |
---|
| 1193 | else |
---|
| 1194 | return R; |
---|
| 1195 | end if; |
---|
| 1196 | end; |
---|
| 1197 | function "="(left,right: STRING) return boolean is |
---|
| 1198 | begin |
---|
| 1199 | if (left'length /= right'length) then |
---|
| 1200 | return false; |
---|
| 1201 | else |
---|
| 1202 | test : for i in 1 to left'length loop |
---|
| 1203 | if left(i) /= right(i) then |
---|
| 1204 | return false; |
---|
| 1205 | end if; |
---|
| 1206 | end loop test; |
---|
| 1207 | return true; |
---|
| 1208 | end if; |
---|
| 1209 | end; |
---|
| 1210 | -- synopsys translate_off |
---|
| 1211 | function is_binary_string_invalid (inp : string) |
---|
| 1212 | return boolean |
---|
| 1213 | is |
---|
| 1214 | variable vec : string(1 to inp'length); |
---|
| 1215 | variable result : boolean; |
---|
| 1216 | begin |
---|
| 1217 | vec := inp; |
---|
| 1218 | result := false; |
---|
| 1219 | for i in 1 to vec'length loop |
---|
| 1220 | if ( vec(i) = 'X' ) then |
---|
| 1221 | result := true; |
---|
| 1222 | end if; |
---|
| 1223 | end loop; |
---|
| 1224 | return result; |
---|
| 1225 | end; |
---|
| 1226 | function is_binary_string_undefined (inp : string) |
---|
| 1227 | return boolean |
---|
| 1228 | is |
---|
| 1229 | variable vec : string(1 to inp'length); |
---|
| 1230 | variable result : boolean; |
---|
| 1231 | begin |
---|
| 1232 | vec := inp; |
---|
| 1233 | result := false; |
---|
| 1234 | for i in 1 to vec'length loop |
---|
| 1235 | if ( vec(i) = 'U' ) then |
---|
| 1236 | result := true; |
---|
| 1237 | end if; |
---|
| 1238 | end loop; |
---|
| 1239 | return result; |
---|
| 1240 | end; |
---|
| 1241 | function is_XorU(inp : std_logic_vector) |
---|
| 1242 | return boolean |
---|
| 1243 | is |
---|
| 1244 | constant width : integer := inp'length; |
---|
| 1245 | variable vec : std_logic_vector(width-1 downto 0); |
---|
| 1246 | variable result : boolean; |
---|
| 1247 | begin |
---|
| 1248 | vec := inp; |
---|
| 1249 | result := false; |
---|
| 1250 | for i in 0 to width-1 loop |
---|
| 1251 | if (vec(i) = 'U') or (vec(i) = 'X') then |
---|
| 1252 | result := true; |
---|
| 1253 | end if; |
---|
| 1254 | end loop; |
---|
| 1255 | return result; |
---|
| 1256 | end; |
---|
| 1257 | function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer) |
---|
| 1258 | return real |
---|
| 1259 | is |
---|
| 1260 | variable vec : std_logic_vector(inp'length-1 downto 0); |
---|
| 1261 | variable result, shift_val, undefined_real : real; |
---|
| 1262 | variable neg_num : boolean; |
---|
| 1263 | begin |
---|
| 1264 | vec := inp; |
---|
| 1265 | result := 0.0; |
---|
| 1266 | neg_num := false; |
---|
| 1267 | if vec(inp'length-1) = '1' then |
---|
| 1268 | neg_num := true; |
---|
| 1269 | end if; |
---|
| 1270 | for i in 0 to inp'length-1 loop |
---|
| 1271 | if vec(i) = 'U' or vec(i) = 'X' then |
---|
| 1272 | return undefined_real; |
---|
| 1273 | end if; |
---|
| 1274 | if arith = xlSigned then |
---|
| 1275 | if neg_num then |
---|
| 1276 | if vec(i) = '0' then |
---|
| 1277 | result := result + 2.0**i; |
---|
| 1278 | end if; |
---|
| 1279 | else |
---|
| 1280 | if vec(i) = '1' then |
---|
| 1281 | result := result + 2.0**i; |
---|
| 1282 | end if; |
---|
| 1283 | end if; |
---|
| 1284 | else |
---|
| 1285 | if vec(i) = '1' then |
---|
| 1286 | result := result + 2.0**i; |
---|
| 1287 | end if; |
---|
| 1288 | end if; |
---|
| 1289 | end loop; |
---|
| 1290 | if arith = xlSigned then |
---|
| 1291 | if neg_num then |
---|
| 1292 | result := result + 1.0; |
---|
| 1293 | result := result * (-1.0); |
---|
| 1294 | end if; |
---|
| 1295 | end if; |
---|
| 1296 | shift_val := 2.0**(-1*bin_pt); |
---|
| 1297 | result := result * shift_val; |
---|
| 1298 | return result; |
---|
| 1299 | end; |
---|
| 1300 | function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer) |
---|
| 1301 | return real |
---|
| 1302 | is |
---|
| 1303 | variable result : real := 0.0; |
---|
| 1304 | begin |
---|
| 1305 | if inp = '1' then |
---|
| 1306 | result := 1.0; |
---|
| 1307 | end if; |
---|
| 1308 | if arith = xlSigned then |
---|
| 1309 | assert false |
---|
| 1310 | report "It doesn't make sense to convert a 1 bit number to a signed real."; |
---|
| 1311 | end if; |
---|
| 1312 | return result; |
---|
| 1313 | end; |
---|
| 1314 | -- synopsys translate_on |
---|
| 1315 | function integer_to_std_logic_vector (inp : integer; width, arith : integer) |
---|
| 1316 | return std_logic_vector |
---|
| 1317 | is |
---|
| 1318 | variable result : std_logic_vector(width-1 downto 0); |
---|
| 1319 | variable unsigned_val : unsigned(width-1 downto 0); |
---|
| 1320 | variable signed_val : signed(width-1 downto 0); |
---|
| 1321 | begin |
---|
| 1322 | if (arith = xlSigned) then |
---|
| 1323 | signed_val := to_signed(inp, width); |
---|
| 1324 | result := signed_to_std_logic_vector(signed_val); |
---|
| 1325 | else |
---|
| 1326 | unsigned_val := to_unsigned(inp, width); |
---|
| 1327 | result := unsigned_to_std_logic_vector(unsigned_val); |
---|
| 1328 | end if; |
---|
| 1329 | return result; |
---|
| 1330 | end; |
---|
| 1331 | function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer) |
---|
| 1332 | return integer |
---|
| 1333 | is |
---|
| 1334 | constant width : integer := inp'length; |
---|
| 1335 | variable unsigned_val : unsigned(width-1 downto 0); |
---|
| 1336 | variable signed_val : signed(width-1 downto 0); |
---|
| 1337 | variable result : integer; |
---|
| 1338 | begin |
---|
| 1339 | if (arith = xlSigned) then |
---|
| 1340 | signed_val := std_logic_vector_to_signed(inp); |
---|
| 1341 | result := to_integer(signed_val); |
---|
| 1342 | else |
---|
| 1343 | unsigned_val := std_logic_vector_to_unsigned(inp); |
---|
| 1344 | result := to_integer(unsigned_val); |
---|
| 1345 | end if; |
---|
| 1346 | return result; |
---|
| 1347 | end; |
---|
| 1348 | function std_logic_to_integer(constant inp : std_logic := '0') |
---|
| 1349 | return integer |
---|
| 1350 | is |
---|
| 1351 | begin |
---|
| 1352 | if inp = '1' then |
---|
| 1353 | return 1; |
---|
| 1354 | else |
---|
| 1355 | return 0; |
---|
| 1356 | end if; |
---|
| 1357 | end; |
---|
| 1358 | function makeZeroBinStr (width : integer) return STRING is |
---|
| 1359 | variable result : string(1 to width+3); |
---|
| 1360 | begin |
---|
| 1361 | result(1) := '0'; |
---|
| 1362 | result(2) := 'b'; |
---|
| 1363 | for i in 3 to width+2 loop |
---|
| 1364 | result(i) := '0'; |
---|
| 1365 | end loop; |
---|
| 1366 | result(width+3) := '.'; |
---|
| 1367 | return result; |
---|
| 1368 | end; |
---|
| 1369 | -- synopsys translate_off |
---|
| 1370 | function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer) |
---|
| 1371 | return std_logic_vector |
---|
| 1372 | is |
---|
| 1373 | variable result : std_logic_vector(width-1 downto 0); |
---|
| 1374 | begin |
---|
| 1375 | result := (others => '0'); |
---|
| 1376 | return result; |
---|
| 1377 | end; |
---|
| 1378 | function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer) |
---|
| 1379 | return std_logic_vector |
---|
| 1380 | is |
---|
| 1381 | variable real_val : real; |
---|
| 1382 | variable int_val : integer; |
---|
| 1383 | variable result : std_logic_vector(width-1 downto 0) := (others => '0'); |
---|
| 1384 | variable unsigned_val : unsigned(width-1 downto 0) := (others => '0'); |
---|
| 1385 | variable signed_val : signed(width-1 downto 0) := (others => '0'); |
---|
| 1386 | begin |
---|
| 1387 | real_val := inp; |
---|
| 1388 | int_val := integer(real_val * 2.0**(bin_pt)); |
---|
| 1389 | if (arith = xlSigned) then |
---|
| 1390 | signed_val := to_signed(int_val, width); |
---|
| 1391 | result := signed_to_std_logic_vector(signed_val); |
---|
| 1392 | else |
---|
| 1393 | unsigned_val := to_unsigned(int_val, width); |
---|
| 1394 | result := unsigned_to_std_logic_vector(unsigned_val); |
---|
| 1395 | end if; |
---|
| 1396 | return result; |
---|
| 1397 | end; |
---|
| 1398 | -- synopsys translate_on |
---|
| 1399 | function valid_bin_string (inp : string) |
---|
| 1400 | return boolean |
---|
| 1401 | is |
---|
| 1402 | variable vec : string(1 to inp'length); |
---|
| 1403 | begin |
---|
| 1404 | vec := inp; |
---|
| 1405 | if (vec(1) = '0' and vec(2) = 'b') then |
---|
| 1406 | return true; |
---|
| 1407 | else |
---|
| 1408 | return false; |
---|
| 1409 | end if; |
---|
| 1410 | end; |
---|
| 1411 | function hex_string_to_std_logic_vector(inp: string; width : integer) |
---|
| 1412 | return std_logic_vector is |
---|
| 1413 | constant strlen : integer := inp'LENGTH; |
---|
| 1414 | variable result : std_logic_vector(width-1 downto 0); |
---|
| 1415 | variable bitval : std_logic_vector((strlen*4)-1 downto 0); |
---|
| 1416 | variable posn : integer; |
---|
| 1417 | variable ch : character; |
---|
| 1418 | variable vec : string(1 to strlen); |
---|
| 1419 | begin |
---|
| 1420 | vec := inp; |
---|
| 1421 | result := (others => '0'); |
---|
| 1422 | posn := (strlen*4)-1; |
---|
| 1423 | for i in 1 to strlen loop |
---|
| 1424 | ch := vec(i); |
---|
| 1425 | case ch is |
---|
| 1426 | when '0' => bitval(posn downto posn-3) := "0000"; |
---|
| 1427 | when '1' => bitval(posn downto posn-3) := "0001"; |
---|
| 1428 | when '2' => bitval(posn downto posn-3) := "0010"; |
---|
| 1429 | when '3' => bitval(posn downto posn-3) := "0011"; |
---|
| 1430 | when '4' => bitval(posn downto posn-3) := "0100"; |
---|
| 1431 | when '5' => bitval(posn downto posn-3) := "0101"; |
---|
| 1432 | when '6' => bitval(posn downto posn-3) := "0110"; |
---|
| 1433 | when '7' => bitval(posn downto posn-3) := "0111"; |
---|
| 1434 | when '8' => bitval(posn downto posn-3) := "1000"; |
---|
| 1435 | when '9' => bitval(posn downto posn-3) := "1001"; |
---|
| 1436 | when 'A' | 'a' => bitval(posn downto posn-3) := "1010"; |
---|
| 1437 | when 'B' | 'b' => bitval(posn downto posn-3) := "1011"; |
---|
| 1438 | when 'C' | 'c' => bitval(posn downto posn-3) := "1100"; |
---|
| 1439 | when 'D' | 'd' => bitval(posn downto posn-3) := "1101"; |
---|
| 1440 | when 'E' | 'e' => bitval(posn downto posn-3) := "1110"; |
---|
| 1441 | when 'F' | 'f' => bitval(posn downto posn-3) := "1111"; |
---|
| 1442 | when others => bitval(posn downto posn-3) := "XXXX"; |
---|
| 1443 | -- synopsys translate_off |
---|
| 1444 | ASSERT false |
---|
| 1445 | REPORT "Invalid hex value" SEVERITY ERROR; |
---|
| 1446 | -- synopsys translate_on |
---|
| 1447 | end case; |
---|
| 1448 | posn := posn - 4; |
---|
| 1449 | end loop; |
---|
| 1450 | if (width <= strlen*4) then |
---|
| 1451 | result := bitval(width-1 downto 0); |
---|
| 1452 | else |
---|
| 1453 | result((strlen*4)-1 downto 0) := bitval; |
---|
| 1454 | end if; |
---|
| 1455 | return result; |
---|
| 1456 | end; |
---|
| 1457 | function bin_string_to_std_logic_vector (inp : string) |
---|
| 1458 | return std_logic_vector |
---|
| 1459 | is |
---|
| 1460 | variable pos : integer; |
---|
| 1461 | variable vec : string(1 to inp'length); |
---|
| 1462 | variable result : std_logic_vector(inp'length-1 downto 0); |
---|
| 1463 | begin |
---|
| 1464 | vec := inp; |
---|
| 1465 | pos := inp'length-1; |
---|
| 1466 | result := (others => '0'); |
---|
| 1467 | for i in 1 to vec'length loop |
---|
| 1468 | -- synopsys translate_off |
---|
| 1469 | if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then |
---|
| 1470 | assert false |
---|
| 1471 | report "Input string is larger than output std_logic_vector. Truncating output."; |
---|
| 1472 | return result; |
---|
| 1473 | end if; |
---|
| 1474 | -- synopsys translate_on |
---|
| 1475 | if vec(i) = '0' then |
---|
| 1476 | result(pos) := '0'; |
---|
| 1477 | pos := pos - 1; |
---|
| 1478 | end if; |
---|
| 1479 | if vec(i) = '1' then |
---|
| 1480 | result(pos) := '1'; |
---|
| 1481 | pos := pos - 1; |
---|
| 1482 | end if; |
---|
| 1483 | -- synopsys translate_off |
---|
| 1484 | if (vec(i) = 'X' or vec(i) = 'U') then |
---|
| 1485 | result(pos) := 'U'; |
---|
| 1486 | pos := pos - 1; |
---|
| 1487 | end if; |
---|
| 1488 | -- synopsys translate_on |
---|
| 1489 | end loop; |
---|
| 1490 | return result; |
---|
| 1491 | end; |
---|
| 1492 | function bin_string_element_to_std_logic_vector (inp : string; width, index : integer) |
---|
| 1493 | return std_logic_vector |
---|
| 1494 | is |
---|
| 1495 | constant str_width : integer := width + 4; |
---|
| 1496 | constant inp_len : integer := inp'length; |
---|
| 1497 | constant num_elements : integer := (inp_len + 1)/str_width; |
---|
| 1498 | constant reverse_index : integer := (num_elements-1) - index; |
---|
| 1499 | variable left_pos : integer; |
---|
| 1500 | variable right_pos : integer; |
---|
| 1501 | variable vec : string(1 to inp'length); |
---|
| 1502 | variable result : std_logic_vector(width-1 downto 0); |
---|
| 1503 | begin |
---|
| 1504 | vec := inp; |
---|
| 1505 | result := (others => '0'); |
---|
| 1506 | if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then |
---|
| 1507 | left_pos := 1; |
---|
| 1508 | right_pos := width + 3; |
---|
| 1509 | result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); |
---|
| 1510 | end if; |
---|
| 1511 | if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then |
---|
| 1512 | left_pos := (reverse_index * str_width) + 1; |
---|
| 1513 | right_pos := left_pos + width + 2; |
---|
| 1514 | result := bin_string_to_std_logic_vector(vec(left_pos to right_pos)); |
---|
| 1515 | end if; |
---|
| 1516 | return result; |
---|
| 1517 | end; |
---|
| 1518 | -- synopsys translate_off |
---|
| 1519 | function std_logic_vector_to_bin_string(inp : std_logic_vector) |
---|
| 1520 | return string |
---|
| 1521 | is |
---|
| 1522 | variable vec : std_logic_vector(1 to inp'length); |
---|
| 1523 | variable result : string(vec'range); |
---|
| 1524 | begin |
---|
| 1525 | vec := inp; |
---|
| 1526 | for i in vec'range loop |
---|
| 1527 | result(i) := to_char(vec(i)); |
---|
| 1528 | end loop; |
---|
| 1529 | return result; |
---|
| 1530 | end; |
---|
| 1531 | function std_logic_to_bin_string(inp : std_logic) |
---|
| 1532 | return string |
---|
| 1533 | is |
---|
| 1534 | variable result : string(1 to 3); |
---|
| 1535 | begin |
---|
| 1536 | result(1) := '0'; |
---|
| 1537 | result(2) := 'b'; |
---|
| 1538 | result(3) := to_char(inp); |
---|
| 1539 | return result; |
---|
| 1540 | end; |
---|
| 1541 | function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer) |
---|
| 1542 | return string |
---|
| 1543 | is |
---|
| 1544 | variable width : integer := inp'length; |
---|
| 1545 | variable vec : std_logic_vector(width-1 downto 0); |
---|
| 1546 | variable str_pos : integer; |
---|
| 1547 | variable result : string(1 to width+3); |
---|
| 1548 | begin |
---|
| 1549 | vec := inp; |
---|
| 1550 | str_pos := 1; |
---|
| 1551 | result(str_pos) := '0'; |
---|
| 1552 | str_pos := 2; |
---|
| 1553 | result(str_pos) := 'b'; |
---|
| 1554 | str_pos := 3; |
---|
| 1555 | for i in width-1 downto 0 loop |
---|
| 1556 | if (((width+3) - bin_pt) = str_pos) then |
---|
| 1557 | result(str_pos) := '.'; |
---|
| 1558 | str_pos := str_pos + 1; |
---|
| 1559 | end if; |
---|
| 1560 | result(str_pos) := to_char(vec(i)); |
---|
| 1561 | str_pos := str_pos + 1; |
---|
| 1562 | end loop; |
---|
| 1563 | if (bin_pt = 0) then |
---|
| 1564 | result(str_pos) := '.'; |
---|
| 1565 | end if; |
---|
| 1566 | return result; |
---|
| 1567 | end; |
---|
| 1568 | function real_to_bin_string(inp : real; width, bin_pt, arith : integer) |
---|
| 1569 | return string |
---|
| 1570 | is |
---|
| 1571 | variable result : string(1 to width); |
---|
| 1572 | variable vec : std_logic_vector(width-1 downto 0); |
---|
| 1573 | begin |
---|
| 1574 | vec := real_to_std_logic_vector(inp, width, bin_pt, arith); |
---|
| 1575 | result := std_logic_vector_to_bin_string(vec); |
---|
| 1576 | return result; |
---|
| 1577 | end; |
---|
| 1578 | function real_to_string (inp : real) return string |
---|
| 1579 | is |
---|
| 1580 | variable result : string(1 to display_precision) := (others => ' '); |
---|
| 1581 | begin |
---|
| 1582 | result(real'image(inp)'range) := real'image(inp); |
---|
| 1583 | return result; |
---|
| 1584 | end; |
---|
| 1585 | -- synopsys translate_on |
---|
| 1586 | end conv_pkg; |
---|
| 1587 | library IEEE; |
---|
| 1588 | use IEEE.std_logic_1164.all; |
---|
| 1589 | package clock_pkg is |
---|
| 1590 | -- synopsys translate_off |
---|
| 1591 | signal int_clk : std_logic; |
---|
| 1592 | -- synopsys translate_on |
---|
| 1593 | end clock_pkg; |
---|
| 1594 | |
---|
| 1595 | ------------------------------------------------------------------- |
---|
| 1596 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 1597 | -- |
---|
| 1598 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 1599 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 1600 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 1601 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 1602 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 1603 | -- this text/file solely for design, simulation, implementation and |
---|
| 1604 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 1605 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 1606 | -- and immediately terminates your license unless covered by a separate |
---|
| 1607 | -- agreement. |
---|
| 1608 | -- |
---|
| 1609 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 1610 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 1611 | -- providing this design, code, or information as one possible |
---|
| 1612 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 1613 | -- making no representation that this implementation is free from any |
---|
| 1614 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 1615 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 1616 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 1617 | -- implementation, including but not limited to warranties of |
---|
| 1618 | -- merchantability or fitness for a particular purpose. |
---|
| 1619 | -- |
---|
| 1620 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 1621 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 1622 | -- |
---|
| 1623 | -- Any modifications that are made to the source code are done at the user's |
---|
| 1624 | -- sole risk and will be unsupported. |
---|
| 1625 | -- |
---|
| 1626 | -- This copyright and support notice must be retained as part of this |
---|
| 1627 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 1628 | -- reserved. |
---|
| 1629 | ------------------------------------------------------------------- |
---|
| 1630 | -- synopsys translate_off |
---|
| 1631 | library unisim; |
---|
| 1632 | use unisim.vcomponents.all; |
---|
| 1633 | -- synopsys translate_on |
---|
| 1634 | library IEEE; |
---|
| 1635 | use IEEE.std_logic_1164.all; |
---|
| 1636 | use work.conv_pkg.all; |
---|
| 1637 | entity srl17e is |
---|
| 1638 | generic (width : integer:=16; |
---|
| 1639 | latency : integer :=8); |
---|
| 1640 | port (clk : in std_logic; |
---|
| 1641 | ce : in std_logic; |
---|
| 1642 | d : in std_logic_vector(width-1 downto 0); |
---|
| 1643 | q : out std_logic_vector(width-1 downto 0)); |
---|
| 1644 | end srl17e; |
---|
| 1645 | architecture structural of srl17e is |
---|
| 1646 | component SRL16E |
---|
| 1647 | port (D : in STD_ULOGIC; |
---|
| 1648 | CE : in STD_ULOGIC; |
---|
| 1649 | CLK : in STD_ULOGIC; |
---|
| 1650 | A0 : in STD_ULOGIC; |
---|
| 1651 | A1 : in STD_ULOGIC; |
---|
| 1652 | A2 : in STD_ULOGIC; |
---|
| 1653 | A3 : in STD_ULOGIC; |
---|
| 1654 | Q : out STD_ULOGIC); |
---|
| 1655 | end component; |
---|
| 1656 | attribute syn_black_box of SRL16E : component is true; |
---|
| 1657 | attribute fpga_dont_touch of SRL16E : component is "true"; |
---|
| 1658 | component FDE |
---|
| 1659 | port( |
---|
| 1660 | Q : out STD_ULOGIC; |
---|
| 1661 | D : in STD_ULOGIC; |
---|
| 1662 | C : in STD_ULOGIC; |
---|
| 1663 | CE : in STD_ULOGIC); |
---|
| 1664 | end component; |
---|
| 1665 | attribute syn_black_box of FDE : component is true; |
---|
| 1666 | attribute fpga_dont_touch of FDE : component is "true"; |
---|
| 1667 | constant a : std_logic_vector(4 downto 0) := |
---|
| 1668 | integer_to_std_logic_vector(latency-2,5,xlSigned); |
---|
| 1669 | signal d_delayed : std_logic_vector(width-1 downto 0); |
---|
| 1670 | signal srl16_out : std_logic_vector(width-1 downto 0); |
---|
| 1671 | begin |
---|
| 1672 | d_delayed <= d after 200 ps; |
---|
| 1673 | reg_array : for i in 0 to width-1 generate |
---|
| 1674 | srl16_used: if latency > 1 generate |
---|
| 1675 | u1 : srl16e port map(clk => clk, |
---|
| 1676 | d => d_delayed(i), |
---|
| 1677 | q => srl16_out(i), |
---|
| 1678 | ce => ce, |
---|
| 1679 | a0 => a(0), |
---|
| 1680 | a1 => a(1), |
---|
| 1681 | a2 => a(2), |
---|
| 1682 | a3 => a(3)); |
---|
| 1683 | end generate; |
---|
| 1684 | srl16_not_used: if latency <= 1 generate |
---|
| 1685 | srl16_out(i) <= d_delayed(i); |
---|
| 1686 | end generate; |
---|
| 1687 | fde_used: if latency /= 0 generate |
---|
| 1688 | u2 : fde port map(c => clk, |
---|
| 1689 | d => srl16_out(i), |
---|
| 1690 | q => q(i), |
---|
| 1691 | ce => ce); |
---|
| 1692 | end generate; |
---|
| 1693 | fde_not_used: if latency = 0 generate |
---|
| 1694 | q(i) <= srl16_out(i); |
---|
| 1695 | end generate; |
---|
| 1696 | end generate; |
---|
| 1697 | end structural; |
---|
| 1698 | library IEEE; |
---|
| 1699 | use IEEE.std_logic_1164.all; |
---|
| 1700 | use work.conv_pkg.all; |
---|
| 1701 | entity synth_reg is |
---|
| 1702 | generic (width : integer := 8; |
---|
| 1703 | latency : integer := 1); |
---|
| 1704 | port (i : in std_logic_vector(width-1 downto 0); |
---|
| 1705 | ce : in std_logic; |
---|
| 1706 | clr : in std_logic; |
---|
| 1707 | clk : in std_logic; |
---|
| 1708 | o : out std_logic_vector(width-1 downto 0)); |
---|
| 1709 | end synth_reg; |
---|
| 1710 | architecture structural of synth_reg is |
---|
| 1711 | component srl17e |
---|
| 1712 | generic (width : integer:=16; |
---|
| 1713 | latency : integer :=8); |
---|
| 1714 | port (clk : in std_logic; |
---|
| 1715 | ce : in std_logic; |
---|
| 1716 | d : in std_logic_vector(width-1 downto 0); |
---|
| 1717 | q : out std_logic_vector(width-1 downto 0)); |
---|
| 1718 | end component; |
---|
| 1719 | function calc_num_srl17es (latency : integer) |
---|
| 1720 | return integer |
---|
| 1721 | is |
---|
| 1722 | variable remaining_latency : integer; |
---|
| 1723 | variable result : integer; |
---|
| 1724 | begin |
---|
| 1725 | result := latency / 17; |
---|
| 1726 | remaining_latency := latency - (result * 17); |
---|
| 1727 | if (remaining_latency /= 0) then |
---|
| 1728 | result := result + 1; |
---|
| 1729 | end if; |
---|
| 1730 | return result; |
---|
| 1731 | end; |
---|
| 1732 | constant complete_num_srl17es : integer := latency / 17; |
---|
| 1733 | constant num_srl17es : integer := calc_num_srl17es(latency); |
---|
| 1734 | constant remaining_latency : integer := latency - (complete_num_srl17es * 17); |
---|
| 1735 | type register_array is array (num_srl17es downto 0) of |
---|
| 1736 | std_logic_vector(width-1 downto 0); |
---|
| 1737 | signal z : register_array; |
---|
| 1738 | begin |
---|
| 1739 | z(0) <= i; |
---|
| 1740 | complete_ones : if complete_num_srl17es > 0 generate |
---|
| 1741 | srl17e_array: for i in 0 to complete_num_srl17es-1 generate |
---|
| 1742 | delay_comp : srl17e |
---|
| 1743 | generic map (width => width, |
---|
| 1744 | latency => 17) |
---|
| 1745 | port map (clk => clk, |
---|
| 1746 | ce => ce, |
---|
| 1747 | d => z(i), |
---|
| 1748 | q => z(i+1)); |
---|
| 1749 | end generate; |
---|
| 1750 | end generate; |
---|
| 1751 | partial_one : if remaining_latency > 0 generate |
---|
| 1752 | last_srl17e : srl17e |
---|
| 1753 | generic map (width => width, |
---|
| 1754 | latency => remaining_latency) |
---|
| 1755 | port map (clk => clk, |
---|
| 1756 | ce => ce, |
---|
| 1757 | d => z(num_srl17es-1), |
---|
| 1758 | q => z(num_srl17es)); |
---|
| 1759 | end generate; |
---|
| 1760 | o <= z(num_srl17es); |
---|
| 1761 | end structural; |
---|
| 1762 | library IEEE; |
---|
| 1763 | use IEEE.std_logic_1164.all; |
---|
| 1764 | use work.conv_pkg.all; |
---|
| 1765 | entity synth_reg_reg is |
---|
| 1766 | generic (width : integer := 8; |
---|
| 1767 | latency : integer := 1); |
---|
| 1768 | port (i : in std_logic_vector(width-1 downto 0); |
---|
| 1769 | ce : in std_logic; |
---|
| 1770 | clr : in std_logic; |
---|
| 1771 | clk : in std_logic; |
---|
| 1772 | o : out std_logic_vector(width-1 downto 0)); |
---|
| 1773 | end synth_reg_reg; |
---|
| 1774 | architecture behav of synth_reg_reg is |
---|
| 1775 | type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0); |
---|
| 1776 | signal reg_bank : reg_array_type := (others => (others => '0')); |
---|
| 1777 | signal reg_bank_in : reg_array_type := (others => (others => '0')); |
---|
| 1778 | attribute syn_allow_retiming : boolean; |
---|
| 1779 | attribute syn_srlstyle : string; |
---|
| 1780 | attribute syn_allow_retiming of reg_bank : signal is true; |
---|
| 1781 | attribute syn_allow_retiming of reg_bank_in : signal is true; |
---|
| 1782 | attribute syn_srlstyle of reg_bank : signal is "registers"; |
---|
| 1783 | attribute syn_srlstyle of reg_bank_in : signal is "registers"; |
---|
| 1784 | begin |
---|
| 1785 | latency_eq_0: if latency = 0 generate |
---|
| 1786 | o <= i; |
---|
| 1787 | end generate latency_eq_0; |
---|
| 1788 | latency_gt_0: if latency >= 1 generate |
---|
| 1789 | o <= reg_bank(latency-1); |
---|
| 1790 | reg_bank_in(0) <= i; |
---|
| 1791 | loop_gen: for idx in latency-2 downto 0 generate |
---|
| 1792 | reg_bank_in(idx+1) <= reg_bank(idx); |
---|
| 1793 | end generate loop_gen; |
---|
| 1794 | sync_loop: for sync_idx in latency-1 downto 0 generate |
---|
| 1795 | sync_proc: process (clk) |
---|
| 1796 | begin |
---|
| 1797 | if clk'event and clk = '1' then |
---|
| 1798 | if ce = '1' then |
---|
| 1799 | reg_bank(sync_idx) <= reg_bank_in(sync_idx); |
---|
| 1800 | end if; |
---|
| 1801 | end if; |
---|
| 1802 | end process sync_proc; |
---|
| 1803 | end generate sync_loop; |
---|
| 1804 | end generate latency_gt_0; |
---|
| 1805 | end behav; |
---|
| 1806 | |
---|
| 1807 | ------------------------------------------------------------------- |
---|
| 1808 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 1809 | -- |
---|
| 1810 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 1811 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 1812 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 1813 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 1814 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 1815 | -- this text/file solely for design, simulation, implementation and |
---|
| 1816 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 1817 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 1818 | -- and immediately terminates your license unless covered by a separate |
---|
| 1819 | -- agreement. |
---|
| 1820 | -- |
---|
| 1821 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 1822 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 1823 | -- providing this design, code, or information as one possible |
---|
| 1824 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 1825 | -- making no representation that this implementation is free from any |
---|
| 1826 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 1827 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 1828 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 1829 | -- implementation, including but not limited to warranties of |
---|
| 1830 | -- merchantability or fitness for a particular purpose. |
---|
| 1831 | -- |
---|
| 1832 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 1833 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 1834 | -- |
---|
| 1835 | -- Any modifications that are made to the source code are done at the user's |
---|
| 1836 | -- sole risk and will be unsupported. |
---|
| 1837 | -- |
---|
| 1838 | -- This copyright and support notice must be retained as part of this |
---|
| 1839 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 1840 | -- reserved. |
---|
| 1841 | ------------------------------------------------------------------- |
---|
| 1842 | -- synopsys translate_off |
---|
| 1843 | library unisim; |
---|
| 1844 | use unisim.vcomponents.all; |
---|
| 1845 | -- synopsys translate_on |
---|
| 1846 | library IEEE; |
---|
| 1847 | use IEEE.std_logic_1164.all; |
---|
| 1848 | use work.conv_pkg.all; |
---|
| 1849 | entity single_reg_w_init is |
---|
| 1850 | generic ( |
---|
| 1851 | width: integer := 8; |
---|
| 1852 | init_index: integer := 0; |
---|
| 1853 | init_value: bit_vector := b"0000" |
---|
| 1854 | ); |
---|
| 1855 | port ( |
---|
| 1856 | i: in std_logic_vector(width - 1 downto 0); |
---|
| 1857 | ce: in std_logic; |
---|
| 1858 | clr: in std_logic; |
---|
| 1859 | clk: in std_logic; |
---|
| 1860 | o: out std_logic_vector(width - 1 downto 0) |
---|
| 1861 | ); |
---|
| 1862 | end single_reg_w_init; |
---|
| 1863 | architecture structural of single_reg_w_init is |
---|
| 1864 | function build_init_const(width: integer; |
---|
| 1865 | init_index: integer; |
---|
| 1866 | init_value: bit_vector) |
---|
| 1867 | return std_logic_vector |
---|
| 1868 | is |
---|
| 1869 | variable result: std_logic_vector(width - 1 downto 0); |
---|
| 1870 | begin |
---|
| 1871 | if init_index = 0 then |
---|
| 1872 | result := (others => '0'); |
---|
| 1873 | elsif init_index = 1 then |
---|
| 1874 | result := (others => '0'); |
---|
| 1875 | result(0) := '1'; |
---|
| 1876 | else |
---|
| 1877 | result := to_stdlogicvector(init_value); |
---|
| 1878 | end if; |
---|
| 1879 | return result; |
---|
| 1880 | end; |
---|
| 1881 | component fdre |
---|
| 1882 | port ( |
---|
| 1883 | q: out std_ulogic; |
---|
| 1884 | d: in std_ulogic; |
---|
| 1885 | c: in std_ulogic; |
---|
| 1886 | ce: in std_ulogic; |
---|
| 1887 | r: in std_ulogic |
---|
| 1888 | ); |
---|
| 1889 | end component; |
---|
| 1890 | attribute syn_black_box of fdre: component is true; |
---|
| 1891 | attribute fpga_dont_touch of fdre: component is "true"; |
---|
| 1892 | component fdse |
---|
| 1893 | port ( |
---|
| 1894 | q: out std_ulogic; |
---|
| 1895 | d: in std_ulogic; |
---|
| 1896 | c: in std_ulogic; |
---|
| 1897 | ce: in std_ulogic; |
---|
| 1898 | s: in std_ulogic |
---|
| 1899 | ); |
---|
| 1900 | end component; |
---|
| 1901 | attribute syn_black_box of fdse: component is true; |
---|
| 1902 | attribute fpga_dont_touch of fdse: component is "true"; |
---|
| 1903 | constant init_const: std_logic_vector(width - 1 downto 0) |
---|
| 1904 | := build_init_const(width, init_index, init_value); |
---|
| 1905 | begin |
---|
| 1906 | fd_prim_array: for index in 0 to width - 1 generate |
---|
| 1907 | bit_is_0: if (init_const(index) = '0') generate |
---|
| 1908 | fdre_comp: fdre |
---|
| 1909 | port map ( |
---|
| 1910 | c => clk, |
---|
| 1911 | d => i(index), |
---|
| 1912 | q => o(index), |
---|
| 1913 | ce => ce, |
---|
| 1914 | r => clr |
---|
| 1915 | ); |
---|
| 1916 | end generate; |
---|
| 1917 | bit_is_1: if (init_const(index) = '1') generate |
---|
| 1918 | fdse_comp: fdse |
---|
| 1919 | port map ( |
---|
| 1920 | c => clk, |
---|
| 1921 | d => i(index), |
---|
| 1922 | q => o(index), |
---|
| 1923 | ce => ce, |
---|
| 1924 | s => clr |
---|
| 1925 | ); |
---|
| 1926 | end generate; |
---|
| 1927 | end generate; |
---|
| 1928 | end architecture structural; |
---|
| 1929 | -- synopsys translate_off |
---|
| 1930 | library unisim; |
---|
| 1931 | use unisim.vcomponents.all; |
---|
| 1932 | -- synopsys translate_on |
---|
| 1933 | library IEEE; |
---|
| 1934 | use IEEE.std_logic_1164.all; |
---|
| 1935 | use work.conv_pkg.all; |
---|
| 1936 | entity synth_reg_w_init is |
---|
| 1937 | generic ( |
---|
| 1938 | width: integer := 8; |
---|
| 1939 | init_index: integer := 0; |
---|
| 1940 | init_value: bit_vector := b"0000"; |
---|
| 1941 | latency: integer := 1 |
---|
| 1942 | ); |
---|
| 1943 | port ( |
---|
| 1944 | i: in std_logic_vector(width - 1 downto 0); |
---|
| 1945 | ce: in std_logic; |
---|
| 1946 | clr: in std_logic; |
---|
| 1947 | clk: in std_logic; |
---|
| 1948 | o: out std_logic_vector(width - 1 downto 0) |
---|
| 1949 | ); |
---|
| 1950 | end synth_reg_w_init; |
---|
| 1951 | architecture structural of synth_reg_w_init is |
---|
| 1952 | component single_reg_w_init |
---|
| 1953 | generic ( |
---|
| 1954 | width: integer := 8; |
---|
| 1955 | init_index: integer := 0; |
---|
| 1956 | init_value: bit_vector := b"0000" |
---|
| 1957 | ); |
---|
| 1958 | port ( |
---|
| 1959 | i: in std_logic_vector(width - 1 downto 0); |
---|
| 1960 | ce: in std_logic; |
---|
| 1961 | clr: in std_logic; |
---|
| 1962 | clk: in std_logic; |
---|
| 1963 | o: out std_logic_vector(width - 1 downto 0) |
---|
| 1964 | ); |
---|
| 1965 | end component; |
---|
| 1966 | signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0); |
---|
| 1967 | signal dly_clr: std_logic; |
---|
| 1968 | begin |
---|
| 1969 | latency_eq_0: if (latency = 0) generate |
---|
| 1970 | o <= i; |
---|
| 1971 | end generate; |
---|
| 1972 | latency_gt_0: if (latency >= 1) generate |
---|
| 1973 | dly_i((latency + 1) * width - 1 downto latency * width) <= i |
---|
| 1974 | after 200 ps; |
---|
| 1975 | dly_clr <= clr after 200 ps; |
---|
| 1976 | fd_array: for index in latency downto 1 generate |
---|
| 1977 | reg_comp: single_reg_w_init |
---|
| 1978 | generic map ( |
---|
| 1979 | width => width, |
---|
| 1980 | init_index => init_index, |
---|
| 1981 | init_value => init_value |
---|
| 1982 | ) |
---|
| 1983 | port map ( |
---|
| 1984 | clk => clk, |
---|
| 1985 | i => dly_i((index + 1) * width - 1 downto index * width), |
---|
| 1986 | o => dly_i(index * width - 1 downto (index - 1) * width), |
---|
| 1987 | ce => ce, |
---|
| 1988 | clr => dly_clr |
---|
| 1989 | ); |
---|
| 1990 | end generate; |
---|
| 1991 | o <= dly_i(width - 1 downto 0); |
---|
| 1992 | end generate; |
---|
| 1993 | end structural; |
---|
| 1994 | library IEEE; |
---|
| 1995 | use IEEE.std_logic_1164.all; |
---|
| 1996 | use IEEE.numeric_std.all; |
---|
| 1997 | use work.conv_pkg.all; |
---|
| 1998 | |
---|
| 1999 | entity constant_963ed6358a is |
---|
| 2000 | port ( |
---|
| 2001 | op : out std_logic_vector((1 - 1) downto 0); |
---|
| 2002 | clk : in std_logic; |
---|
| 2003 | ce : in std_logic; |
---|
| 2004 | clr : in std_logic); |
---|
| 2005 | end constant_963ed6358a; |
---|
| 2006 | |
---|
| 2007 | |
---|
| 2008 | architecture behavior of constant_963ed6358a is |
---|
| 2009 | begin |
---|
| 2010 | op <= "0"; |
---|
| 2011 | end behavior; |
---|
| 2012 | |
---|
| 2013 | library IEEE; |
---|
| 2014 | use IEEE.std_logic_1164.all; |
---|
| 2015 | use IEEE.numeric_std.all; |
---|
| 2016 | use work.conv_pkg.all; |
---|
| 2017 | |
---|
| 2018 | entity mcode_block_b389f41afb is |
---|
| 2019 | port ( |
---|
| 2020 | plbrst : in std_logic_vector((1 - 1) downto 0); |
---|
| 2021 | plbabus : in std_logic_vector((32 - 1) downto 0); |
---|
| 2022 | plbpavalid : in std_logic_vector((1 - 1) downto 0); |
---|
| 2023 | plbrnw : in std_logic_vector((1 - 1) downto 0); |
---|
| 2024 | plbwrdbus : in std_logic_vector((32 - 1) downto 0); |
---|
| 2025 | rddata : in std_logic_vector((32 - 1) downto 0); |
---|
| 2026 | addrpref : in std_logic_vector((20 - 1) downto 0); |
---|
| 2027 | wrdbusreg : out std_logic_vector((32 - 1) downto 0); |
---|
| 2028 | addrack : out std_logic_vector((1 - 1) downto 0); |
---|
| 2029 | rdcomp : out std_logic_vector((1 - 1) downto 0); |
---|
| 2030 | wrdack : out std_logic_vector((1 - 1) downto 0); |
---|
| 2031 | bankaddr : out std_logic_vector((2 - 1) downto 0); |
---|
| 2032 | rnwreg : out std_logic_vector((1 - 1) downto 0); |
---|
| 2033 | rddack : out std_logic_vector((1 - 1) downto 0); |
---|
| 2034 | rddbus : out std_logic_vector((32 - 1) downto 0); |
---|
| 2035 | linearaddr : out std_logic_vector((8 - 1) downto 0); |
---|
| 2036 | clk : in std_logic; |
---|
| 2037 | ce : in std_logic; |
---|
| 2038 | clr : in std_logic); |
---|
| 2039 | end mcode_block_b389f41afb; |
---|
| 2040 | |
---|
| 2041 | |
---|
| 2042 | architecture behavior of mcode_block_b389f41afb is |
---|
| 2043 | signal plbrst_2_20: unsigned((1 - 1) downto 0); |
---|
| 2044 | signal plbabus_2_28: unsigned((32 - 1) downto 0); |
---|
| 2045 | signal plbpavalid_2_37: unsigned((1 - 1) downto 0); |
---|
| 2046 | signal plbrnw_2_49: unsigned((1 - 1) downto 0); |
---|
| 2047 | signal plbwrdbus_2_57: unsigned((32 - 1) downto 0); |
---|
| 2048 | signal rddata_2_68: unsigned((32 - 1) downto 0); |
---|
| 2049 | signal addrpref_2_76: unsigned((20 - 1) downto 0); |
---|
| 2050 | signal plbrstreg_13_24_next: boolean; |
---|
| 2051 | signal plbrstreg_13_24: boolean := false; |
---|
| 2052 | signal plbabusreg_14_25_next: unsigned((32 - 1) downto 0); |
---|
| 2053 | signal plbabusreg_14_25: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; |
---|
| 2054 | signal plbpavalidreg_15_28_next: boolean; |
---|
| 2055 | signal plbpavalidreg_15_28: boolean := false; |
---|
| 2056 | signal plbrnwreg_16_24_next: unsigned((1 - 1) downto 0); |
---|
| 2057 | signal plbrnwreg_16_24: unsigned((1 - 1) downto 0) := "0"; |
---|
| 2058 | signal plbwrdbusreg_17_27_next: unsigned((32 - 1) downto 0); |
---|
| 2059 | signal plbwrdbusreg_17_27: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; |
---|
| 2060 | signal avalidreg_29_23_next: boolean; |
---|
| 2061 | signal avalidreg_29_23: boolean := false; |
---|
| 2062 | signal ps1reg_40_20_next: boolean; |
---|
| 2063 | signal ps1reg_40_20: boolean := false; |
---|
| 2064 | signal psreg_48_19_next: boolean; |
---|
| 2065 | signal psreg_48_19: boolean := false; |
---|
| 2066 | type array_type_rdcompdelay_59_25 is array (0 to (3 - 1)) of unsigned((1 - 1) downto 0); |
---|
| 2067 | signal rdcompdelay_59_25: array_type_rdcompdelay_59_25 := ( |
---|
| 2068 | "0", |
---|
| 2069 | "0", |
---|
| 2070 | "0"); |
---|
| 2071 | signal rdcompdelay_59_25_front_din: unsigned((1 - 1) downto 0); |
---|
| 2072 | signal rdcompdelay_59_25_back: unsigned((1 - 1) downto 0); |
---|
| 2073 | signal rdcompdelay_59_25_push_front_pop_back_en: std_logic; |
---|
| 2074 | signal rdcompreg_63_23_next: unsigned((1 - 1) downto 0); |
---|
| 2075 | signal rdcompreg_63_23: unsigned((1 - 1) downto 0) := "0"; |
---|
| 2076 | signal rddackreg_67_23_next: unsigned((1 - 1) downto 0); |
---|
| 2077 | signal rddackreg_67_23: unsigned((1 - 1) downto 0) := "0"; |
---|
| 2078 | signal wrdackreg_71_23_next: unsigned((1 - 1) downto 0); |
---|
| 2079 | signal wrdackreg_71_23: unsigned((1 - 1) downto 0) := "0"; |
---|
| 2080 | signal rddbusreg_85_23_next: unsigned((32 - 1) downto 0); |
---|
| 2081 | signal rddbusreg_85_23: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; |
---|
| 2082 | signal bankaddr_21_1_slice: unsigned((2 - 1) downto 0); |
---|
| 2083 | signal linearaddr_22_1_slice: unsigned((8 - 1) downto 0); |
---|
| 2084 | signal addrpref_in_33_1_slice: unsigned((20 - 1) downto 0); |
---|
| 2085 | signal rel_34_4: boolean; |
---|
| 2086 | signal ps1_join_34_1: boolean; |
---|
| 2087 | signal ps_43_1_bit: boolean; |
---|
| 2088 | signal bitnot_50_49: boolean; |
---|
| 2089 | signal bitnot_50_73: boolean; |
---|
| 2090 | signal bit_50_49: boolean; |
---|
| 2091 | signal addrack_50_1_convert: unsigned((1 - 1) downto 0); |
---|
| 2092 | signal bit_56_43: unsigned((1 - 1) downto 0); |
---|
| 2093 | signal bitnot_73_35: unsigned((1 - 1) downto 0); |
---|
| 2094 | signal wrdackreg_73_1_bit: unsigned((1 - 1) downto 0); |
---|
| 2095 | signal rdsel_77_1_bit: unsigned((1 - 1) downto 0); |
---|
| 2096 | signal rel_79_4: boolean; |
---|
| 2097 | signal rddbus1_join_79_1: unsigned((32 - 1) downto 0); |
---|
| 2098 | signal plbwrdbusreg_98_1_slice: unsigned((32 - 1) downto 0); |
---|
| 2099 | signal plbrstreg_13_24_next_x_000000: boolean; |
---|
| 2100 | signal plbpavalidreg_15_28_next_x_000000: boolean; |
---|
| 2101 | begin |
---|
| 2102 | plbrst_2_20 <= std_logic_vector_to_unsigned(plbrst); |
---|
| 2103 | plbabus_2_28 <= std_logic_vector_to_unsigned(plbabus); |
---|
| 2104 | plbpavalid_2_37 <= std_logic_vector_to_unsigned(plbpavalid); |
---|
| 2105 | plbrnw_2_49 <= std_logic_vector_to_unsigned(plbrnw); |
---|
| 2106 | plbwrdbus_2_57 <= std_logic_vector_to_unsigned(plbwrdbus); |
---|
| 2107 | rddata_2_68 <= std_logic_vector_to_unsigned(rddata); |
---|
| 2108 | addrpref_2_76 <= std_logic_vector_to_unsigned(addrpref); |
---|
| 2109 | proc_plbrstreg_13_24: process (clk) |
---|
| 2110 | is |
---|
| 2111 | begin |
---|
| 2112 | if (clk'event and (clk = '1')) then |
---|
| 2113 | if (ce = '1') then |
---|
| 2114 | plbrstreg_13_24 <= plbrstreg_13_24_next; |
---|
| 2115 | end if; |
---|
| 2116 | end if; |
---|
| 2117 | end process proc_plbrstreg_13_24; |
---|
| 2118 | proc_plbabusreg_14_25: process (clk) |
---|
| 2119 | is |
---|
| 2120 | begin |
---|
| 2121 | if (clk'event and (clk = '1')) then |
---|
| 2122 | if (ce = '1') then |
---|
| 2123 | plbabusreg_14_25 <= plbabusreg_14_25_next; |
---|
| 2124 | end if; |
---|
| 2125 | end if; |
---|
| 2126 | end process proc_plbabusreg_14_25; |
---|
| 2127 | proc_plbpavalidreg_15_28: process (clk) |
---|
| 2128 | is |
---|
| 2129 | begin |
---|
| 2130 | if (clk'event and (clk = '1')) then |
---|
| 2131 | if (ce = '1') then |
---|
| 2132 | plbpavalidreg_15_28 <= plbpavalidreg_15_28_next; |
---|
| 2133 | end if; |
---|
| 2134 | end if; |
---|
| 2135 | end process proc_plbpavalidreg_15_28; |
---|
| 2136 | proc_plbrnwreg_16_24: process (clk) |
---|
| 2137 | is |
---|
| 2138 | begin |
---|
| 2139 | if (clk'event and (clk = '1')) then |
---|
| 2140 | if (ce = '1') then |
---|
| 2141 | plbrnwreg_16_24 <= plbrnwreg_16_24_next; |
---|
| 2142 | end if; |
---|
| 2143 | end if; |
---|
| 2144 | end process proc_plbrnwreg_16_24; |
---|
| 2145 | proc_plbwrdbusreg_17_27: process (clk) |
---|
| 2146 | is |
---|
| 2147 | begin |
---|
| 2148 | if (clk'event and (clk = '1')) then |
---|
| 2149 | if (ce = '1') then |
---|
| 2150 | plbwrdbusreg_17_27 <= plbwrdbusreg_17_27_next; |
---|
| 2151 | end if; |
---|
| 2152 | end if; |
---|
| 2153 | end process proc_plbwrdbusreg_17_27; |
---|
| 2154 | proc_avalidreg_29_23: process (clk) |
---|
| 2155 | is |
---|
| 2156 | begin |
---|
| 2157 | if (clk'event and (clk = '1')) then |
---|
| 2158 | if (ce = '1') then |
---|
| 2159 | avalidreg_29_23 <= avalidreg_29_23_next; |
---|
| 2160 | end if; |
---|
| 2161 | end if; |
---|
| 2162 | end process proc_avalidreg_29_23; |
---|
| 2163 | proc_ps1reg_40_20: process (clk) |
---|
| 2164 | is |
---|
| 2165 | begin |
---|
| 2166 | if (clk'event and (clk = '1')) then |
---|
| 2167 | if (ce = '1') then |
---|
| 2168 | ps1reg_40_20 <= ps1reg_40_20_next; |
---|
| 2169 | end if; |
---|
| 2170 | end if; |
---|
| 2171 | end process proc_ps1reg_40_20; |
---|
| 2172 | proc_psreg_48_19: process (clk) |
---|
| 2173 | is |
---|
| 2174 | begin |
---|
| 2175 | if (clk'event and (clk = '1')) then |
---|
| 2176 | if (ce = '1') then |
---|
| 2177 | psreg_48_19 <= psreg_48_19_next; |
---|
| 2178 | end if; |
---|
| 2179 | end if; |
---|
| 2180 | end process proc_psreg_48_19; |
---|
| 2181 | rdcompdelay_59_25_back <= rdcompdelay_59_25(2); |
---|
| 2182 | proc_rdcompdelay_59_25: process (clk) |
---|
| 2183 | is |
---|
| 2184 | variable i: integer; |
---|
| 2185 | begin |
---|
| 2186 | if (clk'event and (clk = '1')) then |
---|
| 2187 | if ((ce = '1') and (rdcompdelay_59_25_push_front_pop_back_en = '1')) then |
---|
| 2188 | for i in 2 downto 1 loop |
---|
| 2189 | rdcompdelay_59_25(i) <= rdcompdelay_59_25(i-1); |
---|
| 2190 | end loop; |
---|
| 2191 | rdcompdelay_59_25(0) <= rdcompdelay_59_25_front_din; |
---|
| 2192 | end if; |
---|
| 2193 | end if; |
---|
| 2194 | end process proc_rdcompdelay_59_25; |
---|
| 2195 | proc_rdcompreg_63_23: process (clk) |
---|
| 2196 | is |
---|
| 2197 | begin |
---|
| 2198 | if (clk'event and (clk = '1')) then |
---|
| 2199 | if (ce = '1') then |
---|
| 2200 | rdcompreg_63_23 <= rdcompreg_63_23_next; |
---|
| 2201 | end if; |
---|
| 2202 | end if; |
---|
| 2203 | end process proc_rdcompreg_63_23; |
---|
| 2204 | proc_rddackreg_67_23: process (clk) |
---|
| 2205 | is |
---|
| 2206 | begin |
---|
| 2207 | if (clk'event and (clk = '1')) then |
---|
| 2208 | if (ce = '1') then |
---|
| 2209 | rddackreg_67_23 <= rddackreg_67_23_next; |
---|
| 2210 | end if; |
---|
| 2211 | end if; |
---|
| 2212 | end process proc_rddackreg_67_23; |
---|
| 2213 | proc_wrdackreg_71_23: process (clk) |
---|
| 2214 | is |
---|
| 2215 | begin |
---|
| 2216 | if (clk'event and (clk = '1')) then |
---|
| 2217 | if (ce = '1') then |
---|
| 2218 | wrdackreg_71_23 <= wrdackreg_71_23_next; |
---|
| 2219 | end if; |
---|
| 2220 | end if; |
---|
| 2221 | end process proc_wrdackreg_71_23; |
---|
| 2222 | proc_rddbusreg_85_23: process (clk) |
---|
| 2223 | is |
---|
| 2224 | begin |
---|
| 2225 | if (clk'event and (clk = '1')) then |
---|
| 2226 | if (ce = '1') then |
---|
| 2227 | rddbusreg_85_23 <= rddbusreg_85_23_next; |
---|
| 2228 | end if; |
---|
| 2229 | end if; |
---|
| 2230 | end process proc_rddbusreg_85_23; |
---|
| 2231 | bankaddr_21_1_slice <= u2u_slice(plbabusreg_14_25, 11, 10); |
---|
| 2232 | linearaddr_22_1_slice <= u2u_slice(plbabusreg_14_25, 9, 2); |
---|
| 2233 | addrpref_in_33_1_slice <= u2u_slice(plbabusreg_14_25, 31, 12); |
---|
| 2234 | rel_34_4 <= addrpref_in_33_1_slice = addrpref_2_76; |
---|
| 2235 | proc_if_34_1: process (rel_34_4) |
---|
| 2236 | is |
---|
| 2237 | begin |
---|
| 2238 | if rel_34_4 then |
---|
| 2239 | ps1_join_34_1 <= true; |
---|
| 2240 | else |
---|
| 2241 | ps1_join_34_1 <= false; |
---|
| 2242 | end if; |
---|
| 2243 | end process proc_if_34_1; |
---|
| 2244 | ps_43_1_bit <= ((boolean_to_vector(ps1_join_34_1) and boolean_to_vector(plbpavalidreg_15_28)) = "1"); |
---|
| 2245 | bitnot_50_49 <= ((not boolean_to_vector(plbrstreg_13_24)) = "1"); |
---|
| 2246 | bitnot_50_73 <= ((not boolean_to_vector(psreg_48_19)) = "1"); |
---|
| 2247 | bit_50_49 <= ((boolean_to_vector(bitnot_50_49) and boolean_to_vector(ps_43_1_bit) and boolean_to_vector(bitnot_50_73)) = "1"); |
---|
| 2248 | addrack_50_1_convert <= u2u_cast(std_logic_vector_to_unsigned(boolean_to_vector(bit_50_49)), 0, 1, 0); |
---|
| 2249 | bit_56_43 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(plbrnwreg_16_24)); |
---|
| 2250 | bitnot_73_35 <= std_logic_vector_to_unsigned(not unsigned_to_std_logic_vector(plbrnwreg_16_24)); |
---|
| 2251 | wrdackreg_73_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_50_1_convert) and unsigned_to_std_logic_vector(bitnot_73_35)); |
---|
| 2252 | rdsel_77_1_bit <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(rdcompdelay_59_25_back) or unsigned_to_std_logic_vector(rdcompreg_63_23)); |
---|
| 2253 | rel_79_4 <= rdsel_77_1_bit = std_logic_vector_to_unsigned("1"); |
---|
| 2254 | proc_if_79_1: process (rddata_2_68, rel_79_4) |
---|
| 2255 | is |
---|
| 2256 | begin |
---|
| 2257 | if rel_79_4 then |
---|
| 2258 | rddbus1_join_79_1 <= rddata_2_68; |
---|
| 2259 | else |
---|
| 2260 | rddbus1_join_79_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); |
---|
| 2261 | end if; |
---|
| 2262 | end process proc_if_79_1; |
---|
| 2263 | plbwrdbusreg_98_1_slice <= u2u_slice(plbwrdbus_2_57, 31, 0); |
---|
| 2264 | plbrstreg_13_24_next_x_000000 <= (plbrst_2_20 /= "0"); |
---|
| 2265 | plbrstreg_13_24_next <= plbrstreg_13_24_next_x_000000; |
---|
| 2266 | plbabusreg_14_25_next <= plbabus_2_28; |
---|
| 2267 | plbpavalidreg_15_28_next_x_000000 <= (plbpavalid_2_37 /= "0"); |
---|
| 2268 | plbpavalidreg_15_28_next <= plbpavalidreg_15_28_next_x_000000; |
---|
| 2269 | plbrnwreg_16_24_next <= plbrnw_2_49; |
---|
| 2270 | plbwrdbusreg_17_27_next <= plbwrdbusreg_98_1_slice; |
---|
| 2271 | avalidreg_29_23_next <= plbpavalidreg_15_28; |
---|
| 2272 | ps1reg_40_20_next <= ps1_join_34_1; |
---|
| 2273 | psreg_48_19_next <= ps_43_1_bit; |
---|
| 2274 | rdcompdelay_59_25_front_din <= bit_56_43; |
---|
| 2275 | rdcompdelay_59_25_push_front_pop_back_en <= '1'; |
---|
| 2276 | rdcompreg_63_23_next <= rdcompdelay_59_25_back; |
---|
| 2277 | rddackreg_67_23_next <= rdcompreg_63_23; |
---|
| 2278 | wrdackreg_71_23_next <= wrdackreg_73_1_bit; |
---|
| 2279 | rddbusreg_85_23_next <= rddbus1_join_79_1; |
---|
| 2280 | wrdbusreg <= unsigned_to_std_logic_vector(plbwrdbusreg_17_27); |
---|
| 2281 | addrack <= unsigned_to_std_logic_vector(addrack_50_1_convert); |
---|
| 2282 | rdcomp <= unsigned_to_std_logic_vector(rdcompreg_63_23); |
---|
| 2283 | wrdack <= unsigned_to_std_logic_vector(wrdackreg_71_23); |
---|
| 2284 | bankaddr <= unsigned_to_std_logic_vector(bankaddr_21_1_slice); |
---|
| 2285 | rnwreg <= unsigned_to_std_logic_vector(plbrnwreg_16_24); |
---|
| 2286 | rddack <= unsigned_to_std_logic_vector(rddackreg_67_23); |
---|
| 2287 | rddbus <= unsigned_to_std_logic_vector(rddbusreg_85_23); |
---|
| 2288 | linearaddr <= unsigned_to_std_logic_vector(linearaddr_22_1_slice); |
---|
| 2289 | end behavior; |
---|
| 2290 | |
---|
| 2291 | library IEEE; |
---|
| 2292 | use IEEE.std_logic_1164.all; |
---|
| 2293 | use IEEE.numeric_std.all; |
---|
| 2294 | use work.conv_pkg.all; |
---|
| 2295 | |
---|
| 2296 | entity mcode_block_b59e0d51fc is |
---|
| 2297 | port ( |
---|
| 2298 | wrdbus : in std_logic_vector((32 - 1) downto 0); |
---|
| 2299 | bankaddr : in std_logic_vector((2 - 1) downto 0); |
---|
| 2300 | linearaddr : in std_logic_vector((8 - 1) downto 0); |
---|
| 2301 | rnwreg : in std_logic_vector((1 - 1) downto 0); |
---|
| 2302 | addrack : in std_logic_vector((1 - 1) downto 0); |
---|
| 2303 | sm_timer0_timeleft : in std_logic_vector((32 - 1) downto 0); |
---|
| 2304 | sm_timer1_timeleft : in std_logic_vector((32 - 1) downto 0); |
---|
| 2305 | sm_timer2_timeleft : in std_logic_vector((32 - 1) downto 0); |
---|
| 2306 | sm_timer3_timeleft : in std_logic_vector((32 - 1) downto 0); |
---|
| 2307 | sm_timer_control_r : in std_logic_vector((32 - 1) downto 0); |
---|
| 2308 | sm_timer_status : in std_logic_vector((32 - 1) downto 0); |
---|
| 2309 | sm_timer0_countto : in std_logic_vector((32 - 1) downto 0); |
---|
| 2310 | sm_timer1_countto : in std_logic_vector((32 - 1) downto 0); |
---|
| 2311 | sm_timer2_countto : in std_logic_vector((32 - 1) downto 0); |
---|
| 2312 | sm_timer3_countto : in std_logic_vector((32 - 1) downto 0); |
---|
| 2313 | sm_timer_control_w : in std_logic_vector((32 - 1) downto 0); |
---|
| 2314 | read_bank_out : out std_logic_vector((32 - 1) downto 0); |
---|
| 2315 | sm_timer0_countto_din : out std_logic_vector((32 - 1) downto 0); |
---|
| 2316 | sm_timer0_countto_en : out std_logic_vector((1 - 1) downto 0); |
---|
| 2317 | sm_timer1_countto_din : out std_logic_vector((32 - 1) downto 0); |
---|
| 2318 | sm_timer1_countto_en : out std_logic_vector((1 - 1) downto 0); |
---|
| 2319 | sm_timer2_countto_din : out std_logic_vector((32 - 1) downto 0); |
---|
| 2320 | sm_timer2_countto_en : out std_logic_vector((1 - 1) downto 0); |
---|
| 2321 | sm_timer3_countto_din : out std_logic_vector((32 - 1) downto 0); |
---|
| 2322 | sm_timer3_countto_en : out std_logic_vector((1 - 1) downto 0); |
---|
| 2323 | sm_timer_control_w_din : out std_logic_vector((32 - 1) downto 0); |
---|
| 2324 | sm_timer_control_w_en : out std_logic_vector((1 - 1) downto 0); |
---|
| 2325 | clk : in std_logic; |
---|
| 2326 | ce : in std_logic; |
---|
| 2327 | clr : in std_logic); |
---|
| 2328 | end mcode_block_b59e0d51fc; |
---|
| 2329 | |
---|
| 2330 | |
---|
| 2331 | architecture behavior of mcode_block_b59e0d51fc is |
---|
| 2332 | signal wrdbus_1_273: unsigned((32 - 1) downto 0); |
---|
| 2333 | signal bankaddr_1_281: unsigned((2 - 1) downto 0); |
---|
| 2334 | signal linearaddr_1_291: unsigned((8 - 1) downto 0); |
---|
| 2335 | signal rnwreg_1_303: unsigned((1 - 1) downto 0); |
---|
| 2336 | signal addrack_1_311: unsigned((1 - 1) downto 0); |
---|
| 2337 | signal sm_timer0_timeleft_1_320: unsigned((32 - 1) downto 0); |
---|
| 2338 | signal sm_timer1_timeleft_1_340: unsigned((32 - 1) downto 0); |
---|
| 2339 | signal sm_timer2_timeleft_1_360: unsigned((32 - 1) downto 0); |
---|
| 2340 | signal sm_timer3_timeleft_1_380: unsigned((32 - 1) downto 0); |
---|
| 2341 | signal sm_timer_control_r_1_400: unsigned((32 - 1) downto 0); |
---|
| 2342 | signal sm_timer_status_1_420: unsigned((32 - 1) downto 0); |
---|
| 2343 | signal sm_timer0_countto_1_437: unsigned((32 - 1) downto 0); |
---|
| 2344 | signal sm_timer1_countto_1_456: unsigned((32 - 1) downto 0); |
---|
| 2345 | signal sm_timer2_countto_1_475: unsigned((32 - 1) downto 0); |
---|
| 2346 | signal sm_timer3_countto_1_494: unsigned((32 - 1) downto 0); |
---|
| 2347 | signal sm_timer_control_w_1_513: unsigned((32 - 1) downto 0); |
---|
| 2348 | signal reg_bank_out_reg_47_30_next: unsigned((32 - 1) downto 0); |
---|
| 2349 | signal reg_bank_out_reg_47_30: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; |
---|
| 2350 | signal read_bank_out_reg_158_31_next: unsigned((32 - 1) downto 0); |
---|
| 2351 | signal read_bank_out_reg_158_31: unsigned((32 - 1) downto 0) := "00000000000000000000000000000000"; |
---|
| 2352 | signal bankaddr_reg_161_26_next: unsigned((2 - 1) downto 0); |
---|
| 2353 | signal bankaddr_reg_161_26: unsigned((2 - 1) downto 0) := "00"; |
---|
| 2354 | signal rel_50_4: boolean; |
---|
| 2355 | signal rel_52_8: boolean; |
---|
| 2356 | signal rel_54_8: boolean; |
---|
| 2357 | signal rel_56_8: boolean; |
---|
| 2358 | signal rel_58_8: boolean; |
---|
| 2359 | signal rel_60_8: boolean; |
---|
| 2360 | signal rel_62_8: boolean; |
---|
| 2361 | signal rel_64_8: boolean; |
---|
| 2362 | signal rel_66_8: boolean; |
---|
| 2363 | signal rel_68_8: boolean; |
---|
| 2364 | signal rel_70_8: boolean; |
---|
| 2365 | signal reg_bank_out_reg_join_50_1: unsigned((32 - 1) downto 0); |
---|
| 2366 | signal opcode_81_1_concat: unsigned((12 - 1) downto 0); |
---|
| 2367 | signal rel_102_4: boolean; |
---|
| 2368 | signal sm_timer0_countto_en_join_102_1: boolean; |
---|
| 2369 | signal rel_108_4: boolean; |
---|
| 2370 | signal sm_timer1_countto_en_join_108_1: boolean; |
---|
| 2371 | signal rel_114_4: boolean; |
---|
| 2372 | signal sm_timer2_countto_en_join_114_1: boolean; |
---|
| 2373 | signal rel_120_4: boolean; |
---|
| 2374 | signal sm_timer3_countto_en_join_120_1: boolean; |
---|
| 2375 | signal rel_126_4: boolean; |
---|
| 2376 | signal sm_timer_control_w_en_join_126_1: boolean; |
---|
| 2377 | signal slice_141_42: unsigned((32 - 1) downto 0); |
---|
| 2378 | signal slice_144_42: unsigned((32 - 1) downto 0); |
---|
| 2379 | signal slice_147_42: unsigned((32 - 1) downto 0); |
---|
| 2380 | signal slice_150_42: unsigned((32 - 1) downto 0); |
---|
| 2381 | signal slice_153_43: unsigned((32 - 1) downto 0); |
---|
| 2382 | signal rel_163_4: boolean; |
---|
| 2383 | signal rel_166_8: boolean; |
---|
| 2384 | signal rel_169_8: boolean; |
---|
| 2385 | signal rel_172_8: boolean; |
---|
| 2386 | signal read_bank_out_reg_join_163_1: unsigned((32 - 1) downto 0); |
---|
| 2387 | begin |
---|
| 2388 | wrdbus_1_273 <= std_logic_vector_to_unsigned(wrdbus); |
---|
| 2389 | bankaddr_1_281 <= std_logic_vector_to_unsigned(bankaddr); |
---|
| 2390 | linearaddr_1_291 <= std_logic_vector_to_unsigned(linearaddr); |
---|
| 2391 | rnwreg_1_303 <= std_logic_vector_to_unsigned(rnwreg); |
---|
| 2392 | addrack_1_311 <= std_logic_vector_to_unsigned(addrack); |
---|
| 2393 | sm_timer0_timeleft_1_320 <= std_logic_vector_to_unsigned(sm_timer0_timeleft); |
---|
| 2394 | sm_timer1_timeleft_1_340 <= std_logic_vector_to_unsigned(sm_timer1_timeleft); |
---|
| 2395 | sm_timer2_timeleft_1_360 <= std_logic_vector_to_unsigned(sm_timer2_timeleft); |
---|
| 2396 | sm_timer3_timeleft_1_380 <= std_logic_vector_to_unsigned(sm_timer3_timeleft); |
---|
| 2397 | sm_timer_control_r_1_400 <= std_logic_vector_to_unsigned(sm_timer_control_r); |
---|
| 2398 | sm_timer_status_1_420 <= std_logic_vector_to_unsigned(sm_timer_status); |
---|
| 2399 | sm_timer0_countto_1_437 <= std_logic_vector_to_unsigned(sm_timer0_countto); |
---|
| 2400 | sm_timer1_countto_1_456 <= std_logic_vector_to_unsigned(sm_timer1_countto); |
---|
| 2401 | sm_timer2_countto_1_475 <= std_logic_vector_to_unsigned(sm_timer2_countto); |
---|
| 2402 | sm_timer3_countto_1_494 <= std_logic_vector_to_unsigned(sm_timer3_countto); |
---|
| 2403 | sm_timer_control_w_1_513 <= std_logic_vector_to_unsigned(sm_timer_control_w); |
---|
| 2404 | proc_reg_bank_out_reg_47_30: process (clk) |
---|
| 2405 | is |
---|
| 2406 | begin |
---|
| 2407 | if (clk'event and (clk = '1')) then |
---|
| 2408 | if (ce = '1') then |
---|
| 2409 | reg_bank_out_reg_47_30 <= reg_bank_out_reg_47_30_next; |
---|
| 2410 | end if; |
---|
| 2411 | end if; |
---|
| 2412 | end process proc_reg_bank_out_reg_47_30; |
---|
| 2413 | proc_read_bank_out_reg_158_31: process (clk) |
---|
| 2414 | is |
---|
| 2415 | begin |
---|
| 2416 | if (clk'event and (clk = '1')) then |
---|
| 2417 | if (ce = '1') then |
---|
| 2418 | read_bank_out_reg_158_31 <= read_bank_out_reg_158_31_next; |
---|
| 2419 | end if; |
---|
| 2420 | end if; |
---|
| 2421 | end process proc_read_bank_out_reg_158_31; |
---|
| 2422 | proc_bankaddr_reg_161_26: process (clk) |
---|
| 2423 | is |
---|
| 2424 | begin |
---|
| 2425 | if (clk'event and (clk = '1')) then |
---|
| 2426 | if (ce = '1') then |
---|
| 2427 | bankaddr_reg_161_26 <= bankaddr_reg_161_26_next; |
---|
| 2428 | end if; |
---|
| 2429 | end if; |
---|
| 2430 | end process proc_bankaddr_reg_161_26; |
---|
| 2431 | rel_50_4 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000101"); |
---|
| 2432 | rel_52_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000110"); |
---|
| 2433 | rel_54_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000111"); |
---|
| 2434 | rel_56_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001000"); |
---|
| 2435 | rel_58_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001001"); |
---|
| 2436 | rel_60_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00001010"); |
---|
| 2437 | rel_62_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000000"); |
---|
| 2438 | rel_64_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000001"); |
---|
| 2439 | rel_66_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000010"); |
---|
| 2440 | rel_68_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000011"); |
---|
| 2441 | rel_70_8 <= linearaddr_1_291 = std_logic_vector_to_unsigned("00000100"); |
---|
| 2442 | proc_if_50_1: process (reg_bank_out_reg_47_30, rel_50_4, rel_52_8, rel_54_8, rel_56_8, rel_58_8, rel_60_8, rel_62_8, rel_64_8, rel_66_8, rel_68_8, rel_70_8, sm_timer0_countto_1_437, sm_timer0_timeleft_1_320, sm_timer1_countto_1_456, sm_timer1_timeleft_1_340, sm_timer2_countto_1_475, sm_timer2_timeleft_1_360, sm_timer3_countto_1_494, sm_timer3_timeleft_1_380, sm_timer_control_r_1_400, sm_timer_control_w_1_513, sm_timer_status_1_420) |
---|
| 2443 | is |
---|
| 2444 | begin |
---|
| 2445 | if rel_50_4 then |
---|
| 2446 | reg_bank_out_reg_join_50_1 <= sm_timer0_timeleft_1_320; |
---|
| 2447 | elsif rel_52_8 then |
---|
| 2448 | reg_bank_out_reg_join_50_1 <= sm_timer1_timeleft_1_340; |
---|
| 2449 | elsif rel_54_8 then |
---|
| 2450 | reg_bank_out_reg_join_50_1 <= sm_timer2_timeleft_1_360; |
---|
| 2451 | elsif rel_56_8 then |
---|
| 2452 | reg_bank_out_reg_join_50_1 <= sm_timer3_timeleft_1_380; |
---|
| 2453 | elsif rel_58_8 then |
---|
| 2454 | reg_bank_out_reg_join_50_1 <= sm_timer_control_r_1_400; |
---|
| 2455 | elsif rel_60_8 then |
---|
| 2456 | reg_bank_out_reg_join_50_1 <= sm_timer_status_1_420; |
---|
| 2457 | elsif rel_62_8 then |
---|
| 2458 | reg_bank_out_reg_join_50_1 <= sm_timer0_countto_1_437; |
---|
| 2459 | elsif rel_64_8 then |
---|
| 2460 | reg_bank_out_reg_join_50_1 <= sm_timer1_countto_1_456; |
---|
| 2461 | elsif rel_66_8 then |
---|
| 2462 | reg_bank_out_reg_join_50_1 <= sm_timer2_countto_1_475; |
---|
| 2463 | elsif rel_68_8 then |
---|
| 2464 | reg_bank_out_reg_join_50_1 <= sm_timer3_countto_1_494; |
---|
| 2465 | elsif rel_70_8 then |
---|
| 2466 | reg_bank_out_reg_join_50_1 <= sm_timer_control_w_1_513; |
---|
| 2467 | else |
---|
| 2468 | reg_bank_out_reg_join_50_1 <= reg_bank_out_reg_47_30; |
---|
| 2469 | end if; |
---|
| 2470 | end process proc_if_50_1; |
---|
| 2471 | opcode_81_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(addrack_1_311) & unsigned_to_std_logic_vector(rnwreg_1_303) & unsigned_to_std_logic_vector(bankaddr_1_281) & unsigned_to_std_logic_vector(linearaddr_1_291)); |
---|
| 2472 | rel_102_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000000"); |
---|
| 2473 | proc_if_102_1: process (rel_102_4) |
---|
| 2474 | is |
---|
| 2475 | begin |
---|
| 2476 | if rel_102_4 then |
---|
| 2477 | sm_timer0_countto_en_join_102_1 <= true; |
---|
| 2478 | else |
---|
| 2479 | sm_timer0_countto_en_join_102_1 <= false; |
---|
| 2480 | end if; |
---|
| 2481 | end process proc_if_102_1; |
---|
| 2482 | rel_108_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000001"); |
---|
| 2483 | proc_if_108_1: process (rel_108_4) |
---|
| 2484 | is |
---|
| 2485 | begin |
---|
| 2486 | if rel_108_4 then |
---|
| 2487 | sm_timer1_countto_en_join_108_1 <= true; |
---|
| 2488 | else |
---|
| 2489 | sm_timer1_countto_en_join_108_1 <= false; |
---|
| 2490 | end if; |
---|
| 2491 | end process proc_if_108_1; |
---|
| 2492 | rel_114_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000010"); |
---|
| 2493 | proc_if_114_1: process (rel_114_4) |
---|
| 2494 | is |
---|
| 2495 | begin |
---|
| 2496 | if rel_114_4 then |
---|
| 2497 | sm_timer2_countto_en_join_114_1 <= true; |
---|
| 2498 | else |
---|
| 2499 | sm_timer2_countto_en_join_114_1 <= false; |
---|
| 2500 | end if; |
---|
| 2501 | end process proc_if_114_1; |
---|
| 2502 | rel_120_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000011"); |
---|
| 2503 | proc_if_120_1: process (rel_120_4) |
---|
| 2504 | is |
---|
| 2505 | begin |
---|
| 2506 | if rel_120_4 then |
---|
| 2507 | sm_timer3_countto_en_join_120_1 <= true; |
---|
| 2508 | else |
---|
| 2509 | sm_timer3_countto_en_join_120_1 <= false; |
---|
| 2510 | end if; |
---|
| 2511 | end process proc_if_120_1; |
---|
| 2512 | rel_126_4 <= opcode_81_1_concat = std_logic_vector_to_unsigned("101000000100"); |
---|
| 2513 | proc_if_126_1: process (rel_126_4) |
---|
| 2514 | is |
---|
| 2515 | begin |
---|
| 2516 | if rel_126_4 then |
---|
| 2517 | sm_timer_control_w_en_join_126_1 <= true; |
---|
| 2518 | else |
---|
| 2519 | sm_timer_control_w_en_join_126_1 <= false; |
---|
| 2520 | end if; |
---|
| 2521 | end process proc_if_126_1; |
---|
| 2522 | slice_141_42 <= u2u_slice(wrdbus_1_273, 31, 0); |
---|
| 2523 | slice_144_42 <= u2u_slice(wrdbus_1_273, 31, 0); |
---|
| 2524 | slice_147_42 <= u2u_slice(wrdbus_1_273, 31, 0); |
---|
| 2525 | slice_150_42 <= u2u_slice(wrdbus_1_273, 31, 0); |
---|
| 2526 | slice_153_43 <= u2u_slice(wrdbus_1_273, 31, 0); |
---|
| 2527 | rel_163_4 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("00"); |
---|
| 2528 | rel_166_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("01"); |
---|
| 2529 | rel_169_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("10"); |
---|
| 2530 | rel_172_8 <= bankaddr_reg_161_26 = std_logic_vector_to_unsigned("11"); |
---|
| 2531 | proc_if_163_1: process (read_bank_out_reg_158_31, reg_bank_out_reg_47_30, rel_163_4, rel_166_8, rel_169_8, rel_172_8) |
---|
| 2532 | is |
---|
| 2533 | begin |
---|
| 2534 | if rel_163_4 then |
---|
| 2535 | read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); |
---|
| 2536 | elsif rel_166_8 then |
---|
| 2537 | read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); |
---|
| 2538 | elsif rel_169_8 then |
---|
| 2539 | read_bank_out_reg_join_163_1 <= reg_bank_out_reg_47_30; |
---|
| 2540 | elsif rel_172_8 then |
---|
| 2541 | read_bank_out_reg_join_163_1 <= std_logic_vector_to_unsigned("00000000000000000000000000000000"); |
---|
| 2542 | else |
---|
| 2543 | read_bank_out_reg_join_163_1 <= read_bank_out_reg_158_31; |
---|
| 2544 | end if; |
---|
| 2545 | end process proc_if_163_1; |
---|
| 2546 | reg_bank_out_reg_47_30_next <= reg_bank_out_reg_join_50_1; |
---|
| 2547 | read_bank_out_reg_158_31_next <= read_bank_out_reg_join_163_1; |
---|
| 2548 | bankaddr_reg_161_26_next <= bankaddr_1_281; |
---|
| 2549 | read_bank_out <= unsigned_to_std_logic_vector(read_bank_out_reg_158_31); |
---|
| 2550 | sm_timer0_countto_din <= unsigned_to_std_logic_vector(slice_141_42); |
---|
| 2551 | sm_timer0_countto_en <= boolean_to_vector(sm_timer0_countto_en_join_102_1); |
---|
| 2552 | sm_timer1_countto_din <= unsigned_to_std_logic_vector(slice_144_42); |
---|
| 2553 | sm_timer1_countto_en <= boolean_to_vector(sm_timer1_countto_en_join_108_1); |
---|
| 2554 | sm_timer2_countto_din <= unsigned_to_std_logic_vector(slice_147_42); |
---|
| 2555 | sm_timer2_countto_en <= boolean_to_vector(sm_timer2_countto_en_join_114_1); |
---|
| 2556 | sm_timer3_countto_din <= unsigned_to_std_logic_vector(slice_150_42); |
---|
| 2557 | sm_timer3_countto_en <= boolean_to_vector(sm_timer3_countto_en_join_120_1); |
---|
| 2558 | sm_timer_control_w_din <= unsigned_to_std_logic_vector(slice_153_43); |
---|
| 2559 | sm_timer_control_w_en <= boolean_to_vector(sm_timer_control_w_en_join_126_1); |
---|
| 2560 | end behavior; |
---|
| 2561 | |
---|
| 2562 | library IEEE; |
---|
| 2563 | use IEEE.std_logic_1164.all; |
---|
| 2564 | use IEEE.numeric_std.all; |
---|
| 2565 | use work.conv_pkg.all; |
---|
| 2566 | |
---|
| 2567 | entity inverter_e5b38cca3b is |
---|
| 2568 | port ( |
---|
| 2569 | ip : in std_logic_vector((1 - 1) downto 0); |
---|
| 2570 | op : out std_logic_vector((1 - 1) downto 0); |
---|
| 2571 | clk : in std_logic; |
---|
| 2572 | ce : in std_logic; |
---|
| 2573 | clr : in std_logic); |
---|
| 2574 | end inverter_e5b38cca3b; |
---|
| 2575 | |
---|
| 2576 | |
---|
| 2577 | architecture behavior of inverter_e5b38cca3b is |
---|
| 2578 | signal ip_1_26: boolean; |
---|
| 2579 | type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean; |
---|
| 2580 | signal op_mem_22_20: array_type_op_mem_22_20 := ( |
---|
| 2581 | 0 => false); |
---|
| 2582 | signal op_mem_22_20_front_din: boolean; |
---|
| 2583 | signal op_mem_22_20_back: boolean; |
---|
| 2584 | signal op_mem_22_20_push_front_pop_back_en: std_logic; |
---|
| 2585 | signal internal_ip_12_1_bitnot: boolean; |
---|
| 2586 | begin |
---|
| 2587 | ip_1_26 <= ((ip) = "1"); |
---|
| 2588 | op_mem_22_20_back <= op_mem_22_20(0); |
---|
| 2589 | proc_op_mem_22_20: process (clk) |
---|
| 2590 | is |
---|
| 2591 | variable i: integer; |
---|
| 2592 | begin |
---|
| 2593 | if (clk'event and (clk = '1')) then |
---|
| 2594 | if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then |
---|
| 2595 | op_mem_22_20(0) <= op_mem_22_20_front_din; |
---|
| 2596 | end if; |
---|
| 2597 | end if; |
---|
| 2598 | end process proc_op_mem_22_20; |
---|
| 2599 | internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1"); |
---|
| 2600 | op_mem_22_20_push_front_pop_back_en <= '0'; |
---|
| 2601 | op <= boolean_to_vector(internal_ip_12_1_bitnot); |
---|
| 2602 | end behavior; |
---|
| 2603 | |
---|
| 2604 | |
---|
| 2605 | ------------------------------------------------------------------- |
---|
| 2606 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 2607 | -- |
---|
| 2608 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 2609 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 2610 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 2611 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 2612 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 2613 | -- this text/file solely for design, simulation, implementation and |
---|
| 2614 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 2615 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 2616 | -- and immediately terminates your license unless covered by a separate |
---|
| 2617 | -- agreement. |
---|
| 2618 | -- |
---|
| 2619 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 2620 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 2621 | -- providing this design, code, or information as one possible |
---|
| 2622 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 2623 | -- making no representation that this implementation is free from any |
---|
| 2624 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 2625 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 2626 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 2627 | -- implementation, including but not limited to warranties of |
---|
| 2628 | -- merchantability or fitness for a particular purpose. |
---|
| 2629 | -- |
---|
| 2630 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 2631 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 2632 | -- |
---|
| 2633 | -- Any modifications that are made to the source code are done at the user's |
---|
| 2634 | -- sole risk and will be unsupported. |
---|
| 2635 | -- |
---|
| 2636 | -- This copyright and support notice must be retained as part of this |
---|
| 2637 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 2638 | -- reserved. |
---|
| 2639 | ------------------------------------------------------------------- |
---|
| 2640 | library IEEE; |
---|
| 2641 | use IEEE.std_logic_1164.all; |
---|
| 2642 | use work.conv_pkg.all; |
---|
| 2643 | entity xlregister is |
---|
| 2644 | generic (d_width : integer := 5; |
---|
| 2645 | init_value : bit_vector := b"00"); |
---|
| 2646 | port (d : in std_logic_vector (d_width-1 downto 0); |
---|
| 2647 | rst : in std_logic_vector(0 downto 0) := "0"; |
---|
| 2648 | en : in std_logic_vector(0 downto 0) := "1"; |
---|
| 2649 | ce : in std_logic; |
---|
| 2650 | clk : in std_logic; |
---|
| 2651 | q : out std_logic_vector (d_width-1 downto 0)); |
---|
| 2652 | end xlregister; |
---|
| 2653 | architecture behavior of xlregister is |
---|
| 2654 | component synth_reg_w_init |
---|
| 2655 | generic (width : integer; |
---|
| 2656 | init_index : integer; |
---|
| 2657 | init_value : bit_vector; |
---|
| 2658 | latency : integer); |
---|
| 2659 | port (i : in std_logic_vector(width-1 downto 0); |
---|
| 2660 | ce : in std_logic; |
---|
| 2661 | clr : in std_logic; |
---|
| 2662 | clk : in std_logic; |
---|
| 2663 | o : out std_logic_vector(width-1 downto 0)); |
---|
| 2664 | end component; |
---|
| 2665 | -- synopsys translate_off |
---|
| 2666 | signal real_d, real_q : real; |
---|
| 2667 | -- synopsys translate_on |
---|
| 2668 | signal internal_clr : std_logic; |
---|
| 2669 | signal internal_ce : std_logic; |
---|
| 2670 | begin |
---|
| 2671 | internal_clr <= rst(0) and ce; |
---|
| 2672 | internal_ce <= en(0) and ce; |
---|
| 2673 | synth_reg_inst : synth_reg_w_init |
---|
| 2674 | generic map (width => d_width, |
---|
| 2675 | init_index => 2, |
---|
| 2676 | init_value => init_value, |
---|
| 2677 | latency => 1) |
---|
| 2678 | port map (i => d, |
---|
| 2679 | ce => internal_ce, |
---|
| 2680 | clr => internal_clr, |
---|
| 2681 | clk => clk, |
---|
| 2682 | o => q); |
---|
| 2683 | end architecture behavior; |
---|
| 2684 | |
---|
| 2685 | ------------------------------------------------------------------- |
---|
| 2686 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 2687 | -- |
---|
| 2688 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 2689 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 2690 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 2691 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 2692 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 2693 | -- this text/file solely for design, simulation, implementation and |
---|
| 2694 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 2695 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 2696 | -- and immediately terminates your license unless covered by a separate |
---|
| 2697 | -- agreement. |
---|
| 2698 | -- |
---|
| 2699 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 2700 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 2701 | -- providing this design, code, or information as one possible |
---|
| 2702 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 2703 | -- making no representation that this implementation is free from any |
---|
| 2704 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 2705 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 2706 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 2707 | -- implementation, including but not limited to warranties of |
---|
| 2708 | -- merchantability or fitness for a particular purpose. |
---|
| 2709 | -- |
---|
| 2710 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 2711 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 2712 | -- |
---|
| 2713 | -- Any modifications that are made to the source code are done at the user's |
---|
| 2714 | -- sole risk and will be unsupported. |
---|
| 2715 | -- |
---|
| 2716 | -- This copyright and support notice must be retained as part of this |
---|
| 2717 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 2718 | -- reserved. |
---|
| 2719 | ------------------------------------------------------------------- |
---|
| 2720 | library IEEE; |
---|
| 2721 | use IEEE.std_logic_1164.all; |
---|
| 2722 | use work.conv_pkg.all; |
---|
| 2723 | entity xldelay is |
---|
| 2724 | generic(width : integer := -1; |
---|
| 2725 | latency : integer := -1; |
---|
| 2726 | reg_retiming : integer := 0); |
---|
| 2727 | port(d : in std_logic_vector (width-1 downto 0); |
---|
| 2728 | ce : in std_logic; |
---|
| 2729 | clk : in std_logic; |
---|
| 2730 | en : in std_logic; |
---|
| 2731 | q : out std_logic_vector (width-1 downto 0)); |
---|
| 2732 | end xldelay; |
---|
| 2733 | architecture behavior of xldelay is |
---|
| 2734 | component synth_reg |
---|
| 2735 | generic (width : integer; |
---|
| 2736 | latency : integer); |
---|
| 2737 | port (i : in std_logic_vector(width-1 downto 0); |
---|
| 2738 | ce : in std_logic; |
---|
| 2739 | clr : in std_logic; |
---|
| 2740 | clk : in std_logic; |
---|
| 2741 | o : out std_logic_vector(width-1 downto 0)); |
---|
| 2742 | end component; |
---|
| 2743 | component synth_reg_reg |
---|
| 2744 | generic (width : integer; |
---|
| 2745 | latency : integer); |
---|
| 2746 | port (i : in std_logic_vector(width-1 downto 0); |
---|
| 2747 | ce : in std_logic; |
---|
| 2748 | clr : in std_logic; |
---|
| 2749 | clk : in std_logic; |
---|
| 2750 | o : out std_logic_vector(width-1 downto 0)); |
---|
| 2751 | end component; |
---|
| 2752 | signal internal_ce : std_logic; |
---|
| 2753 | begin |
---|
| 2754 | internal_ce <= ce and en; |
---|
| 2755 | srl_delay: if (reg_retiming = 0) or (latency < 1) generate |
---|
| 2756 | synth_reg_srl_inst : synth_reg |
---|
| 2757 | generic map ( |
---|
| 2758 | width => width, |
---|
| 2759 | latency => latency) |
---|
| 2760 | port map ( |
---|
| 2761 | i => d, |
---|
| 2762 | ce => internal_ce, |
---|
| 2763 | clr => '0', |
---|
| 2764 | clk => clk, |
---|
| 2765 | o => q); |
---|
| 2766 | end generate srl_delay; |
---|
| 2767 | reg_delay: if (reg_retiming = 1) and (latency >= 1) generate |
---|
| 2768 | synth_reg_reg_inst : synth_reg_reg |
---|
| 2769 | generic map ( |
---|
| 2770 | width => width, |
---|
| 2771 | latency => latency) |
---|
| 2772 | port map ( |
---|
| 2773 | i => d, |
---|
| 2774 | ce => internal_ce, |
---|
| 2775 | clr => '0', |
---|
| 2776 | clk => clk, |
---|
| 2777 | o => q); |
---|
| 2778 | end generate reg_delay; |
---|
| 2779 | end architecture behavior; |
---|
| 2780 | library IEEE; |
---|
| 2781 | use IEEE.std_logic_1164.all; |
---|
| 2782 | use IEEE.numeric_std.all; |
---|
| 2783 | use work.conv_pkg.all; |
---|
| 2784 | |
---|
| 2785 | entity logical_80f90b97d0 is |
---|
| 2786 | port ( |
---|
| 2787 | d0 : in std_logic_vector((1 - 1) downto 0); |
---|
| 2788 | d1 : in std_logic_vector((1 - 1) downto 0); |
---|
| 2789 | y : out std_logic_vector((1 - 1) downto 0); |
---|
| 2790 | clk : in std_logic; |
---|
| 2791 | ce : in std_logic; |
---|
| 2792 | clr : in std_logic); |
---|
| 2793 | end logical_80f90b97d0; |
---|
| 2794 | |
---|
| 2795 | |
---|
| 2796 | architecture behavior of logical_80f90b97d0 is |
---|
| 2797 | signal d0_1_24: std_logic; |
---|
| 2798 | signal d1_1_27: std_logic; |
---|
| 2799 | signal fully_2_1_bit: std_logic; |
---|
| 2800 | begin |
---|
| 2801 | d0_1_24 <= d0(0); |
---|
| 2802 | d1_1_27 <= d1(0); |
---|
| 2803 | fully_2_1_bit <= d0_1_24 and d1_1_27; |
---|
| 2804 | y <= std_logic_to_vector(fully_2_1_bit); |
---|
| 2805 | end behavior; |
---|
| 2806 | |
---|
| 2807 | |
---|
| 2808 | ------------------------------------------------------------------- |
---|
| 2809 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 2810 | -- |
---|
| 2811 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 2812 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 2813 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 2814 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 2815 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 2816 | -- this text/file solely for design, simulation, implementation and |
---|
| 2817 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 2818 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 2819 | -- and immediately terminates your license unless covered by a separate |
---|
| 2820 | -- agreement. |
---|
| 2821 | -- |
---|
| 2822 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 2823 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 2824 | -- providing this design, code, or information as one possible |
---|
| 2825 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 2826 | -- making no representation that this implementation is free from any |
---|
| 2827 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 2828 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 2829 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 2830 | -- implementation, including but not limited to warranties of |
---|
| 2831 | -- merchantability or fitness for a particular purpose. |
---|
| 2832 | -- |
---|
| 2833 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 2834 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 2835 | -- |
---|
| 2836 | -- Any modifications that are made to the source code are done at the user's |
---|
| 2837 | -- sole risk and will be unsupported. |
---|
| 2838 | -- |
---|
| 2839 | -- This copyright and support notice must be retained as part of this |
---|
| 2840 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 2841 | -- reserved. |
---|
| 2842 | ------------------------------------------------------------------- |
---|
| 2843 | -- synopsys translate_off |
---|
| 2844 | library XilinxCoreLib; |
---|
| 2845 | -- synopsys translate_on |
---|
| 2846 | library IEEE; |
---|
| 2847 | use IEEE.std_logic_1164.all; |
---|
| 2848 | use IEEE.std_logic_arith.all; |
---|
| 2849 | use work.conv_pkg.all; |
---|
| 2850 | entity xladdsub is |
---|
| 2851 | generic ( |
---|
| 2852 | core_name0: string := ""; |
---|
| 2853 | a_width: integer := 16; |
---|
| 2854 | a_bin_pt: integer := 4; |
---|
| 2855 | a_arith: integer := xlUnsigned; |
---|
| 2856 | c_in_width: integer := 16; |
---|
| 2857 | c_in_bin_pt: integer := 4; |
---|
| 2858 | c_in_arith: integer := xlUnsigned; |
---|
| 2859 | c_out_width: integer := 16; |
---|
| 2860 | c_out_bin_pt: integer := 4; |
---|
| 2861 | c_out_arith: integer := xlUnsigned; |
---|
| 2862 | b_width: integer := 8; |
---|
| 2863 | b_bin_pt: integer := 2; |
---|
| 2864 | b_arith: integer := xlUnsigned; |
---|
| 2865 | s_width: integer := 17; |
---|
| 2866 | s_bin_pt: integer := 4; |
---|
| 2867 | s_arith: integer := xlUnsigned; |
---|
| 2868 | rst_width: integer := 1; |
---|
| 2869 | rst_bin_pt: integer := 0; |
---|
| 2870 | rst_arith: integer := xlUnsigned; |
---|
| 2871 | en_width: integer := 1; |
---|
| 2872 | en_bin_pt: integer := 0; |
---|
| 2873 | en_arith: integer := xlUnsigned; |
---|
| 2874 | full_s_width: integer := 17; |
---|
| 2875 | full_s_arith: integer := xlUnsigned; |
---|
| 2876 | mode: integer := xlAddMode; |
---|
| 2877 | extra_registers: integer := 0; |
---|
| 2878 | latency: integer := 0; |
---|
| 2879 | quantization: integer := xlTruncate; |
---|
| 2880 | overflow: integer := xlWrap; |
---|
| 2881 | c_latency: integer := 0; |
---|
| 2882 | c_output_width: integer := 17; |
---|
| 2883 | c_has_q : integer := 1; |
---|
| 2884 | c_has_s : integer := 0; |
---|
| 2885 | c_has_c_out : integer := 0; |
---|
| 2886 | c_has_q_c_out : integer := 0; |
---|
| 2887 | c_has_b_out : integer := 0; |
---|
| 2888 | c_has_q_b_out : integer := 0; |
---|
| 2889 | c_has_q_ovfl : integer := 0; |
---|
| 2890 | c_has_ovfl : integer := 0 |
---|
| 2891 | ); |
---|
| 2892 | port ( |
---|
| 2893 | a: in std_logic_vector(a_width - 1 downto 0); |
---|
| 2894 | b: in std_logic_vector(b_width - 1 downto 0); |
---|
| 2895 | c_in : in std_logic_vector (0 downto 0) := "0"; |
---|
| 2896 | ce: in std_logic; |
---|
| 2897 | clr: in std_logic := '0'; |
---|
| 2898 | clk: in std_logic; |
---|
| 2899 | rst: in std_logic_vector(rst_width - 1 downto 0) := "0"; |
---|
| 2900 | en: in std_logic_vector(en_width - 1 downto 0) := "1"; |
---|
| 2901 | c_out : out std_logic_vector (0 downto 0); |
---|
| 2902 | s: out std_logic_vector(s_width - 1 downto 0) |
---|
| 2903 | ); |
---|
| 2904 | end xladdsub ; |
---|
| 2905 | architecture behavior of xladdsub is |
---|
| 2906 | |
---|
| 2907 | component synth_reg |
---|
| 2908 | generic ( |
---|
| 2909 | width: integer := 16; |
---|
| 2910 | latency: integer := 5 |
---|
| 2911 | ); |
---|
| 2912 | port ( |
---|
| 2913 | i: in std_logic_vector(width - 1 downto 0); |
---|
| 2914 | ce: in std_logic; |
---|
| 2915 | clr: in std_logic; |
---|
| 2916 | clk: in std_logic; |
---|
| 2917 | o: out std_logic_vector(width - 1 downto 0) |
---|
| 2918 | ); |
---|
| 2919 | end component; |
---|
| 2920 | function format_input(inp: std_logic_vector; old_width, delta, new_arith, |
---|
| 2921 | new_width: integer) |
---|
| 2922 | return std_logic_vector |
---|
| 2923 | is |
---|
| 2924 | variable vec: std_logic_vector(old_width-1 downto 0); |
---|
| 2925 | variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0); |
---|
| 2926 | variable result: std_logic_vector(new_width-1 downto 0); |
---|
| 2927 | begin |
---|
| 2928 | vec := inp; |
---|
| 2929 | if delta > 0 then |
---|
| 2930 | padded_inp := pad_LSB(vec, old_width+delta); |
---|
| 2931 | result := extend_MSB(padded_inp, new_width, new_arith); |
---|
| 2932 | else |
---|
| 2933 | result := extend_MSB(vec, new_width, new_arith); |
---|
| 2934 | end if; |
---|
| 2935 | return result; |
---|
| 2936 | end; |
---|
| 2937 | constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt); |
---|
| 2938 | constant full_a_width: integer := full_s_width; |
---|
| 2939 | constant full_b_width: integer := full_s_width; |
---|
| 2940 | signal full_a: std_logic_vector(full_a_width - 1 downto 0); |
---|
| 2941 | signal full_b: std_logic_vector(full_b_width - 1 downto 0); |
---|
| 2942 | signal core_s: std_logic_vector(full_s_width - 1 downto 0); |
---|
| 2943 | signal conv_s: std_logic_vector(s_width - 1 downto 0); |
---|
| 2944 | signal temp_cout : std_logic; |
---|
| 2945 | signal internal_clr: std_logic; |
---|
| 2946 | signal internal_ce: std_logic; |
---|
| 2947 | signal extra_reg_ce: std_logic; |
---|
| 2948 | signal override: std_logic; |
---|
| 2949 | signal logic1: std_logic_vector(0 downto 0); |
---|
| 2950 | component adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e |
---|
| 2951 | port ( |
---|
| 2952 | a: in std_logic_vector( 33 - 1 downto 0); |
---|
| 2953 | s: out std_logic_vector(c_output_width - 1 downto 0); |
---|
| 2954 | b: in std_logic_vector(33 - 1 downto 0) |
---|
| 2955 | ); |
---|
| 2956 | end component; |
---|
| 2957 | attribute syn_black_box of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e: |
---|
| 2958 | component is true; |
---|
| 2959 | attribute fpga_dont_touch of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e: |
---|
| 2960 | component is "true"; |
---|
| 2961 | attribute box_type of adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e: |
---|
| 2962 | component is "black_box"; |
---|
| 2963 | begin |
---|
| 2964 | internal_clr <= (clr or (rst(0))) and ce; |
---|
| 2965 | internal_ce <= ce and en(0); |
---|
| 2966 | logic1(0) <= '1'; |
---|
| 2967 | addsub_process: process(a, b, core_s) |
---|
| 2968 | begin |
---|
| 2969 | full_a <= format_input(a, a_width, b_bin_pt - a_bin_pt, a_arith, |
---|
| 2970 | full_a_width); |
---|
| 2971 | full_b <= format_input(b, b_width, a_bin_pt - b_bin_pt, b_arith, |
---|
| 2972 | full_b_width); |
---|
| 2973 | conv_s <= convert_type(core_s, full_s_width, full_s_bin_pt, full_s_arith, |
---|
| 2974 | s_width, s_bin_pt, s_arith, quantization, overflow); |
---|
| 2975 | end process addsub_process; |
---|
| 2976 | |
---|
| 2977 | comp0: if ((core_name0 = "adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e")) generate |
---|
| 2978 | core_instance0: adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e |
---|
| 2979 | port map ( |
---|
| 2980 | a => full_a, |
---|
| 2981 | s => core_s, |
---|
| 2982 | b => full_b |
---|
| 2983 | ); |
---|
| 2984 | end generate; |
---|
| 2985 | latency_test: if (extra_registers > 0) generate |
---|
| 2986 | override_test: if (c_latency > 1) generate |
---|
| 2987 | override_pipe: synth_reg |
---|
| 2988 | generic map ( |
---|
| 2989 | width => 1, |
---|
| 2990 | latency => c_latency) |
---|
| 2991 | port map ( |
---|
| 2992 | i => logic1, |
---|
| 2993 | ce => internal_ce, |
---|
| 2994 | clr => internal_clr, |
---|
| 2995 | clk => clk, |
---|
| 2996 | o(0) => override); |
---|
| 2997 | extra_reg_ce <= ce and en(0) and override; |
---|
| 2998 | end generate override_test; |
---|
| 2999 | no_override: if (c_latency = 0) or (c_latency = 1) generate |
---|
| 3000 | extra_reg_ce <= ce and en(0); |
---|
| 3001 | end generate no_override; |
---|
| 3002 | extra_reg: synth_reg |
---|
| 3003 | generic map ( |
---|
| 3004 | width => s_width, |
---|
| 3005 | latency => extra_registers |
---|
| 3006 | ) |
---|
| 3007 | port map ( |
---|
| 3008 | i => conv_s, |
---|
| 3009 | ce => extra_reg_ce, |
---|
| 3010 | clr => internal_clr, |
---|
| 3011 | clk => clk, |
---|
| 3012 | o => s |
---|
| 3013 | ); |
---|
| 3014 | cout_test : if((c_has_c_out = 1) or |
---|
| 3015 | (c_has_b_out = 1) or |
---|
| 3016 | (c_has_q_c_out = 1) or |
---|
| 3017 | (c_has_q_b_out = 1)) generate |
---|
| 3018 | c_out_extra_reg: synth_reg |
---|
| 3019 | generic map ( |
---|
| 3020 | width => 1, |
---|
| 3021 | latency => extra_registers |
---|
| 3022 | ) |
---|
| 3023 | port map ( |
---|
| 3024 | i(0) => temp_cout, |
---|
| 3025 | ce => extra_reg_ce, |
---|
| 3026 | clr => internal_clr, |
---|
| 3027 | clk => clk, |
---|
| 3028 | o => c_out |
---|
| 3029 | ); |
---|
| 3030 | end generate cout_test; |
---|
| 3031 | end generate; |
---|
| 3032 | latency_s: if ((latency = 0) or (extra_registers = 0)) generate |
---|
| 3033 | s <= conv_s; |
---|
| 3034 | end generate latency_s; |
---|
| 3035 | latency0: if ( ((latency = 0) or (extra_registers = 0)) and |
---|
| 3036 | ((c_has_b_out = 1) or |
---|
| 3037 | (c_has_q_c_out = 1) or |
---|
| 3038 | (c_has_c_out = 1) or |
---|
| 3039 | (c_has_q_b_out = 1))) generate |
---|
| 3040 | c_out(0) <= temp_cout; |
---|
| 3041 | end generate latency0; |
---|
| 3042 | tie_dangling_cout: if ((c_has_c_out = 0) and |
---|
| 3043 | (c_has_b_out = 0) and |
---|
| 3044 | (c_has_q_c_out = 0) and |
---|
| 3045 | (c_has_q_b_out = 0)) generate |
---|
| 3046 | c_out <= "0"; |
---|
| 3047 | end generate tie_dangling_cout; |
---|
| 3048 | end architecture behavior; |
---|
| 3049 | library IEEE; |
---|
| 3050 | use IEEE.std_logic_1164.all; |
---|
| 3051 | use IEEE.numeric_std.all; |
---|
| 3052 | use work.conv_pkg.all; |
---|
| 3053 | |
---|
| 3054 | entity constant_6293007044 is |
---|
| 3055 | port ( |
---|
| 3056 | op : out std_logic_vector((1 - 1) downto 0); |
---|
| 3057 | clk : in std_logic; |
---|
| 3058 | ce : in std_logic; |
---|
| 3059 | clr : in std_logic); |
---|
| 3060 | end constant_6293007044; |
---|
| 3061 | |
---|
| 3062 | |
---|
| 3063 | architecture behavior of constant_6293007044 is |
---|
| 3064 | begin |
---|
| 3065 | op <= "1"; |
---|
| 3066 | end behavior; |
---|
| 3067 | |
---|
| 3068 | |
---|
| 3069 | ------------------------------------------------------------------- |
---|
| 3070 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 3071 | -- |
---|
| 3072 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 3073 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 3074 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 3075 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 3076 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 3077 | -- this text/file solely for design, simulation, implementation and |
---|
| 3078 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 3079 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 3080 | -- and immediately terminates your license unless covered by a separate |
---|
| 3081 | -- agreement. |
---|
| 3082 | -- |
---|
| 3083 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 3084 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 3085 | -- providing this design, code, or information as one possible |
---|
| 3086 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 3087 | -- making no representation that this implementation is free from any |
---|
| 3088 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 3089 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 3090 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 3091 | -- implementation, including but not limited to warranties of |
---|
| 3092 | -- merchantability or fitness for a particular purpose. |
---|
| 3093 | -- |
---|
| 3094 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 3095 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 3096 | -- |
---|
| 3097 | -- Any modifications that are made to the source code are done at the user's |
---|
| 3098 | -- sole risk and will be unsupported. |
---|
| 3099 | -- |
---|
| 3100 | -- This copyright and support notice must be retained as part of this |
---|
| 3101 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 3102 | -- reserved. |
---|
| 3103 | ------------------------------------------------------------------- |
---|
| 3104 | library IEEE; |
---|
| 3105 | use IEEE.std_logic_1164.all; |
---|
| 3106 | use work.conv_pkg.all; |
---|
| 3107 | entity convert_func_call is |
---|
| 3108 | generic ( |
---|
| 3109 | din_width : integer := 16; |
---|
| 3110 | din_bin_pt : integer := 4; |
---|
| 3111 | din_arith : integer := xlUnsigned; |
---|
| 3112 | dout_width : integer := 8; |
---|
| 3113 | dout_bin_pt : integer := 2; |
---|
| 3114 | dout_arith : integer := xlUnsigned; |
---|
| 3115 | quantization : integer := xlTruncate; |
---|
| 3116 | overflow : integer := xlWrap); |
---|
| 3117 | port ( |
---|
| 3118 | din : in std_logic_vector (din_width-1 downto 0); |
---|
| 3119 | result : out std_logic_vector (dout_width-1 downto 0)); |
---|
| 3120 | end convert_func_call; |
---|
| 3121 | architecture behavior of convert_func_call is |
---|
| 3122 | begin |
---|
| 3123 | result <= convert_type(din, din_width, din_bin_pt, din_arith, |
---|
| 3124 | dout_width, dout_bin_pt, dout_arith, |
---|
| 3125 | quantization, overflow); |
---|
| 3126 | end behavior; |
---|
| 3127 | library IEEE; |
---|
| 3128 | use IEEE.std_logic_1164.all; |
---|
| 3129 | use work.conv_pkg.all; |
---|
| 3130 | entity xlconvert is |
---|
| 3131 | generic ( |
---|
| 3132 | din_width : integer := 16; |
---|
| 3133 | din_bin_pt : integer := 4; |
---|
| 3134 | din_arith : integer := xlUnsigned; |
---|
| 3135 | dout_width : integer := 8; |
---|
| 3136 | dout_bin_pt : integer := 2; |
---|
| 3137 | dout_arith : integer := xlUnsigned; |
---|
| 3138 | bool_conversion : integer :=0; |
---|
| 3139 | latency : integer := 0; |
---|
| 3140 | quantization : integer := xlTruncate; |
---|
| 3141 | overflow : integer := xlWrap); |
---|
| 3142 | port ( |
---|
| 3143 | din : in std_logic_vector (din_width-1 downto 0); |
---|
| 3144 | ce : in std_logic; |
---|
| 3145 | clr : in std_logic; |
---|
| 3146 | clk : in std_logic; |
---|
| 3147 | dout : out std_logic_vector (dout_width-1 downto 0)); |
---|
| 3148 | end xlconvert; |
---|
| 3149 | architecture behavior of xlconvert is |
---|
| 3150 | component synth_reg |
---|
| 3151 | generic (width : integer; |
---|
| 3152 | latency : integer); |
---|
| 3153 | port (i : in std_logic_vector(width-1 downto 0); |
---|
| 3154 | ce : in std_logic; |
---|
| 3155 | clr : in std_logic; |
---|
| 3156 | clk : in std_logic; |
---|
| 3157 | o : out std_logic_vector(width-1 downto 0)); |
---|
| 3158 | end component; |
---|
| 3159 | component convert_func_call |
---|
| 3160 | generic ( |
---|
| 3161 | din_width : integer := 16; |
---|
| 3162 | din_bin_pt : integer := 4; |
---|
| 3163 | din_arith : integer := xlUnsigned; |
---|
| 3164 | dout_width : integer := 8; |
---|
| 3165 | dout_bin_pt : integer := 2; |
---|
| 3166 | dout_arith : integer := xlUnsigned; |
---|
| 3167 | quantization : integer := xlTruncate; |
---|
| 3168 | overflow : integer := xlWrap); |
---|
| 3169 | port ( |
---|
| 3170 | din : in std_logic_vector (din_width-1 downto 0); |
---|
| 3171 | result : out std_logic_vector (dout_width-1 downto 0)); |
---|
| 3172 | end component; |
---|
| 3173 | -- synopsys translate_off |
---|
| 3174 | signal real_din, real_dout : real; |
---|
| 3175 | -- synopsys translate_on |
---|
| 3176 | signal result : std_logic_vector(dout_width-1 downto 0); |
---|
| 3177 | begin |
---|
| 3178 | -- synopsys translate_off |
---|
| 3179 | -- synopsys translate_on |
---|
| 3180 | bool_conversion_generate : if (bool_conversion = 1) |
---|
| 3181 | generate |
---|
| 3182 | result <= din; |
---|
| 3183 | end generate; |
---|
| 3184 | std_conversion_generate : if (bool_conversion = 0) |
---|
| 3185 | generate |
---|
| 3186 | convert : convert_func_call |
---|
| 3187 | generic map ( |
---|
| 3188 | din_width => din_width, |
---|
| 3189 | din_bin_pt => din_bin_pt, |
---|
| 3190 | din_arith => din_arith, |
---|
| 3191 | dout_width => dout_width, |
---|
| 3192 | dout_bin_pt => dout_bin_pt, |
---|
| 3193 | dout_arith => dout_arith, |
---|
| 3194 | quantization => quantization, |
---|
| 3195 | overflow => overflow) |
---|
| 3196 | port map ( |
---|
| 3197 | din => din, |
---|
| 3198 | result => result); |
---|
| 3199 | end generate; |
---|
| 3200 | latency_test : if (latency > 0) |
---|
| 3201 | generate |
---|
| 3202 | reg : synth_reg |
---|
| 3203 | generic map ( width => dout_width, |
---|
| 3204 | latency => latency) |
---|
| 3205 | port map (i => result, |
---|
| 3206 | ce => ce, |
---|
| 3207 | clr => clr, |
---|
| 3208 | clk => clk, |
---|
| 3209 | o => dout); |
---|
| 3210 | end generate; |
---|
| 3211 | latency0 : if (latency = 0) |
---|
| 3212 | generate |
---|
| 3213 | dout <= result; |
---|
| 3214 | end generate latency0; |
---|
| 3215 | end behavior; |
---|
| 3216 | |
---|
| 3217 | ------------------------------------------------------------------- |
---|
| 3218 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 3219 | -- |
---|
| 3220 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 3221 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 3222 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 3223 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 3224 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 3225 | -- this text/file solely for design, simulation, implementation and |
---|
| 3226 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 3227 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 3228 | -- and immediately terminates your license unless covered by a separate |
---|
| 3229 | -- agreement. |
---|
| 3230 | -- |
---|
| 3231 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 3232 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 3233 | -- providing this design, code, or information as one possible |
---|
| 3234 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 3235 | -- making no representation that this implementation is free from any |
---|
| 3236 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 3237 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 3238 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 3239 | -- implementation, including but not limited to warranties of |
---|
| 3240 | -- merchantability or fitness for a particular purpose. |
---|
| 3241 | -- |
---|
| 3242 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 3243 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 3244 | -- |
---|
| 3245 | -- Any modifications that are made to the source code are done at the user's |
---|
| 3246 | -- sole risk and will be unsupported. |
---|
| 3247 | -- |
---|
| 3248 | -- This copyright and support notice must be retained as part of this |
---|
| 3249 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 3250 | -- reserved. |
---|
| 3251 | ------------------------------------------------------------------- |
---|
| 3252 | -- synopsys translate_off |
---|
| 3253 | library XilinxCoreLib; |
---|
| 3254 | -- synopsys translate_on |
---|
| 3255 | library IEEE; |
---|
| 3256 | use IEEE.std_logic_1164.all; |
---|
| 3257 | use work.conv_pkg.all; |
---|
| 3258 | entity xlcounter_free is |
---|
| 3259 | generic ( |
---|
| 3260 | core_name0: string := ""; |
---|
| 3261 | op_width: integer := 5; |
---|
| 3262 | op_arith: integer := xlSigned |
---|
| 3263 | ); |
---|
| 3264 | port ( |
---|
| 3265 | ce: in std_logic; |
---|
| 3266 | clr: in std_logic; |
---|
| 3267 | clk: in std_logic; |
---|
| 3268 | op: out std_logic_vector(op_width - 1 downto 0); |
---|
| 3269 | up: in std_logic_vector(0 downto 0) := (others => '0'); |
---|
| 3270 | load: in std_logic_vector(0 downto 0) := (others => '0'); |
---|
| 3271 | din: in std_logic_vector(op_width - 1 downto 0) := (others => '0'); |
---|
| 3272 | en: in std_logic_vector(0 downto 0); |
---|
| 3273 | rst: in std_logic_vector(0 downto 0) |
---|
| 3274 | ); |
---|
| 3275 | end xlcounter_free ; |
---|
| 3276 | architecture behavior of xlcounter_free is |
---|
| 3277 | component binary_counter_virtex2p_7_0_b57302a6bcbb6876 |
---|
| 3278 | port ( |
---|
| 3279 | clk: in std_logic; |
---|
| 3280 | ce: in std_logic; |
---|
| 3281 | sinit: in std_logic; |
---|
| 3282 | q: out std_logic_vector(op_width - 1 downto 0) |
---|
| 3283 | ); |
---|
| 3284 | end component; |
---|
| 3285 | attribute syn_black_box of binary_counter_virtex2p_7_0_b57302a6bcbb6876: |
---|
| 3286 | component is true; |
---|
| 3287 | attribute fpga_dont_touch of binary_counter_virtex2p_7_0_b57302a6bcbb6876: |
---|
| 3288 | component is "true"; |
---|
| 3289 | attribute box_type of binary_counter_virtex2p_7_0_b57302a6bcbb6876: |
---|
| 3290 | component is "black_box"; |
---|
| 3291 | -- synopsys translate_off |
---|
| 3292 | constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0'); |
---|
| 3293 | constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1'); |
---|
| 3294 | constant zeroStr: string(1 to op_width) := |
---|
| 3295 | std_logic_vector_to_bin_string(zeroVec); |
---|
| 3296 | constant oneStr: string(1 to op_width) := |
---|
| 3297 | std_logic_vector_to_bin_string(oneVec); |
---|
| 3298 | -- synopsys translate_on |
---|
| 3299 | signal core_sinit: std_logic; |
---|
| 3300 | signal core_ce: std_logic; |
---|
| 3301 | signal op_net: std_logic_vector(op_width - 1 downto 0); |
---|
| 3302 | begin |
---|
| 3303 | core_ce <= ce and en(0); |
---|
| 3304 | core_sinit <= (clr or rst(0)) and ce; |
---|
| 3305 | op <= op_net; |
---|
| 3306 | comp0: if ((core_name0 = "binary_counter_virtex2p_7_0_b57302a6bcbb6876")) generate |
---|
| 3307 | core_instance0: binary_counter_virtex2p_7_0_b57302a6bcbb6876 |
---|
| 3308 | port map ( |
---|
| 3309 | clk => clk, |
---|
| 3310 | ce => core_ce, |
---|
| 3311 | sinit => core_sinit, |
---|
| 3312 | q => op_net |
---|
| 3313 | ); |
---|
| 3314 | end generate; |
---|
| 3315 | end behavior; |
---|
| 3316 | library IEEE; |
---|
| 3317 | use IEEE.std_logic_1164.all; |
---|
| 3318 | use IEEE.numeric_std.all; |
---|
| 3319 | use work.conv_pkg.all; |
---|
| 3320 | |
---|
| 3321 | entity logical_6cb8f0ce02 is |
---|
| 3322 | port ( |
---|
| 3323 | d0 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3324 | d1 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3325 | d2 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3326 | y : out std_logic_vector((1 - 1) downto 0); |
---|
| 3327 | clk : in std_logic; |
---|
| 3328 | ce : in std_logic; |
---|
| 3329 | clr : in std_logic); |
---|
| 3330 | end logical_6cb8f0ce02; |
---|
| 3331 | |
---|
| 3332 | |
---|
| 3333 | architecture behavior of logical_6cb8f0ce02 is |
---|
| 3334 | signal d0_1_24: std_logic; |
---|
| 3335 | signal d1_1_27: std_logic; |
---|
| 3336 | signal d2_1_30: std_logic; |
---|
| 3337 | signal fully_2_1_bit: std_logic; |
---|
| 3338 | begin |
---|
| 3339 | d0_1_24 <= d0(0); |
---|
| 3340 | d1_1_27 <= d1(0); |
---|
| 3341 | d2_1_30 <= d2(0); |
---|
| 3342 | fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30; |
---|
| 3343 | y <= std_logic_to_vector(fully_2_1_bit); |
---|
| 3344 | end behavior; |
---|
| 3345 | |
---|
| 3346 | library IEEE; |
---|
| 3347 | use IEEE.std_logic_1164.all; |
---|
| 3348 | use IEEE.numeric_std.all; |
---|
| 3349 | use work.conv_pkg.all; |
---|
| 3350 | |
---|
| 3351 | entity logical_aacf6e1b0e is |
---|
| 3352 | port ( |
---|
| 3353 | d0 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3354 | d1 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3355 | y : out std_logic_vector((1 - 1) downto 0); |
---|
| 3356 | clk : in std_logic; |
---|
| 3357 | ce : in std_logic; |
---|
| 3358 | clr : in std_logic); |
---|
| 3359 | end logical_aacf6e1b0e; |
---|
| 3360 | |
---|
| 3361 | |
---|
| 3362 | architecture behavior of logical_aacf6e1b0e is |
---|
| 3363 | signal d0_1_24: std_logic; |
---|
| 3364 | signal d1_1_27: std_logic; |
---|
| 3365 | signal fully_2_1_bit: std_logic; |
---|
| 3366 | begin |
---|
| 3367 | d0_1_24 <= d0(0); |
---|
| 3368 | d1_1_27 <= d1(0); |
---|
| 3369 | fully_2_1_bit <= d0_1_24 or d1_1_27; |
---|
| 3370 | y <= std_logic_to_vector(fully_2_1_bit); |
---|
| 3371 | end behavior; |
---|
| 3372 | |
---|
| 3373 | library IEEE; |
---|
| 3374 | use IEEE.std_logic_1164.all; |
---|
| 3375 | use IEEE.numeric_std.all; |
---|
| 3376 | use work.conv_pkg.all; |
---|
| 3377 | |
---|
| 3378 | entity mux_112ed141f4 is |
---|
| 3379 | port ( |
---|
| 3380 | sel : in std_logic_vector((1 - 1) downto 0); |
---|
| 3381 | d0 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3382 | d1 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3383 | y : out std_logic_vector((1 - 1) downto 0); |
---|
| 3384 | clk : in std_logic; |
---|
| 3385 | ce : in std_logic; |
---|
| 3386 | clr : in std_logic); |
---|
| 3387 | end mux_112ed141f4; |
---|
| 3388 | |
---|
| 3389 | |
---|
| 3390 | architecture behavior of mux_112ed141f4 is |
---|
| 3391 | signal sel_1_20: std_logic; |
---|
| 3392 | signal d0_1_24: std_logic_vector((1 - 1) downto 0); |
---|
| 3393 | signal d1_1_27: std_logic_vector((1 - 1) downto 0); |
---|
| 3394 | signal sel_internal_2_1_convert: std_logic_vector((1 - 1) downto 0); |
---|
| 3395 | signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0); |
---|
| 3396 | begin |
---|
| 3397 | sel_1_20 <= sel(0); |
---|
| 3398 | d0_1_24 <= d0; |
---|
| 3399 | d1_1_27 <= d1; |
---|
| 3400 | sel_internal_2_1_convert <= cast(std_logic_to_vector(sel_1_20), 0, 1, 0, xlUnsigned); |
---|
| 3401 | proc_switch_6_1: process (d0_1_24, d1_1_27, sel_internal_2_1_convert) |
---|
| 3402 | is |
---|
| 3403 | begin |
---|
| 3404 | case sel_internal_2_1_convert is |
---|
| 3405 | when "0" => |
---|
| 3406 | unregy_join_6_1 <= d0_1_24; |
---|
| 3407 | when others => |
---|
| 3408 | unregy_join_6_1 <= d1_1_27; |
---|
| 3409 | end case; |
---|
| 3410 | end process proc_switch_6_1; |
---|
| 3411 | y <= unregy_join_6_1; |
---|
| 3412 | end behavior; |
---|
| 3413 | |
---|
| 3414 | library IEEE; |
---|
| 3415 | use IEEE.std_logic_1164.all; |
---|
| 3416 | use IEEE.numeric_std.all; |
---|
| 3417 | use work.conv_pkg.all; |
---|
| 3418 | |
---|
| 3419 | entity relational_3ffd1d0a40 is |
---|
| 3420 | port ( |
---|
| 3421 | a : in std_logic_vector((32 - 1) downto 0); |
---|
| 3422 | b : in std_logic_vector((32 - 1) downto 0); |
---|
| 3423 | op : out std_logic_vector((1 - 1) downto 0); |
---|
| 3424 | clk : in std_logic; |
---|
| 3425 | ce : in std_logic; |
---|
| 3426 | clr : in std_logic); |
---|
| 3427 | end relational_3ffd1d0a40; |
---|
| 3428 | |
---|
| 3429 | |
---|
| 3430 | architecture behavior of relational_3ffd1d0a40 is |
---|
| 3431 | signal a_1_31: unsigned((32 - 1) downto 0); |
---|
| 3432 | signal b_1_34: unsigned((32 - 1) downto 0); |
---|
| 3433 | signal result_12_3_rel: boolean; |
---|
| 3434 | begin |
---|
| 3435 | a_1_31 <= std_logic_vector_to_unsigned(a); |
---|
| 3436 | b_1_34 <= std_logic_vector_to_unsigned(b); |
---|
| 3437 | result_12_3_rel <= a_1_31 = b_1_34; |
---|
| 3438 | op <= boolean_to_vector(result_12_3_rel); |
---|
| 3439 | end behavior; |
---|
| 3440 | |
---|
| 3441 | library IEEE; |
---|
| 3442 | use IEEE.std_logic_1164.all; |
---|
| 3443 | use IEEE.numeric_std.all; |
---|
| 3444 | use work.conv_pkg.all; |
---|
| 3445 | |
---|
| 3446 | entity relational_34fc311f5b is |
---|
| 3447 | port ( |
---|
| 3448 | a : in std_logic_vector((32 - 1) downto 0); |
---|
| 3449 | b : in std_logic_vector((32 - 1) downto 0); |
---|
| 3450 | op : out std_logic_vector((1 - 1) downto 0); |
---|
| 3451 | clk : in std_logic; |
---|
| 3452 | ce : in std_logic; |
---|
| 3453 | clr : in std_logic); |
---|
| 3454 | end relational_34fc311f5b; |
---|
| 3455 | |
---|
| 3456 | |
---|
| 3457 | architecture behavior of relational_34fc311f5b is |
---|
| 3458 | signal a_1_31: unsigned((32 - 1) downto 0); |
---|
| 3459 | signal b_1_34: unsigned((32 - 1) downto 0); |
---|
| 3460 | type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean; |
---|
| 3461 | signal op_mem_32_22: array_type_op_mem_32_22 := ( |
---|
| 3462 | 0 => false); |
---|
| 3463 | signal op_mem_32_22_front_din: boolean; |
---|
| 3464 | signal op_mem_32_22_back: boolean; |
---|
| 3465 | signal op_mem_32_22_push_front_pop_back_en: std_logic; |
---|
| 3466 | signal result_18_3_rel: boolean; |
---|
| 3467 | begin |
---|
| 3468 | a_1_31 <= std_logic_vector_to_unsigned(a); |
---|
| 3469 | b_1_34 <= std_logic_vector_to_unsigned(b); |
---|
| 3470 | op_mem_32_22_back <= op_mem_32_22(0); |
---|
| 3471 | proc_op_mem_32_22: process (clk) |
---|
| 3472 | is |
---|
| 3473 | variable i: integer; |
---|
| 3474 | begin |
---|
| 3475 | if (clk'event and (clk = '1')) then |
---|
| 3476 | if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then |
---|
| 3477 | op_mem_32_22(0) <= op_mem_32_22_front_din; |
---|
| 3478 | end if; |
---|
| 3479 | end if; |
---|
| 3480 | end process proc_op_mem_32_22; |
---|
| 3481 | result_18_3_rel <= a_1_31 > b_1_34; |
---|
| 3482 | op_mem_32_22_front_din <= result_18_3_rel; |
---|
| 3483 | op_mem_32_22_push_front_pop_back_en <= '1'; |
---|
| 3484 | op <= boolean_to_vector(op_mem_32_22_back); |
---|
| 3485 | end behavior; |
---|
| 3486 | |
---|
| 3487 | library IEEE; |
---|
| 3488 | use IEEE.std_logic_1164.all; |
---|
| 3489 | use IEEE.numeric_std.all; |
---|
| 3490 | use work.conv_pkg.all; |
---|
| 3491 | |
---|
| 3492 | entity constant_37567836aa is |
---|
| 3493 | port ( |
---|
| 3494 | op : out std_logic_vector((32 - 1) downto 0); |
---|
| 3495 | clk : in std_logic; |
---|
| 3496 | ce : in std_logic; |
---|
| 3497 | clr : in std_logic); |
---|
| 3498 | end constant_37567836aa; |
---|
| 3499 | |
---|
| 3500 | |
---|
| 3501 | architecture behavior of constant_37567836aa is |
---|
| 3502 | begin |
---|
| 3503 | op <= "00000000000000000000000000000000"; |
---|
| 3504 | end behavior; |
---|
| 3505 | |
---|
| 3506 | library IEEE; |
---|
| 3507 | use IEEE.std_logic_1164.all; |
---|
| 3508 | use IEEE.numeric_std.all; |
---|
| 3509 | use work.conv_pkg.all; |
---|
| 3510 | |
---|
| 3511 | entity concat_a1e126f11c is |
---|
| 3512 | port ( |
---|
| 3513 | in0 : in std_logic_vector((8 - 1) downto 0); |
---|
| 3514 | in1 : in std_logic_vector((8 - 1) downto 0); |
---|
| 3515 | in2 : in std_logic_vector((8 - 1) downto 0); |
---|
| 3516 | in3 : in std_logic_vector((8 - 1) downto 0); |
---|
| 3517 | y : out std_logic_vector((32 - 1) downto 0); |
---|
| 3518 | clk : in std_logic; |
---|
| 3519 | ce : in std_logic; |
---|
| 3520 | clr : in std_logic); |
---|
| 3521 | end concat_a1e126f11c; |
---|
| 3522 | |
---|
| 3523 | |
---|
| 3524 | architecture behavior of concat_a1e126f11c is |
---|
| 3525 | signal in0_1_23: unsigned((8 - 1) downto 0); |
---|
| 3526 | signal in1_1_27: unsigned((8 - 1) downto 0); |
---|
| 3527 | signal in2_1_31: unsigned((8 - 1) downto 0); |
---|
| 3528 | signal in3_1_35: unsigned((8 - 1) downto 0); |
---|
| 3529 | signal y_2_1_concat: unsigned((32 - 1) downto 0); |
---|
| 3530 | begin |
---|
| 3531 | in0_1_23 <= std_logic_vector_to_unsigned(in0); |
---|
| 3532 | in1_1_27 <= std_logic_vector_to_unsigned(in1); |
---|
| 3533 | in2_1_31 <= std_logic_vector_to_unsigned(in2); |
---|
| 3534 | in3_1_35 <= std_logic_vector_to_unsigned(in3); |
---|
| 3535 | y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27) & unsigned_to_std_logic_vector(in2_1_31) & unsigned_to_std_logic_vector(in3_1_35)); |
---|
| 3536 | y <= unsigned_to_std_logic_vector(y_2_1_concat); |
---|
| 3537 | end behavior; |
---|
| 3538 | |
---|
| 3539 | library IEEE; |
---|
| 3540 | use IEEE.std_logic_1164.all; |
---|
| 3541 | use IEEE.numeric_std.all; |
---|
| 3542 | use work.conv_pkg.all; |
---|
| 3543 | |
---|
| 3544 | entity concat_09e13b86e0 is |
---|
| 3545 | port ( |
---|
| 3546 | in0 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3547 | in1 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3548 | in2 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3549 | y : out std_logic_vector((3 - 1) downto 0); |
---|
| 3550 | clk : in std_logic; |
---|
| 3551 | ce : in std_logic; |
---|
| 3552 | clr : in std_logic); |
---|
| 3553 | end concat_09e13b86e0; |
---|
| 3554 | |
---|
| 3555 | |
---|
| 3556 | architecture behavior of concat_09e13b86e0 is |
---|
| 3557 | signal in0_1_23: boolean; |
---|
| 3558 | signal in1_1_27: boolean; |
---|
| 3559 | signal in2_1_31: boolean; |
---|
| 3560 | signal y_2_1_concat: unsigned((3 - 1) downto 0); |
---|
| 3561 | begin |
---|
| 3562 | in0_1_23 <= ((in0) = "1"); |
---|
| 3563 | in1_1_27 <= ((in1) = "1"); |
---|
| 3564 | in2_1_31 <= ((in2) = "1"); |
---|
| 3565 | y_2_1_concat <= std_logic_vector_to_unsigned(boolean_to_vector(in0_1_23) & boolean_to_vector(in1_1_27) & boolean_to_vector(in2_1_31)); |
---|
| 3566 | y <= unsigned_to_std_logic_vector(y_2_1_concat); |
---|
| 3567 | end behavior; |
---|
| 3568 | |
---|
| 3569 | library IEEE; |
---|
| 3570 | use IEEE.std_logic_1164.all; |
---|
| 3571 | use IEEE.numeric_std.all; |
---|
| 3572 | use work.conv_pkg.all; |
---|
| 3573 | |
---|
| 3574 | entity logical_a6d07705dd is |
---|
| 3575 | port ( |
---|
| 3576 | d0 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3577 | d1 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3578 | d2 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3579 | d3 : in std_logic_vector((1 - 1) downto 0); |
---|
| 3580 | y : out std_logic_vector((1 - 1) downto 0); |
---|
| 3581 | clk : in std_logic; |
---|
| 3582 | ce : in std_logic; |
---|
| 3583 | clr : in std_logic); |
---|
| 3584 | end logical_a6d07705dd; |
---|
| 3585 | |
---|
| 3586 | |
---|
| 3587 | architecture behavior of logical_a6d07705dd is |
---|
| 3588 | signal d0_1_24: std_logic; |
---|
| 3589 | signal d1_1_27: std_logic; |
---|
| 3590 | signal d2_1_30: std_logic; |
---|
| 3591 | signal d3_1_33: std_logic; |
---|
| 3592 | signal fully_2_1_bit: std_logic; |
---|
| 3593 | begin |
---|
| 3594 | d0_1_24 <= d0(0); |
---|
| 3595 | d1_1_27 <= d1(0); |
---|
| 3596 | d2_1_30 <= d2(0); |
---|
| 3597 | d3_1_33 <= d3(0); |
---|
| 3598 | fully_2_1_bit <= d0_1_24 or d1_1_27 or d2_1_30 or d3_1_33; |
---|
| 3599 | y <= std_logic_to_vector(fully_2_1_bit); |
---|
| 3600 | end behavior; |
---|
| 3601 | |
---|
| 3602 | |
---|
| 3603 | ------------------------------------------------------------------- |
---|
| 3604 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 3605 | -- |
---|
| 3606 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 3607 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 3608 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 3609 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 3610 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 3611 | -- this text/file solely for design, simulation, implementation and |
---|
| 3612 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 3613 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 3614 | -- and immediately terminates your license unless covered by a separate |
---|
| 3615 | -- agreement. |
---|
| 3616 | -- |
---|
| 3617 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 3618 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 3619 | -- providing this design, code, or information as one possible |
---|
| 3620 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 3621 | -- making no representation that this implementation is free from any |
---|
| 3622 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 3623 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 3624 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 3625 | -- implementation, including but not limited to warranties of |
---|
| 3626 | -- merchantability or fitness for a particular purpose. |
---|
| 3627 | -- |
---|
| 3628 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 3629 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 3630 | -- |
---|
| 3631 | -- Any modifications that are made to the source code are done at the user's |
---|
| 3632 | -- sole risk and will be unsupported. |
---|
| 3633 | -- |
---|
| 3634 | -- This copyright and support notice must be retained as part of this |
---|
| 3635 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 3636 | -- reserved. |
---|
| 3637 | ------------------------------------------------------------------- |
---|
| 3638 | library IEEE; |
---|
| 3639 | use IEEE.std_logic_1164.all; |
---|
| 3640 | use IEEE.std_logic_arith.all; |
---|
| 3641 | use work.conv_pkg.all; |
---|
| 3642 | entity xlslice is |
---|
| 3643 | generic ( |
---|
| 3644 | new_msb : integer := 9; |
---|
| 3645 | new_lsb : integer := 1; |
---|
| 3646 | x_width : integer := 16; |
---|
| 3647 | y_width : integer := 8); |
---|
| 3648 | port ( |
---|
| 3649 | x : in std_logic_vector (x_width-1 downto 0); |
---|
| 3650 | y : out std_logic_vector (y_width-1 downto 0)); |
---|
| 3651 | end xlslice; |
---|
| 3652 | architecture behavior of xlslice is |
---|
| 3653 | begin |
---|
| 3654 | y <= x(new_msb downto new_lsb); |
---|
| 3655 | end behavior; |
---|
| 3656 | library IEEE; |
---|
| 3657 | use IEEE.std_logic_1164.all; |
---|
| 3658 | use work.conv_pkg.all; |
---|
| 3659 | |
---|
| 3660 | -- Generated from Simulink block "warp_timer/EDK Processor" |
---|
| 3661 | |
---|
| 3662 | entity edk_processor_entity_cddda35d8e is |
---|
| 3663 | port ( |
---|
| 3664 | ce_1: in std_logic; |
---|
| 3665 | clk_1: in std_logic; |
---|
| 3666 | from_register: in std_logic_vector(31 downto 0); |
---|
| 3667 | from_register1: in std_logic_vector(31 downto 0); |
---|
| 3668 | from_register2: in std_logic_vector(31 downto 0); |
---|
| 3669 | from_register3: in std_logic_vector(31 downto 0); |
---|
| 3670 | from_register4: in std_logic_vector(31 downto 0); |
---|
| 3671 | from_register5: in std_logic_vector(31 downto 0); |
---|
| 3672 | plb_abus: in std_logic_vector(31 downto 0); |
---|
| 3673 | plb_pavalid: in std_logic; |
---|
| 3674 | plb_rnw: in std_logic; |
---|
| 3675 | plb_wrdbus: in std_logic_vector(31 downto 0); |
---|
| 3676 | sg_plb_addrpref: in std_logic_vector(19 downto 0); |
---|
| 3677 | splb_rst: in std_logic; |
---|
| 3678 | to_register: in std_logic_vector(31 downto 0); |
---|
| 3679 | to_register1: in std_logic_vector(31 downto 0); |
---|
| 3680 | to_register2: in std_logic_vector(31 downto 0); |
---|
| 3681 | to_register3: in std_logic_vector(31 downto 0); |
---|
| 3682 | to_register4: in std_logic_vector(31 downto 0); |
---|
| 3683 | constant5_x0: out std_logic; |
---|
| 3684 | plb_decode_x0: out std_logic; |
---|
| 3685 | plb_decode_x1: out std_logic; |
---|
| 3686 | plb_decode_x2: out std_logic; |
---|
| 3687 | plb_decode_x3: out std_logic; |
---|
| 3688 | plb_decode_x4: out std_logic_vector(31 downto 0); |
---|
| 3689 | plb_memmap_x0: out std_logic_vector(31 downto 0); |
---|
| 3690 | plb_memmap_x1: out std_logic; |
---|
| 3691 | plb_memmap_x2: out std_logic_vector(31 downto 0); |
---|
| 3692 | plb_memmap_x3: out std_logic; |
---|
| 3693 | plb_memmap_x4: out std_logic_vector(31 downto 0); |
---|
| 3694 | plb_memmap_x5: out std_logic; |
---|
| 3695 | plb_memmap_x6: out std_logic_vector(31 downto 0); |
---|
| 3696 | plb_memmap_x7: out std_logic; |
---|
| 3697 | plb_memmap_x8: out std_logic_vector(31 downto 0); |
---|
| 3698 | plb_memmap_x9: out std_logic |
---|
| 3699 | ); |
---|
| 3700 | end edk_processor_entity_cddda35d8e; |
---|
| 3701 | |
---|
| 3702 | architecture structural of edk_processor_entity_cddda35d8e is |
---|
| 3703 | signal bankaddr: std_logic_vector(1 downto 0); |
---|
| 3704 | signal ce_1_sg_x0: std_logic; |
---|
| 3705 | signal clk_1_sg_x0: std_logic; |
---|
| 3706 | signal linearaddr: std_logic_vector(7 downto 0); |
---|
| 3707 | signal plb_abus_net_x0: std_logic_vector(31 downto 0); |
---|
| 3708 | signal plb_pavalid_net_x0: std_logic; |
---|
| 3709 | signal plb_rnw_net_x0: std_logic; |
---|
| 3710 | signal plb_wrdbus_net_x0: std_logic_vector(31 downto 0); |
---|
| 3711 | signal rddata: std_logic_vector(31 downto 0); |
---|
| 3712 | signal rnwreg: std_logic; |
---|
| 3713 | signal sg_plb_addrpref_net_x0: std_logic_vector(19 downto 0); |
---|
| 3714 | signal sl_addrack_x0: std_logic; |
---|
| 3715 | signal sl_rdcomp_x0: std_logic; |
---|
| 3716 | signal sl_rddack_x0: std_logic; |
---|
| 3717 | signal sl_rddbus_x0: std_logic_vector(31 downto 0); |
---|
| 3718 | signal sl_wait_x0: std_logic; |
---|
| 3719 | signal sl_wrdack_x0: std_logic; |
---|
| 3720 | signal splb_rst_net_x0: std_logic; |
---|
| 3721 | signal timer0_countto_din_x0: std_logic_vector(31 downto 0); |
---|
| 3722 | signal timer0_countto_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3723 | signal timer0_countto_en_x0: std_logic; |
---|
| 3724 | signal timer0_timeleft_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3725 | signal timer1_countto_din_x0: std_logic_vector(31 downto 0); |
---|
| 3726 | signal timer1_countto_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3727 | signal timer1_countto_en_x0: std_logic; |
---|
| 3728 | signal timer1_timeleft_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3729 | signal timer2_countto_din_x0: std_logic_vector(31 downto 0); |
---|
| 3730 | signal timer2_countto_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3731 | signal timer2_countto_en_x0: std_logic; |
---|
| 3732 | signal timer2_timeleft_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3733 | signal timer3_countto_din_x0: std_logic_vector(31 downto 0); |
---|
| 3734 | signal timer3_countto_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3735 | signal timer3_countto_en_x0: std_logic; |
---|
| 3736 | signal timer3_timeleft_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3737 | signal timer_control_r_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3738 | signal timer_control_w_din_x0: std_logic_vector(31 downto 0); |
---|
| 3739 | signal timer_control_w_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3740 | signal timer_control_w_en_x0: std_logic; |
---|
| 3741 | signal timer_status_dout_x0: std_logic_vector(31 downto 0); |
---|
| 3742 | signal wrdbusreg: std_logic_vector(31 downto 0); |
---|
| 3743 | |
---|
| 3744 | begin |
---|
| 3745 | ce_1_sg_x0 <= ce_1; |
---|
| 3746 | clk_1_sg_x0 <= clk_1; |
---|
| 3747 | timer0_timeleft_dout_x0 <= from_register; |
---|
| 3748 | timer1_timeleft_dout_x0 <= from_register1; |
---|
| 3749 | timer2_timeleft_dout_x0 <= from_register2; |
---|
| 3750 | timer3_timeleft_dout_x0 <= from_register3; |
---|
| 3751 | timer_control_r_dout_x0 <= from_register4; |
---|
| 3752 | timer_status_dout_x0 <= from_register5; |
---|
| 3753 | plb_abus_net_x0 <= plb_abus; |
---|
| 3754 | plb_pavalid_net_x0 <= plb_pavalid; |
---|
| 3755 | plb_rnw_net_x0 <= plb_rnw; |
---|
| 3756 | plb_wrdbus_net_x0 <= plb_wrdbus; |
---|
| 3757 | sg_plb_addrpref_net_x0 <= sg_plb_addrpref; |
---|
| 3758 | splb_rst_net_x0 <= splb_rst; |
---|
| 3759 | timer0_countto_dout_x0 <= to_register; |
---|
| 3760 | timer1_countto_dout_x0 <= to_register1; |
---|
| 3761 | timer2_countto_dout_x0 <= to_register2; |
---|
| 3762 | timer3_countto_dout_x0 <= to_register3; |
---|
| 3763 | timer_control_w_dout_x0 <= to_register4; |
---|
| 3764 | constant5_x0 <= sl_wait_x0; |
---|
| 3765 | plb_decode_x0 <= sl_addrack_x0; |
---|
| 3766 | plb_decode_x1 <= sl_rdcomp_x0; |
---|
| 3767 | plb_decode_x2 <= sl_wrdack_x0; |
---|
| 3768 | plb_decode_x3 <= sl_rddack_x0; |
---|
| 3769 | plb_decode_x4 <= sl_rddbus_x0; |
---|
| 3770 | plb_memmap_x0 <= timer0_countto_din_x0; |
---|
| 3771 | plb_memmap_x1 <= timer0_countto_en_x0; |
---|
| 3772 | plb_memmap_x2 <= timer1_countto_din_x0; |
---|
| 3773 | plb_memmap_x3 <= timer1_countto_en_x0; |
---|
| 3774 | plb_memmap_x4 <= timer2_countto_din_x0; |
---|
| 3775 | plb_memmap_x5 <= timer2_countto_en_x0; |
---|
| 3776 | plb_memmap_x6 <= timer3_countto_din_x0; |
---|
| 3777 | plb_memmap_x7 <= timer3_countto_en_x0; |
---|
| 3778 | plb_memmap_x8 <= timer_control_w_din_x0; |
---|
| 3779 | plb_memmap_x9 <= timer_control_w_en_x0; |
---|
| 3780 | |
---|
| 3781 | constant5: entity work.constant_963ed6358a |
---|
| 3782 | port map ( |
---|
| 3783 | ce => '0', |
---|
| 3784 | clk => '0', |
---|
| 3785 | clr => '0', |
---|
| 3786 | op(0) => sl_wait_x0 |
---|
| 3787 | ); |
---|
| 3788 | |
---|
| 3789 | plb_decode: entity work.mcode_block_b389f41afb |
---|
| 3790 | port map ( |
---|
| 3791 | addrpref => sg_plb_addrpref_net_x0, |
---|
| 3792 | ce => ce_1_sg_x0, |
---|
| 3793 | clk => clk_1_sg_x0, |
---|
| 3794 | clr => '0', |
---|
| 3795 | plbabus => plb_abus_net_x0, |
---|
| 3796 | plbpavalid(0) => plb_pavalid_net_x0, |
---|
| 3797 | plbrnw(0) => plb_rnw_net_x0, |
---|
| 3798 | plbrst(0) => splb_rst_net_x0, |
---|
| 3799 | plbwrdbus => plb_wrdbus_net_x0, |
---|
| 3800 | rddata => rddata, |
---|
| 3801 | addrack(0) => sl_addrack_x0, |
---|
| 3802 | bankaddr => bankaddr, |
---|
| 3803 | linearaddr => linearaddr, |
---|
| 3804 | rdcomp(0) => sl_rdcomp_x0, |
---|
| 3805 | rddack(0) => sl_rddack_x0, |
---|
| 3806 | rddbus => sl_rddbus_x0, |
---|
| 3807 | rnwreg(0) => rnwreg, |
---|
| 3808 | wrdack(0) => sl_wrdack_x0, |
---|
| 3809 | wrdbusreg => wrdbusreg |
---|
| 3810 | ); |
---|
| 3811 | |
---|
| 3812 | plb_memmap: entity work.mcode_block_b59e0d51fc |
---|
| 3813 | port map ( |
---|
| 3814 | addrack(0) => sl_addrack_x0, |
---|
| 3815 | bankaddr => bankaddr, |
---|
| 3816 | ce => ce_1_sg_x0, |
---|
| 3817 | clk => clk_1_sg_x0, |
---|
| 3818 | clr => '0', |
---|
| 3819 | linearaddr => linearaddr, |
---|
| 3820 | rnwreg(0) => rnwreg, |
---|
| 3821 | sm_timer0_countto => timer0_countto_dout_x0, |
---|
| 3822 | sm_timer0_timeleft => timer0_timeleft_dout_x0, |
---|
| 3823 | sm_timer1_countto => timer1_countto_dout_x0, |
---|
| 3824 | sm_timer1_timeleft => timer1_timeleft_dout_x0, |
---|
| 3825 | sm_timer2_countto => timer2_countto_dout_x0, |
---|
| 3826 | sm_timer2_timeleft => timer2_timeleft_dout_x0, |
---|
| 3827 | sm_timer3_countto => timer3_countto_dout_x0, |
---|
| 3828 | sm_timer3_timeleft => timer3_timeleft_dout_x0, |
---|
| 3829 | sm_timer_control_r => timer_control_r_dout_x0, |
---|
| 3830 | sm_timer_control_w => timer_control_w_dout_x0, |
---|
| 3831 | sm_timer_status => timer_status_dout_x0, |
---|
| 3832 | wrdbus => wrdbusreg, |
---|
| 3833 | read_bank_out => rddata, |
---|
| 3834 | sm_timer0_countto_din => timer0_countto_din_x0, |
---|
| 3835 | sm_timer0_countto_en(0) => timer0_countto_en_x0, |
---|
| 3836 | sm_timer1_countto_din => timer1_countto_din_x0, |
---|
| 3837 | sm_timer1_countto_en(0) => timer1_countto_en_x0, |
---|
| 3838 | sm_timer2_countto_din => timer2_countto_din_x0, |
---|
| 3839 | sm_timer2_countto_en(0) => timer2_countto_en_x0, |
---|
| 3840 | sm_timer3_countto_din => timer3_countto_din_x0, |
---|
| 3841 | sm_timer3_countto_en(0) => timer3_countto_en_x0, |
---|
| 3842 | sm_timer_control_w_din => timer_control_w_din_x0, |
---|
| 3843 | sm_timer_control_w_en(0) => timer_control_w_en_x0 |
---|
| 3844 | ); |
---|
| 3845 | |
---|
| 3846 | end structural; |
---|
| 3847 | library IEEE; |
---|
| 3848 | use IEEE.std_logic_1164.all; |
---|
| 3849 | use work.conv_pkg.all; |
---|
| 3850 | |
---|
| 3851 | -- Generated from Simulink block "warp_timer/timer/S-R_Latch1" |
---|
| 3852 | |
---|
| 3853 | entity s_r_latch1_entity_5f9ce35768 is |
---|
| 3854 | port ( |
---|
| 3855 | ce_1: in std_logic; |
---|
| 3856 | clk_1: in std_logic; |
---|
| 3857 | r: in std_logic; |
---|
| 3858 | s: in std_logic; |
---|
| 3859 | q: out std_logic |
---|
| 3860 | ); |
---|
| 3861 | end s_r_latch1_entity_5f9ce35768; |
---|
| 3862 | |
---|
| 3863 | architecture structural of s_r_latch1_entity_5f9ce35768 is |
---|
| 3864 | signal ce_1_sg_x1: std_logic; |
---|
| 3865 | signal clk_1_sg_x1: std_logic; |
---|
| 3866 | signal inverter_op_net: std_logic; |
---|
| 3867 | signal logical2_y_net_x0: std_logic; |
---|
| 3868 | signal logical3_y_net_x0: std_logic; |
---|
| 3869 | signal register_q_net_x0: std_logic; |
---|
| 3870 | |
---|
| 3871 | begin |
---|
| 3872 | ce_1_sg_x1 <= ce_1; |
---|
| 3873 | clk_1_sg_x1 <= clk_1; |
---|
| 3874 | logical2_y_net_x0 <= r; |
---|
| 3875 | logical3_y_net_x0 <= s; |
---|
| 3876 | q <= register_q_net_x0; |
---|
| 3877 | |
---|
| 3878 | inverter: entity work.inverter_e5b38cca3b |
---|
| 3879 | port map ( |
---|
| 3880 | ce => ce_1_sg_x1, |
---|
| 3881 | clk => clk_1_sg_x1, |
---|
| 3882 | clr => '0', |
---|
| 3883 | ip(0) => register_q_net_x0, |
---|
| 3884 | op(0) => inverter_op_net |
---|
| 3885 | ); |
---|
| 3886 | |
---|
| 3887 | register_x0: entity work.xlregister |
---|
| 3888 | generic map ( |
---|
| 3889 | d_width => 1, |
---|
| 3890 | init_value => b"0" |
---|
| 3891 | ) |
---|
| 3892 | port map ( |
---|
| 3893 | ce => ce_1_sg_x1, |
---|
| 3894 | clk => clk_1_sg_x1, |
---|
| 3895 | d(0) => logical3_y_net_x0, |
---|
| 3896 | en(0) => inverter_op_net, |
---|
| 3897 | rst(0) => logical2_y_net_x0, |
---|
| 3898 | q(0) => register_q_net_x0 |
---|
| 3899 | ); |
---|
| 3900 | |
---|
| 3901 | end structural; |
---|
| 3902 | library IEEE; |
---|
| 3903 | use IEEE.std_logic_1164.all; |
---|
| 3904 | use work.conv_pkg.all; |
---|
| 3905 | |
---|
| 3906 | -- Generated from Simulink block "warp_timer/timer/posedge" |
---|
| 3907 | |
---|
| 3908 | entity posedge_entity_8c50a6be04 is |
---|
| 3909 | port ( |
---|
| 3910 | ce_1: in std_logic; |
---|
| 3911 | clk_1: in std_logic; |
---|
| 3912 | in_x0: in std_logic; |
---|
| 3913 | out_x0: out std_logic |
---|
| 3914 | ); |
---|
| 3915 | end posedge_entity_8c50a6be04; |
---|
| 3916 | |
---|
| 3917 | architecture structural of posedge_entity_8c50a6be04 is |
---|
| 3918 | signal ce_1_sg_x3: std_logic; |
---|
| 3919 | signal clk_1_sg_x3: std_logic; |
---|
| 3920 | signal delay_q_net: std_logic; |
---|
| 3921 | signal inverter_op_net: std_logic; |
---|
| 3922 | signal logical_y_net_x0: std_logic; |
---|
| 3923 | signal slice_y_net_x0: std_logic; |
---|
| 3924 | |
---|
| 3925 | begin |
---|
| 3926 | ce_1_sg_x3 <= ce_1; |
---|
| 3927 | clk_1_sg_x3 <= clk_1; |
---|
| 3928 | slice_y_net_x0 <= in_x0; |
---|
| 3929 | out_x0 <= logical_y_net_x0; |
---|
| 3930 | |
---|
| 3931 | delay: entity work.xldelay |
---|
| 3932 | generic map ( |
---|
| 3933 | latency => 1, |
---|
| 3934 | reg_retiming => 0, |
---|
| 3935 | width => 1 |
---|
| 3936 | ) |
---|
| 3937 | port map ( |
---|
| 3938 | ce => ce_1_sg_x3, |
---|
| 3939 | clk => clk_1_sg_x3, |
---|
| 3940 | d(0) => slice_y_net_x0, |
---|
| 3941 | en => '1', |
---|
| 3942 | q(0) => delay_q_net |
---|
| 3943 | ); |
---|
| 3944 | |
---|
| 3945 | inverter: entity work.inverter_e5b38cca3b |
---|
| 3946 | port map ( |
---|
| 3947 | ce => ce_1_sg_x3, |
---|
| 3948 | clk => clk_1_sg_x3, |
---|
| 3949 | clr => '0', |
---|
| 3950 | ip(0) => delay_q_net, |
---|
| 3951 | op(0) => inverter_op_net |
---|
| 3952 | ); |
---|
| 3953 | |
---|
| 3954 | logical: entity work.logical_80f90b97d0 |
---|
| 3955 | port map ( |
---|
| 3956 | ce => '0', |
---|
| 3957 | clk => '0', |
---|
| 3958 | clr => '0', |
---|
| 3959 | d0(0) => slice_y_net_x0, |
---|
| 3960 | d1(0) => inverter_op_net, |
---|
| 3961 | y(0) => logical_y_net_x0 |
---|
| 3962 | ); |
---|
| 3963 | |
---|
| 3964 | end structural; |
---|
| 3965 | library IEEE; |
---|
| 3966 | use IEEE.std_logic_1164.all; |
---|
| 3967 | use work.conv_pkg.all; |
---|
| 3968 | |
---|
| 3969 | -- Generated from Simulink block "warp_timer/timer" |
---|
| 3970 | |
---|
| 3971 | entity timer_entity_fee90fe8e7 is |
---|
| 3972 | port ( |
---|
| 3973 | ce_1: in std_logic; |
---|
| 3974 | clk_1: in std_logic; |
---|
| 3975 | countto: in std_logic_vector(31 downto 0); |
---|
| 3976 | idlefordifs_inp: in std_logic; |
---|
| 3977 | interruptreset: in std_logic; |
---|
| 3978 | mode: in std_logic; |
---|
| 3979 | pause: in std_logic; |
---|
| 3980 | resume: in std_logic; |
---|
| 3981 | start: in std_logic; |
---|
| 3982 | stop: in std_logic; |
---|
| 3983 | active: out std_logic; |
---|
| 3984 | interrupt: out std_logic; |
---|
| 3985 | paused: out std_logic; |
---|
| 3986 | timeleft: out std_logic_vector(31 downto 0) |
---|
| 3987 | ); |
---|
| 3988 | end timer_entity_fee90fe8e7; |
---|
| 3989 | |
---|
| 3990 | architecture structural of timer_entity_fee90fe8e7 is |
---|
| 3991 | signal addsub_s_net_x0: std_logic_vector(31 downto 0); |
---|
| 3992 | signal ce_1_sg_x5: std_logic; |
---|
| 3993 | signal clk_1_sg_x5: std_logic; |
---|
| 3994 | signal constant1_op_net: std_logic; |
---|
| 3995 | signal constant_op_net: std_logic_vector(31 downto 0); |
---|
| 3996 | signal convert1_dout_net: std_logic; |
---|
| 3997 | signal counter_op_net: std_logic_vector(31 downto 0); |
---|
| 3998 | signal from_register1_data_out_net_x0: std_logic_vector(31 downto 0); |
---|
| 3999 | signal idlefordifs_net_x0: std_logic; |
---|
| 4000 | signal inverter_op_net: std_logic; |
---|
| 4001 | signal logical1_y_net: std_logic; |
---|
| 4002 | signal logical2_y_net_x0: std_logic; |
---|
| 4003 | signal logical3_y_net_x0: std_logic; |
---|
| 4004 | signal logical4_y_net_x0: std_logic; |
---|
| 4005 | signal logical_y_net: std_logic; |
---|
| 4006 | signal logical_y_net_x0: std_logic; |
---|
| 4007 | signal logical_y_net_x1: std_logic; |
---|
| 4008 | signal mux_y_net: std_logic; |
---|
| 4009 | signal register_q_net_x2: std_logic; |
---|
| 4010 | signal register_q_net_x3: std_logic; |
---|
| 4011 | signal relational1_op_net: std_logic; |
---|
| 4012 | signal relational_op_net_x0: std_logic; |
---|
| 4013 | signal slice1_y_net_x0: std_logic; |
---|
| 4014 | signal slice2_y_net_x1: std_logic; |
---|
| 4015 | signal slice3_y_net_x0: std_logic; |
---|
| 4016 | signal slice4_y_net_x0: std_logic; |
---|
| 4017 | signal slice5_y_net_x1: std_logic; |
---|
| 4018 | signal slice_y_net_x1: std_logic; |
---|
| 4019 | |
---|
| 4020 | begin |
---|
| 4021 | ce_1_sg_x5 <= ce_1; |
---|
| 4022 | clk_1_sg_x5 <= clk_1; |
---|
| 4023 | from_register1_data_out_net_x0 <= countto; |
---|
| 4024 | idlefordifs_net_x0 <= idlefordifs_inp; |
---|
| 4025 | slice5_y_net_x1 <= interruptreset; |
---|
| 4026 | slice4_y_net_x0 <= mode; |
---|
| 4027 | slice3_y_net_x0 <= pause; |
---|
| 4028 | slice2_y_net_x1 <= resume; |
---|
| 4029 | slice_y_net_x1 <= start; |
---|
| 4030 | slice1_y_net_x0 <= stop; |
---|
| 4031 | active <= register_q_net_x2; |
---|
| 4032 | interrupt <= register_q_net_x3; |
---|
| 4033 | paused <= logical4_y_net_x0; |
---|
| 4034 | timeleft <= addsub_s_net_x0; |
---|
| 4035 | |
---|
| 4036 | addsub: entity work.xladdsub |
---|
| 4037 | generic map ( |
---|
| 4038 | a_arith => xlUnsigned, |
---|
| 4039 | a_bin_pt => 0, |
---|
| 4040 | a_width => 32, |
---|
| 4041 | b_arith => xlUnsigned, |
---|
| 4042 | b_bin_pt => 0, |
---|
| 4043 | b_width => 32, |
---|
| 4044 | c_has_b_out => 0, |
---|
| 4045 | c_has_c_out => 0, |
---|
| 4046 | c_has_q => 0, |
---|
| 4047 | c_has_q_b_out => 0, |
---|
| 4048 | c_has_q_c_out => 0, |
---|
| 4049 | c_has_s => 1, |
---|
| 4050 | c_latency => 0, |
---|
| 4051 | c_output_width => 33, |
---|
| 4052 | core_name0 => "adder_subtracter_virtex2p_7_0_f7ee8f7e7f94515e", |
---|
| 4053 | extra_registers => 0, |
---|
| 4054 | full_s_arith => 2, |
---|
| 4055 | full_s_width => 33, |
---|
| 4056 | latency => 0, |
---|
| 4057 | mode => 2, |
---|
| 4058 | overflow => 1, |
---|
| 4059 | quantization => 1, |
---|
| 4060 | s_arith => xlUnsigned, |
---|
| 4061 | s_bin_pt => 0, |
---|
| 4062 | s_width => 32 |
---|
| 4063 | ) |
---|
| 4064 | port map ( |
---|
| 4065 | a => from_register1_data_out_net_x0, |
---|
| 4066 | b => counter_op_net, |
---|
| 4067 | ce => ce_1_sg_x5, |
---|
| 4068 | clk => clk_1_sg_x5, |
---|
| 4069 | clr => '0', |
---|
| 4070 | en => "1", |
---|
| 4071 | s => addsub_s_net_x0 |
---|
| 4072 | ); |
---|
| 4073 | |
---|
| 4074 | constant1: entity work.constant_6293007044 |
---|
| 4075 | port map ( |
---|
| 4076 | ce => '0', |
---|
| 4077 | clk => '0', |
---|
| 4078 | clr => '0', |
---|
| 4079 | op(0) => constant1_op_net |
---|
| 4080 | ); |
---|
| 4081 | |
---|
| 4082 | constant_x0: entity work.constant_37567836aa |
---|
| 4083 | port map ( |
---|
| 4084 | ce => '0', |
---|
| 4085 | clk => '0', |
---|
| 4086 | clr => '0', |
---|
| 4087 | op => constant_op_net |
---|
| 4088 | ); |
---|
| 4089 | |
---|
| 4090 | convert1: entity work.xlconvert |
---|
| 4091 | generic map ( |
---|
| 4092 | bool_conversion => 1, |
---|
| 4093 | din_arith => 1, |
---|
| 4094 | din_bin_pt => 0, |
---|
| 4095 | din_width => 1, |
---|
| 4096 | dout_arith => 1, |
---|
| 4097 | dout_bin_pt => 0, |
---|
| 4098 | dout_width => 1, |
---|
| 4099 | latency => 0, |
---|
| 4100 | overflow => xlWrap, |
---|
| 4101 | quantization => xlTruncate |
---|
| 4102 | ) |
---|
| 4103 | port map ( |
---|
| 4104 | ce => '0', |
---|
| 4105 | clk => '0', |
---|
| 4106 | clr => '0', |
---|
| 4107 | din(0) => mux_y_net, |
---|
| 4108 | dout(0) => convert1_dout_net |
---|
| 4109 | ); |
---|
| 4110 | |
---|
| 4111 | counter: entity work.xlcounter_free |
---|
| 4112 | generic map ( |
---|
| 4113 | core_name0 => "binary_counter_virtex2p_7_0_b57302a6bcbb6876", |
---|
| 4114 | op_arith => xlUnsigned, |
---|
| 4115 | op_width => 32 |
---|
| 4116 | ) |
---|
| 4117 | port map ( |
---|
| 4118 | ce => ce_1_sg_x5, |
---|
| 4119 | clk => clk_1_sg_x5, |
---|
| 4120 | clr => '0', |
---|
| 4121 | en(0) => logical_y_net, |
---|
| 4122 | rst(0) => logical1_y_net, |
---|
| 4123 | op => counter_op_net |
---|
| 4124 | ); |
---|
| 4125 | |
---|
| 4126 | inverter: entity work.inverter_e5b38cca3b |
---|
| 4127 | port map ( |
---|
| 4128 | ce => ce_1_sg_x5, |
---|
| 4129 | clk => clk_1_sg_x5, |
---|
| 4130 | clr => '0', |
---|
| 4131 | ip(0) => register_q_net_x2, |
---|
| 4132 | op(0) => inverter_op_net |
---|
| 4133 | ); |
---|
| 4134 | |
---|
| 4135 | logical: entity work.logical_80f90b97d0 |
---|
| 4136 | port map ( |
---|
| 4137 | ce => '0', |
---|
| 4138 | clk => '0', |
---|
| 4139 | clr => '0', |
---|
| 4140 | d0(0) => convert1_dout_net, |
---|
| 4141 | d1(0) => register_q_net_x2, |
---|
| 4142 | y(0) => logical_y_net |
---|
| 4143 | ); |
---|
| 4144 | |
---|
| 4145 | logical1: entity work.logical_6cb8f0ce02 |
---|
| 4146 | port map ( |
---|
| 4147 | ce => '0', |
---|
| 4148 | clk => '0', |
---|
| 4149 | clr => '0', |
---|
| 4150 | d0(0) => relational_op_net_x0, |
---|
| 4151 | d1(0) => slice1_y_net_x0, |
---|
| 4152 | d2(0) => logical_y_net_x0, |
---|
| 4153 | y(0) => logical1_y_net |
---|
| 4154 | ); |
---|
| 4155 | |
---|
| 4156 | logical2: entity work.logical_6cb8f0ce02 |
---|
| 4157 | port map ( |
---|
| 4158 | ce => '0', |
---|
| 4159 | clk => '0', |
---|
| 4160 | clr => '0', |
---|
| 4161 | d0(0) => slice1_y_net_x0, |
---|
| 4162 | d1(0) => slice3_y_net_x0, |
---|
| 4163 | d2(0) => relational_op_net_x0, |
---|
| 4164 | y(0) => logical2_y_net_x0 |
---|
| 4165 | ); |
---|
| 4166 | |
---|
| 4167 | logical3: entity work.logical_aacf6e1b0e |
---|
| 4168 | port map ( |
---|
| 4169 | ce => '0', |
---|
| 4170 | clk => '0', |
---|
| 4171 | clr => '0', |
---|
| 4172 | d0(0) => logical_y_net_x0, |
---|
| 4173 | d1(0) => logical_y_net_x1, |
---|
| 4174 | y(0) => logical3_y_net_x0 |
---|
| 4175 | ); |
---|
| 4176 | |
---|
| 4177 | logical4: entity work.logical_80f90b97d0 |
---|
| 4178 | port map ( |
---|
| 4179 | ce => '0', |
---|
| 4180 | clk => '0', |
---|
| 4181 | clr => '0', |
---|
| 4182 | d0(0) => relational1_op_net, |
---|
| 4183 | d1(0) => inverter_op_net, |
---|
| 4184 | y(0) => logical4_y_net_x0 |
---|
| 4185 | ); |
---|
| 4186 | |
---|
| 4187 | mux: entity work.mux_112ed141f4 |
---|
| 4188 | port map ( |
---|
| 4189 | ce => '0', |
---|
| 4190 | clk => '0', |
---|
| 4191 | clr => '0', |
---|
| 4192 | d0(0) => constant1_op_net, |
---|
| 4193 | d1(0) => idlefordifs_net_x0, |
---|
| 4194 | sel(0) => slice4_y_net_x0, |
---|
| 4195 | y(0) => mux_y_net |
---|
| 4196 | ); |
---|
| 4197 | |
---|
| 4198 | posedge1_8332b77348: entity work.posedge_entity_8c50a6be04 |
---|
| 4199 | port map ( |
---|
| 4200 | ce_1 => ce_1_sg_x5, |
---|
| 4201 | clk_1 => clk_1_sg_x5, |
---|
| 4202 | in_x0 => slice2_y_net_x1, |
---|
| 4203 | out_x0 => logical_y_net_x1 |
---|
| 4204 | ); |
---|
| 4205 | |
---|
| 4206 | posedge_8c50a6be04: entity work.posedge_entity_8c50a6be04 |
---|
| 4207 | port map ( |
---|
| 4208 | ce_1 => ce_1_sg_x5, |
---|
| 4209 | clk_1 => clk_1_sg_x5, |
---|
| 4210 | in_x0 => slice_y_net_x1, |
---|
| 4211 | out_x0 => logical_y_net_x0 |
---|
| 4212 | ); |
---|
| 4213 | |
---|
| 4214 | relational: entity work.relational_3ffd1d0a40 |
---|
| 4215 | port map ( |
---|
| 4216 | a => from_register1_data_out_net_x0, |
---|
| 4217 | b => counter_op_net, |
---|
| 4218 | ce => '0', |
---|
| 4219 | clk => '0', |
---|
| 4220 | clr => '0', |
---|
| 4221 | op(0) => relational_op_net_x0 |
---|
| 4222 | ); |
---|
| 4223 | |
---|
| 4224 | relational1: entity work.relational_34fc311f5b |
---|
| 4225 | port map ( |
---|
| 4226 | a => counter_op_net, |
---|
| 4227 | b => constant_op_net, |
---|
| 4228 | ce => ce_1_sg_x5, |
---|
| 4229 | clk => clk_1_sg_x5, |
---|
| 4230 | clr => '0', |
---|
| 4231 | op(0) => relational1_op_net |
---|
| 4232 | ); |
---|
| 4233 | |
---|
| 4234 | s_r_latch1_5f9ce35768: entity work.s_r_latch1_entity_5f9ce35768 |
---|
| 4235 | port map ( |
---|
| 4236 | ce_1 => ce_1_sg_x5, |
---|
| 4237 | clk_1 => clk_1_sg_x5, |
---|
| 4238 | r => logical2_y_net_x0, |
---|
| 4239 | s => logical3_y_net_x0, |
---|
| 4240 | q => register_q_net_x2 |
---|
| 4241 | ); |
---|
| 4242 | |
---|
| 4243 | s_r_latch2_722d862217: entity work.s_r_latch1_entity_5f9ce35768 |
---|
| 4244 | port map ( |
---|
| 4245 | ce_1 => ce_1_sg_x5, |
---|
| 4246 | clk_1 => clk_1_sg_x5, |
---|
| 4247 | r => slice5_y_net_x1, |
---|
| 4248 | s => relational_op_net_x0, |
---|
| 4249 | q => register_q_net_x3 |
---|
| 4250 | ); |
---|
| 4251 | |
---|
| 4252 | end structural; |
---|
| 4253 | library IEEE; |
---|
| 4254 | use IEEE.std_logic_1164.all; |
---|
| 4255 | use work.conv_pkg.all; |
---|
| 4256 | |
---|
| 4257 | -- Generated from Simulink block "warp_timer/timer_control" |
---|
| 4258 | |
---|
| 4259 | entity timer_control_entity_09b11c57d8 is |
---|
| 4260 | port ( |
---|
| 4261 | constant6_x0: out std_logic |
---|
| 4262 | ); |
---|
| 4263 | end timer_control_entity_09b11c57d8; |
---|
| 4264 | |
---|
| 4265 | architecture structural of timer_control_entity_09b11c57d8 is |
---|
| 4266 | signal constant6_op_net_x0: std_logic; |
---|
| 4267 | |
---|
| 4268 | begin |
---|
| 4269 | constant6_x0 <= constant6_op_net_x0; |
---|
| 4270 | |
---|
| 4271 | constant6: entity work.constant_6293007044 |
---|
| 4272 | port map ( |
---|
| 4273 | ce => '0', |
---|
| 4274 | clk => '0', |
---|
| 4275 | clr => '0', |
---|
| 4276 | op(0) => constant6_op_net_x0 |
---|
| 4277 | ); |
---|
| 4278 | |
---|
| 4279 | end structural; |
---|
| 4280 | library IEEE; |
---|
| 4281 | use IEEE.std_logic_1164.all; |
---|
| 4282 | use work.conv_pkg.all; |
---|
| 4283 | |
---|
| 4284 | -- Generated from Simulink block "warp_timer" |
---|
| 4285 | |
---|
| 4286 | entity warp_timer is |
---|
| 4287 | port ( |
---|
| 4288 | ce_1: in std_logic; |
---|
| 4289 | clk_1: in std_logic; |
---|
| 4290 | data_out: in std_logic_vector(31 downto 0); |
---|
| 4291 | data_out_x0: in std_logic_vector(31 downto 0); |
---|
| 4292 | data_out_x1: in std_logic_vector(31 downto 0); |
---|
| 4293 | data_out_x2: in std_logic_vector(31 downto 0); |
---|
| 4294 | data_out_x3: in std_logic_vector(31 downto 0); |
---|
| 4295 | data_out_x4: in std_logic_vector(31 downto 0); |
---|
| 4296 | data_out_x5: in std_logic_vector(31 downto 0); |
---|
| 4297 | data_out_x6: in std_logic_vector(31 downto 0); |
---|
| 4298 | data_out_x7: in std_logic_vector(31 downto 0); |
---|
| 4299 | data_out_x8: in std_logic_vector(31 downto 0); |
---|
| 4300 | data_out_x9: in std_logic_vector(31 downto 0); |
---|
| 4301 | dout_x4: in std_logic_vector(31 downto 0); |
---|
| 4302 | dout_x5: in std_logic_vector(31 downto 0); |
---|
| 4303 | dout_x6: in std_logic_vector(31 downto 0); |
---|
| 4304 | dout_x7: in std_logic_vector(31 downto 0); |
---|
| 4305 | dout_x8: in std_logic_vector(31 downto 0); |
---|
| 4306 | idlefordifs: in std_logic; |
---|
| 4307 | plb_abus: in std_logic_vector(31 downto 0); |
---|
| 4308 | plb_pavalid: in std_logic; |
---|
| 4309 | plb_rnw: in std_logic; |
---|
| 4310 | plb_wrdbus: in std_logic_vector(31 downto 0); |
---|
| 4311 | sg_plb_addrpref: in std_logic_vector(19 downto 0); |
---|
| 4312 | splb_rst: in std_logic; |
---|
| 4313 | data_in: out std_logic_vector(31 downto 0); |
---|
| 4314 | data_in_x0: out std_logic_vector(31 downto 0); |
---|
| 4315 | data_in_x1: out std_logic_vector(31 downto 0); |
---|
| 4316 | data_in_x2: out std_logic_vector(31 downto 0); |
---|
| 4317 | data_in_x3: out std_logic_vector(31 downto 0); |
---|
| 4318 | data_in_x4: out std_logic_vector(31 downto 0); |
---|
| 4319 | data_in_x5: out std_logic_vector(31 downto 0); |
---|
| 4320 | data_in_x6: out std_logic_vector(31 downto 0); |
---|
| 4321 | data_in_x7: out std_logic_vector(31 downto 0); |
---|
| 4322 | data_in_x8: out std_logic_vector(31 downto 0); |
---|
| 4323 | data_in_x9: out std_logic_vector(31 downto 0); |
---|
| 4324 | en: out std_logic; |
---|
| 4325 | en_x0: out std_logic; |
---|
| 4326 | en_x1: out std_logic; |
---|
| 4327 | en_x2: out std_logic; |
---|
| 4328 | en_x3: out std_logic; |
---|
| 4329 | en_x4: out std_logic; |
---|
| 4330 | en_x5: out std_logic; |
---|
| 4331 | en_x6: out std_logic; |
---|
| 4332 | en_x7: out std_logic; |
---|
| 4333 | en_x8: out std_logic; |
---|
| 4334 | en_x9: out std_logic; |
---|
| 4335 | sl_addrack: out std_logic; |
---|
| 4336 | sl_rdcomp: out std_logic; |
---|
| 4337 | sl_rddack: out std_logic; |
---|
| 4338 | sl_rddbus: out std_logic_vector(31 downto 0); |
---|
| 4339 | sl_wait: out std_logic; |
---|
| 4340 | sl_wrcomp: out std_logic; |
---|
| 4341 | sl_wrdack: out std_logic; |
---|
| 4342 | timer0_active: out std_logic; |
---|
| 4343 | timer1_active: out std_logic; |
---|
| 4344 | timer2_active: out std_logic; |
---|
| 4345 | timer3_active: out std_logic; |
---|
| 4346 | timerexpire: out std_logic |
---|
| 4347 | ); |
---|
| 4348 | end warp_timer; |
---|
| 4349 | |
---|
| 4350 | architecture structural of warp_timer is |
---|
| 4351 | signal ce_1_sg_x21: std_logic; |
---|
| 4352 | signal clk_1_sg_x21: std_logic; |
---|
| 4353 | signal concat1_y_net: std_logic_vector(2 downto 0); |
---|
| 4354 | signal concat2_y_net: std_logic_vector(2 downto 0); |
---|
| 4355 | signal concat3_y_net: std_logic_vector(2 downto 0); |
---|
| 4356 | signal concat4_y_net: std_logic_vector(2 downto 0); |
---|
| 4357 | signal convert1_dout_net: std_logic_vector(7 downto 0); |
---|
| 4358 | signal convert2_dout_net: std_logic_vector(7 downto 0); |
---|
| 4359 | signal convert3_dout_net: std_logic_vector(7 downto 0); |
---|
| 4360 | signal convert_dout_net: std_logic_vector(7 downto 0); |
---|
| 4361 | signal data_in_net: std_logic_vector(31 downto 0); |
---|
| 4362 | signal data_in_x0_net: std_logic_vector(31 downto 0); |
---|
| 4363 | signal data_in_x1_net: std_logic_vector(31 downto 0); |
---|
| 4364 | signal data_in_x2_net: std_logic_vector(31 downto 0); |
---|
| 4365 | signal data_in_x3_net: std_logic_vector(31 downto 0); |
---|
| 4366 | signal data_in_x4_net: std_logic_vector(31 downto 0); |
---|
| 4367 | signal data_in_x5_net: std_logic_vector(31 downto 0); |
---|
| 4368 | signal data_in_x6_net: std_logic_vector(31 downto 0); |
---|
| 4369 | signal data_in_x7_net: std_logic_vector(31 downto 0); |
---|
| 4370 | signal data_in_x8_net: std_logic_vector(31 downto 0); |
---|
| 4371 | signal data_out_net: std_logic_vector(31 downto 0); |
---|
| 4372 | signal data_out_x0_net: std_logic_vector(31 downto 0); |
---|
| 4373 | signal data_out_x1_net: std_logic_vector(31 downto 0); |
---|
| 4374 | signal data_out_x2_net: std_logic_vector(31 downto 0); |
---|
| 4375 | signal data_out_x3_net: std_logic_vector(31 downto 0); |
---|
| 4376 | signal data_out_x4_net: std_logic_vector(31 downto 0); |
---|
| 4377 | signal data_out_x5_net: std_logic_vector(31 downto 0); |
---|
| 4378 | signal data_out_x6_net: std_logic_vector(31 downto 0); |
---|
| 4379 | signal data_out_x7_net: std_logic_vector(31 downto 0); |
---|
| 4380 | signal data_out_x8_net: std_logic_vector(31 downto 0); |
---|
| 4381 | signal dout_x4_net: std_logic_vector(31 downto 0); |
---|
| 4382 | signal dout_x5_net: std_logic_vector(31 downto 0); |
---|
| 4383 | signal dout_x6_net: std_logic_vector(31 downto 0); |
---|
| 4384 | signal dout_x7_net: std_logic_vector(31 downto 0); |
---|
| 4385 | signal dout_x8_net: std_logic_vector(31 downto 0); |
---|
| 4386 | signal en_net: std_logic; |
---|
| 4387 | signal en_x0_net: std_logic; |
---|
| 4388 | signal en_x1_net: std_logic; |
---|
| 4389 | signal en_x2_net: std_logic; |
---|
| 4390 | signal en_x3_net: std_logic; |
---|
| 4391 | signal en_x4_net: std_logic; |
---|
| 4392 | signal en_x5_net: std_logic; |
---|
| 4393 | signal en_x6_net: std_logic; |
---|
| 4394 | signal en_x7_net: std_logic; |
---|
| 4395 | signal en_x8_net: std_logic; |
---|
| 4396 | signal en_x9_net: std_logic; |
---|
| 4397 | signal from_register2_data_out_net_x0: std_logic_vector(31 downto 0); |
---|
| 4398 | signal idlefordifs_net: std_logic; |
---|
| 4399 | signal logical4_y_net_x0: std_logic; |
---|
| 4400 | signal logical4_y_net_x1: std_logic; |
---|
| 4401 | signal logical4_y_net_x2: std_logic; |
---|
| 4402 | signal logical4_y_net_x3: std_logic; |
---|
| 4403 | signal plb_abus_net: std_logic_vector(31 downto 0); |
---|
| 4404 | signal plb_pavalid_net: std_logic; |
---|
| 4405 | signal plb_rnw_net: std_logic; |
---|
| 4406 | signal plb_wrdbus_net: std_logic_vector(31 downto 0); |
---|
| 4407 | signal register_q_net_x3: std_logic; |
---|
| 4408 | signal register_q_net_x5: std_logic; |
---|
| 4409 | signal register_q_net_x7: std_logic; |
---|
| 4410 | signal register_q_net_x9: std_logic; |
---|
| 4411 | signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); |
---|
| 4412 | signal sl_addrack_net: std_logic; |
---|
| 4413 | signal sl_rdcomp_net: std_logic; |
---|
| 4414 | signal sl_rddack_net: std_logic; |
---|
| 4415 | signal sl_rddbus_net: std_logic_vector(31 downto 0); |
---|
| 4416 | signal sl_wait_net: std_logic; |
---|
| 4417 | signal sl_wrdack_x1: std_logic; |
---|
| 4418 | signal slice10_y_net_x0: std_logic; |
---|
| 4419 | signal slice11_y_net_x1: std_logic; |
---|
| 4420 | signal slice12_y_net_x1: std_logic; |
---|
| 4421 | signal slice13_y_net_x0: std_logic; |
---|
| 4422 | signal slice14_y_net_x1: std_logic; |
---|
| 4423 | signal slice15_y_net_x0: std_logic; |
---|
| 4424 | signal slice16_y_net_x0: std_logic; |
---|
| 4425 | signal slice17_y_net_x1: std_logic; |
---|
| 4426 | signal slice18_y_net_x1: std_logic; |
---|
| 4427 | signal slice19_y_net_x0: std_logic; |
---|
| 4428 | signal slice1_y_net_x0: std_logic; |
---|
| 4429 | signal slice20_y_net_x1: std_logic; |
---|
| 4430 | signal slice21_y_net_x0: std_logic; |
---|
| 4431 | signal slice22_y_net_x0: std_logic; |
---|
| 4432 | signal slice23_y_net_x1: std_logic; |
---|
| 4433 | signal slice2_y_net_x1: std_logic; |
---|
| 4434 | signal slice3_y_net_x0: std_logic; |
---|
| 4435 | signal slice4_y_net_x0: std_logic; |
---|
| 4436 | signal slice5_y_net_x1: std_logic; |
---|
| 4437 | signal slice6_y_net_x1: std_logic; |
---|
| 4438 | signal slice7_y_net_x0: std_logic; |
---|
| 4439 | signal slice8_y_net_x1: std_logic; |
---|
| 4440 | signal slice9_y_net_x0: std_logic; |
---|
| 4441 | signal slice_y_net_x1: std_logic; |
---|
| 4442 | signal splb_rst_net: std_logic; |
---|
| 4443 | signal timer0_active_net: std_logic; |
---|
| 4444 | signal timer1_active_net: std_logic; |
---|
| 4445 | signal timer2_active_net: std_logic; |
---|
| 4446 | signal timer3_active_net: std_logic; |
---|
| 4447 | signal timerexpire_net: std_logic; |
---|
| 4448 | |
---|
| 4449 | begin |
---|
| 4450 | ce_1_sg_x21 <= ce_1; |
---|
| 4451 | clk_1_sg_x21 <= clk_1; |
---|
| 4452 | data_out_net <= data_out; |
---|
| 4453 | data_out_x0_net <= data_out_x0; |
---|
| 4454 | data_out_x1_net <= data_out_x1; |
---|
| 4455 | data_out_x2_net <= data_out_x2; |
---|
| 4456 | data_out_x3_net <= data_out_x3; |
---|
| 4457 | data_out_x4_net <= data_out_x4; |
---|
| 4458 | data_out_x5_net <= data_out_x5; |
---|
| 4459 | data_out_x6_net <= data_out_x6; |
---|
| 4460 | data_out_x7_net <= data_out_x7; |
---|
| 4461 | data_out_x8_net <= data_out_x8; |
---|
| 4462 | from_register2_data_out_net_x0 <= data_out_x9; |
---|
| 4463 | dout_x4_net <= dout_x4; |
---|
| 4464 | dout_x5_net <= dout_x5; |
---|
| 4465 | dout_x6_net <= dout_x6; |
---|
| 4466 | dout_x7_net <= dout_x7; |
---|
| 4467 | dout_x8_net <= dout_x8; |
---|
| 4468 | idlefordifs_net <= idlefordifs; |
---|
| 4469 | plb_abus_net <= plb_abus; |
---|
| 4470 | plb_pavalid_net <= plb_pavalid; |
---|
| 4471 | plb_rnw_net <= plb_rnw; |
---|
| 4472 | plb_wrdbus_net <= plb_wrdbus; |
---|
| 4473 | sg_plb_addrpref_net <= sg_plb_addrpref; |
---|
| 4474 | splb_rst_net <= splb_rst; |
---|
| 4475 | data_in <= data_in_net; |
---|
| 4476 | data_in_x0 <= data_in_x0_net; |
---|
| 4477 | data_in_x1 <= data_in_x1_net; |
---|
| 4478 | data_in_x2 <= data_in_x2_net; |
---|
| 4479 | data_in_x3 <= data_in_x3_net; |
---|
| 4480 | data_in_x4 <= data_in_x4_net; |
---|
| 4481 | data_in_x5 <= data_in_x5_net; |
---|
| 4482 | data_in_x6 <= data_in_x6_net; |
---|
| 4483 | data_in_x7 <= data_in_x7_net; |
---|
| 4484 | data_in_x8 <= data_in_x8_net; |
---|
| 4485 | data_in_x9 <= from_register2_data_out_net_x0; |
---|
| 4486 | en <= en_net; |
---|
| 4487 | en_x0 <= en_x0_net; |
---|
| 4488 | en_x1 <= en_x1_net; |
---|
| 4489 | en_x2 <= en_x2_net; |
---|
| 4490 | en_x3 <= en_x3_net; |
---|
| 4491 | en_x4 <= en_x4_net; |
---|
| 4492 | en_x5 <= en_x5_net; |
---|
| 4493 | en_x6 <= en_x6_net; |
---|
| 4494 | en_x7 <= en_x7_net; |
---|
| 4495 | en_x8 <= en_x8_net; |
---|
| 4496 | en_x9 <= en_x9_net; |
---|
| 4497 | sl_addrack <= sl_addrack_net; |
---|
| 4498 | sl_rdcomp <= sl_rdcomp_net; |
---|
| 4499 | sl_rddack <= sl_rddack_net; |
---|
| 4500 | sl_rddbus <= sl_rddbus_net; |
---|
| 4501 | sl_wait <= sl_wait_net; |
---|
| 4502 | sl_wrcomp <= sl_wrdack_x1; |
---|
| 4503 | sl_wrdack <= sl_wrdack_x1; |
---|
| 4504 | timer0_active <= timer0_active_net; |
---|
| 4505 | timer1_active <= timer1_active_net; |
---|
| 4506 | timer2_active <= timer2_active_net; |
---|
| 4507 | timer3_active <= timer3_active_net; |
---|
| 4508 | timerexpire <= timerexpire_net; |
---|
| 4509 | |
---|
| 4510 | concat: entity work.concat_a1e126f11c |
---|
| 4511 | port map ( |
---|
| 4512 | ce => '0', |
---|
| 4513 | clk => '0', |
---|
| 4514 | clr => '0', |
---|
| 4515 | in0 => convert3_dout_net, |
---|
| 4516 | in1 => convert2_dout_net, |
---|
| 4517 | in2 => convert1_dout_net, |
---|
| 4518 | in3 => convert_dout_net, |
---|
| 4519 | y => data_in_x3_net |
---|
| 4520 | ); |
---|
| 4521 | |
---|
| 4522 | concat1: entity work.concat_09e13b86e0 |
---|
| 4523 | port map ( |
---|
| 4524 | ce => '0', |
---|
| 4525 | clk => '0', |
---|
| 4526 | clr => '0', |
---|
| 4527 | in0(0) => logical4_y_net_x0, |
---|
| 4528 | in1(0) => timer0_active_net, |
---|
| 4529 | in2(0) => register_q_net_x3, |
---|
| 4530 | y => concat1_y_net |
---|
| 4531 | ); |
---|
| 4532 | |
---|
| 4533 | concat2: entity work.concat_09e13b86e0 |
---|
| 4534 | port map ( |
---|
| 4535 | ce => '0', |
---|
| 4536 | clk => '0', |
---|
| 4537 | clr => '0', |
---|
| 4538 | in0(0) => logical4_y_net_x1, |
---|
| 4539 | in1(0) => timer1_active_net, |
---|
| 4540 | in2(0) => register_q_net_x5, |
---|
| 4541 | y => concat2_y_net |
---|
| 4542 | ); |
---|
| 4543 | |
---|
| 4544 | concat3: entity work.concat_09e13b86e0 |
---|
| 4545 | port map ( |
---|
| 4546 | ce => '0', |
---|
| 4547 | clk => '0', |
---|
| 4548 | clr => '0', |
---|
| 4549 | in0(0) => logical4_y_net_x2, |
---|
| 4550 | in1(0) => timer2_active_net, |
---|
| 4551 | in2(0) => register_q_net_x7, |
---|
| 4552 | y => concat3_y_net |
---|
| 4553 | ); |
---|
| 4554 | |
---|
| 4555 | concat4: entity work.concat_09e13b86e0 |
---|
| 4556 | port map ( |
---|
| 4557 | ce => '0', |
---|
| 4558 | clk => '0', |
---|
| 4559 | clr => '0', |
---|
| 4560 | in0(0) => logical4_y_net_x3, |
---|
| 4561 | in1(0) => timer3_active_net, |
---|
| 4562 | in2(0) => register_q_net_x9, |
---|
| 4563 | y => concat4_y_net |
---|
| 4564 | ); |
---|
| 4565 | |
---|
| 4566 | constant1: entity work.constant_6293007044 |
---|
| 4567 | port map ( |
---|
| 4568 | ce => '0', |
---|
| 4569 | clk => '0', |
---|
| 4570 | clr => '0', |
---|
| 4571 | op(0) => en_net |
---|
| 4572 | ); |
---|
| 4573 | |
---|
| 4574 | constant2: entity work.constant_6293007044 |
---|
| 4575 | port map ( |
---|
| 4576 | ce => '0', |
---|
| 4577 | clk => '0', |
---|
| 4578 | clr => '0', |
---|
| 4579 | op(0) => en_x0_net |
---|
| 4580 | ); |
---|
| 4581 | |
---|
| 4582 | constant3: entity work.constant_6293007044 |
---|
| 4583 | port map ( |
---|
| 4584 | ce => '0', |
---|
| 4585 | clk => '0', |
---|
| 4586 | clr => '0', |
---|
| 4587 | op(0) => en_x1_net |
---|
| 4588 | ); |
---|
| 4589 | |
---|
| 4590 | constant4: entity work.constant_6293007044 |
---|
| 4591 | port map ( |
---|
| 4592 | ce => '0', |
---|
| 4593 | clk => '0', |
---|
| 4594 | clr => '0', |
---|
| 4595 | op(0) => en_x2_net |
---|
| 4596 | ); |
---|
| 4597 | |
---|
| 4598 | constant5: entity work.constant_6293007044 |
---|
| 4599 | port map ( |
---|
| 4600 | ce => '0', |
---|
| 4601 | clk => '0', |
---|
| 4602 | clr => '0', |
---|
| 4603 | op(0) => en_x3_net |
---|
| 4604 | ); |
---|
| 4605 | |
---|
| 4606 | convert: entity work.xlconvert |
---|
| 4607 | generic map ( |
---|
| 4608 | bool_conversion => 0, |
---|
| 4609 | din_arith => 1, |
---|
| 4610 | din_bin_pt => 0, |
---|
| 4611 | din_width => 3, |
---|
| 4612 | dout_arith => 1, |
---|
| 4613 | dout_bin_pt => 0, |
---|
| 4614 | dout_width => 8, |
---|
| 4615 | latency => 0, |
---|
| 4616 | overflow => xlWrap, |
---|
| 4617 | quantization => xlTruncate |
---|
| 4618 | ) |
---|
| 4619 | port map ( |
---|
| 4620 | ce => '0', |
---|
| 4621 | clk => '0', |
---|
| 4622 | clr => '0', |
---|
| 4623 | din => concat1_y_net, |
---|
| 4624 | dout => convert_dout_net |
---|
| 4625 | ); |
---|
| 4626 | |
---|
| 4627 | convert1: entity work.xlconvert |
---|
| 4628 | generic map ( |
---|
| 4629 | bool_conversion => 0, |
---|
| 4630 | din_arith => 1, |
---|
| 4631 | din_bin_pt => 0, |
---|
| 4632 | din_width => 3, |
---|
| 4633 | dout_arith => 1, |
---|
| 4634 | dout_bin_pt => 0, |
---|
| 4635 | dout_width => 8, |
---|
| 4636 | latency => 0, |
---|
| 4637 | overflow => xlWrap, |
---|
| 4638 | quantization => xlTruncate |
---|
| 4639 | ) |
---|
| 4640 | port map ( |
---|
| 4641 | ce => '0', |
---|
| 4642 | clk => '0', |
---|
| 4643 | clr => '0', |
---|
| 4644 | din => concat2_y_net, |
---|
| 4645 | dout => convert1_dout_net |
---|
| 4646 | ); |
---|
| 4647 | |
---|
| 4648 | convert2: entity work.xlconvert |
---|
| 4649 | generic map ( |
---|
| 4650 | bool_conversion => 0, |
---|
| 4651 | din_arith => 1, |
---|
| 4652 | din_bin_pt => 0, |
---|
| 4653 | din_width => 3, |
---|
| 4654 | dout_arith => 1, |
---|
| 4655 | dout_bin_pt => 0, |
---|
| 4656 | dout_width => 8, |
---|
| 4657 | latency => 0, |
---|
| 4658 | overflow => xlWrap, |
---|
| 4659 | quantization => xlTruncate |
---|
| 4660 | ) |
---|
| 4661 | port map ( |
---|
| 4662 | ce => '0', |
---|
| 4663 | clk => '0', |
---|
| 4664 | clr => '0', |
---|
| 4665 | din => concat3_y_net, |
---|
| 4666 | dout => convert2_dout_net |
---|
| 4667 | ); |
---|
| 4668 | |
---|
| 4669 | convert3: entity work.xlconvert |
---|
| 4670 | generic map ( |
---|
| 4671 | bool_conversion => 0, |
---|
| 4672 | din_arith => 1, |
---|
| 4673 | din_bin_pt => 0, |
---|
| 4674 | din_width => 3, |
---|
| 4675 | dout_arith => 1, |
---|
| 4676 | dout_bin_pt => 0, |
---|
| 4677 | dout_width => 8, |
---|
| 4678 | latency => 0, |
---|
| 4679 | overflow => xlWrap, |
---|
| 4680 | quantization => xlTruncate |
---|
| 4681 | ) |
---|
| 4682 | port map ( |
---|
| 4683 | ce => '0', |
---|
| 4684 | clk => '0', |
---|
| 4685 | clr => '0', |
---|
| 4686 | din => concat4_y_net, |
---|
| 4687 | dout => convert3_dout_net |
---|
| 4688 | ); |
---|
| 4689 | |
---|
| 4690 | edk_processor_cddda35d8e: entity work.edk_processor_entity_cddda35d8e |
---|
| 4691 | port map ( |
---|
| 4692 | ce_1 => ce_1_sg_x21, |
---|
| 4693 | clk_1 => clk_1_sg_x21, |
---|
| 4694 | from_register => data_out_x3_net, |
---|
| 4695 | from_register1 => data_out_x4_net, |
---|
| 4696 | from_register2 => data_out_x5_net, |
---|
| 4697 | from_register3 => data_out_x6_net, |
---|
| 4698 | from_register4 => data_out_x7_net, |
---|
| 4699 | from_register5 => data_out_x8_net, |
---|
| 4700 | plb_abus => plb_abus_net, |
---|
| 4701 | plb_pavalid => plb_pavalid_net, |
---|
| 4702 | plb_rnw => plb_rnw_net, |
---|
| 4703 | plb_wrdbus => plb_wrdbus_net, |
---|
| 4704 | sg_plb_addrpref => sg_plb_addrpref_net, |
---|
| 4705 | splb_rst => splb_rst_net, |
---|
| 4706 | to_register => dout_x4_net, |
---|
| 4707 | to_register1 => dout_x5_net, |
---|
| 4708 | to_register2 => dout_x6_net, |
---|
| 4709 | to_register3 => dout_x7_net, |
---|
| 4710 | to_register4 => dout_x8_net, |
---|
| 4711 | constant5_x0 => sl_wait_net, |
---|
| 4712 | plb_decode_x0 => sl_addrack_net, |
---|
| 4713 | plb_decode_x1 => sl_rdcomp_net, |
---|
| 4714 | plb_decode_x2 => sl_wrdack_x1, |
---|
| 4715 | plb_decode_x3 => sl_rddack_net, |
---|
| 4716 | plb_decode_x4 => sl_rddbus_net, |
---|
| 4717 | plb_memmap_x0 => data_in_x4_net, |
---|
| 4718 | plb_memmap_x1 => en_x4_net, |
---|
| 4719 | plb_memmap_x2 => data_in_x5_net, |
---|
| 4720 | plb_memmap_x3 => en_x5_net, |
---|
| 4721 | plb_memmap_x4 => data_in_x6_net, |
---|
| 4722 | plb_memmap_x5 => en_x6_net, |
---|
| 4723 | plb_memmap_x6 => data_in_x7_net, |
---|
| 4724 | plb_memmap_x7 => en_x7_net, |
---|
| 4725 | plb_memmap_x8 => data_in_x8_net, |
---|
| 4726 | plb_memmap_x9 => en_x8_net |
---|
| 4727 | ); |
---|
| 4728 | |
---|
| 4729 | logical: entity work.logical_a6d07705dd |
---|
| 4730 | port map ( |
---|
| 4731 | ce => '0', |
---|
| 4732 | clk => '0', |
---|
| 4733 | clr => '0', |
---|
| 4734 | d0(0) => register_q_net_x3, |
---|
| 4735 | d1(0) => register_q_net_x5, |
---|
| 4736 | d2(0) => register_q_net_x7, |
---|
| 4737 | d3(0) => register_q_net_x9, |
---|
| 4738 | y(0) => timerexpire_net |
---|
| 4739 | ); |
---|
| 4740 | |
---|
| 4741 | slice: entity work.xlslice |
---|
| 4742 | generic map ( |
---|
| 4743 | new_lsb => 0, |
---|
| 4744 | new_msb => 0, |
---|
| 4745 | x_width => 32, |
---|
| 4746 | y_width => 1 |
---|
| 4747 | ) |
---|
| 4748 | port map ( |
---|
| 4749 | x => from_register2_data_out_net_x0, |
---|
| 4750 | y(0) => slice_y_net_x1 |
---|
| 4751 | ); |
---|
| 4752 | |
---|
| 4753 | slice1: entity work.xlslice |
---|
| 4754 | generic map ( |
---|
| 4755 | new_lsb => 1, |
---|
| 4756 | new_msb => 1, |
---|
| 4757 | x_width => 32, |
---|
| 4758 | y_width => 1 |
---|
| 4759 | ) |
---|
| 4760 | port map ( |
---|
| 4761 | x => from_register2_data_out_net_x0, |
---|
| 4762 | y(0) => slice1_y_net_x0 |
---|
| 4763 | ); |
---|
| 4764 | |
---|
| 4765 | slice10: entity work.xlslice |
---|
| 4766 | generic map ( |
---|
| 4767 | new_lsb => 12, |
---|
| 4768 | new_msb => 12, |
---|
| 4769 | x_width => 32, |
---|
| 4770 | y_width => 1 |
---|
| 4771 | ) |
---|
| 4772 | port map ( |
---|
| 4773 | x => from_register2_data_out_net_x0, |
---|
| 4774 | y(0) => slice10_y_net_x0 |
---|
| 4775 | ); |
---|
| 4776 | |
---|
| 4777 | slice11: entity work.xlslice |
---|
| 4778 | generic map ( |
---|
| 4779 | new_lsb => 13, |
---|
| 4780 | new_msb => 13, |
---|
| 4781 | x_width => 32, |
---|
| 4782 | y_width => 1 |
---|
| 4783 | ) |
---|
| 4784 | port map ( |
---|
| 4785 | x => from_register2_data_out_net_x0, |
---|
| 4786 | y(0) => slice11_y_net_x1 |
---|
| 4787 | ); |
---|
| 4788 | |
---|
| 4789 | slice12: entity work.xlslice |
---|
| 4790 | generic map ( |
---|
| 4791 | new_lsb => 16, |
---|
| 4792 | new_msb => 16, |
---|
| 4793 | x_width => 32, |
---|
| 4794 | y_width => 1 |
---|
| 4795 | ) |
---|
| 4796 | port map ( |
---|
| 4797 | x => from_register2_data_out_net_x0, |
---|
| 4798 | y(0) => slice12_y_net_x1 |
---|
| 4799 | ); |
---|
| 4800 | |
---|
| 4801 | slice13: entity work.xlslice |
---|
| 4802 | generic map ( |
---|
| 4803 | new_lsb => 17, |
---|
| 4804 | new_msb => 17, |
---|
| 4805 | x_width => 32, |
---|
| 4806 | y_width => 1 |
---|
| 4807 | ) |
---|
| 4808 | port map ( |
---|
| 4809 | x => from_register2_data_out_net_x0, |
---|
| 4810 | y(0) => slice13_y_net_x0 |
---|
| 4811 | ); |
---|
| 4812 | |
---|
| 4813 | slice14: entity work.xlslice |
---|
| 4814 | generic map ( |
---|
| 4815 | new_lsb => 18, |
---|
| 4816 | new_msb => 18, |
---|
| 4817 | x_width => 32, |
---|
| 4818 | y_width => 1 |
---|
| 4819 | ) |
---|
| 4820 | port map ( |
---|
| 4821 | x => from_register2_data_out_net_x0, |
---|
| 4822 | y(0) => slice14_y_net_x1 |
---|
| 4823 | ); |
---|
| 4824 | |
---|
| 4825 | slice15: entity work.xlslice |
---|
| 4826 | generic map ( |
---|
| 4827 | new_lsb => 19, |
---|
| 4828 | new_msb => 19, |
---|
| 4829 | x_width => 32, |
---|
| 4830 | y_width => 1 |
---|
| 4831 | ) |
---|
| 4832 | port map ( |
---|
| 4833 | x => from_register2_data_out_net_x0, |
---|
| 4834 | y(0) => slice15_y_net_x0 |
---|
| 4835 | ); |
---|
| 4836 | |
---|
| 4837 | slice16: entity work.xlslice |
---|
| 4838 | generic map ( |
---|
| 4839 | new_lsb => 20, |
---|
| 4840 | new_msb => 20, |
---|
| 4841 | x_width => 32, |
---|
| 4842 | y_width => 1 |
---|
| 4843 | ) |
---|
| 4844 | port map ( |
---|
| 4845 | x => from_register2_data_out_net_x0, |
---|
| 4846 | y(0) => slice16_y_net_x0 |
---|
| 4847 | ); |
---|
| 4848 | |
---|
| 4849 | slice17: entity work.xlslice |
---|
| 4850 | generic map ( |
---|
| 4851 | new_lsb => 21, |
---|
| 4852 | new_msb => 21, |
---|
| 4853 | x_width => 32, |
---|
| 4854 | y_width => 1 |
---|
| 4855 | ) |
---|
| 4856 | port map ( |
---|
| 4857 | x => from_register2_data_out_net_x0, |
---|
| 4858 | y(0) => slice17_y_net_x1 |
---|
| 4859 | ); |
---|
| 4860 | |
---|
| 4861 | slice18: entity work.xlslice |
---|
| 4862 | generic map ( |
---|
| 4863 | new_lsb => 24, |
---|
| 4864 | new_msb => 24, |
---|
| 4865 | x_width => 32, |
---|
| 4866 | y_width => 1 |
---|
| 4867 | ) |
---|
| 4868 | port map ( |
---|
| 4869 | x => from_register2_data_out_net_x0, |
---|
| 4870 | y(0) => slice18_y_net_x1 |
---|
| 4871 | ); |
---|
| 4872 | |
---|
| 4873 | slice19: entity work.xlslice |
---|
| 4874 | generic map ( |
---|
| 4875 | new_lsb => 25, |
---|
| 4876 | new_msb => 25, |
---|
| 4877 | x_width => 32, |
---|
| 4878 | y_width => 1 |
---|
| 4879 | ) |
---|
| 4880 | port map ( |
---|
| 4881 | x => from_register2_data_out_net_x0, |
---|
| 4882 | y(0) => slice19_y_net_x0 |
---|
| 4883 | ); |
---|
| 4884 | |
---|
| 4885 | slice2: entity work.xlslice |
---|
| 4886 | generic map ( |
---|
| 4887 | new_lsb => 2, |
---|
| 4888 | new_msb => 2, |
---|
| 4889 | x_width => 32, |
---|
| 4890 | y_width => 1 |
---|
| 4891 | ) |
---|
| 4892 | port map ( |
---|
| 4893 | x => from_register2_data_out_net_x0, |
---|
| 4894 | y(0) => slice2_y_net_x1 |
---|
| 4895 | ); |
---|
| 4896 | |
---|
| 4897 | slice20: entity work.xlslice |
---|
| 4898 | generic map ( |
---|
| 4899 | new_lsb => 26, |
---|
| 4900 | new_msb => 26, |
---|
| 4901 | x_width => 32, |
---|
| 4902 | y_width => 1 |
---|
| 4903 | ) |
---|
| 4904 | port map ( |
---|
| 4905 | x => from_register2_data_out_net_x0, |
---|
| 4906 | y(0) => slice20_y_net_x1 |
---|
| 4907 | ); |
---|
| 4908 | |
---|
| 4909 | slice21: entity work.xlslice |
---|
| 4910 | generic map ( |
---|
| 4911 | new_lsb => 27, |
---|
| 4912 | new_msb => 27, |
---|
| 4913 | x_width => 32, |
---|
| 4914 | y_width => 1 |
---|
| 4915 | ) |
---|
| 4916 | port map ( |
---|
| 4917 | x => from_register2_data_out_net_x0, |
---|
| 4918 | y(0) => slice21_y_net_x0 |
---|
| 4919 | ); |
---|
| 4920 | |
---|
| 4921 | slice22: entity work.xlslice |
---|
| 4922 | generic map ( |
---|
| 4923 | new_lsb => 28, |
---|
| 4924 | new_msb => 28, |
---|
| 4925 | x_width => 32, |
---|
| 4926 | y_width => 1 |
---|
| 4927 | ) |
---|
| 4928 | port map ( |
---|
| 4929 | x => from_register2_data_out_net_x0, |
---|
| 4930 | y(0) => slice22_y_net_x0 |
---|
| 4931 | ); |
---|
| 4932 | |
---|
| 4933 | slice23: entity work.xlslice |
---|
| 4934 | generic map ( |
---|
| 4935 | new_lsb => 29, |
---|
| 4936 | new_msb => 29, |
---|
| 4937 | x_width => 32, |
---|
| 4938 | y_width => 1 |
---|
| 4939 | ) |
---|
| 4940 | port map ( |
---|
| 4941 | x => from_register2_data_out_net_x0, |
---|
| 4942 | y(0) => slice23_y_net_x1 |
---|
| 4943 | ); |
---|
| 4944 | |
---|
| 4945 | slice3: entity work.xlslice |
---|
| 4946 | generic map ( |
---|
| 4947 | new_lsb => 3, |
---|
| 4948 | new_msb => 3, |
---|
| 4949 | x_width => 32, |
---|
| 4950 | y_width => 1 |
---|
| 4951 | ) |
---|
| 4952 | port map ( |
---|
| 4953 | x => from_register2_data_out_net_x0, |
---|
| 4954 | y(0) => slice3_y_net_x0 |
---|
| 4955 | ); |
---|
| 4956 | |
---|
| 4957 | slice4: entity work.xlslice |
---|
| 4958 | generic map ( |
---|
| 4959 | new_lsb => 4, |
---|
| 4960 | new_msb => 4, |
---|
| 4961 | x_width => 32, |
---|
| 4962 | y_width => 1 |
---|
| 4963 | ) |
---|
| 4964 | port map ( |
---|
| 4965 | x => from_register2_data_out_net_x0, |
---|
| 4966 | y(0) => slice4_y_net_x0 |
---|
| 4967 | ); |
---|
| 4968 | |
---|
| 4969 | slice5: entity work.xlslice |
---|
| 4970 | generic map ( |
---|
| 4971 | new_lsb => 5, |
---|
| 4972 | new_msb => 5, |
---|
| 4973 | x_width => 32, |
---|
| 4974 | y_width => 1 |
---|
| 4975 | ) |
---|
| 4976 | port map ( |
---|
| 4977 | x => from_register2_data_out_net_x0, |
---|
| 4978 | y(0) => slice5_y_net_x1 |
---|
| 4979 | ); |
---|
| 4980 | |
---|
| 4981 | slice6: entity work.xlslice |
---|
| 4982 | generic map ( |
---|
| 4983 | new_lsb => 8, |
---|
| 4984 | new_msb => 8, |
---|
| 4985 | x_width => 32, |
---|
| 4986 | y_width => 1 |
---|
| 4987 | ) |
---|
| 4988 | port map ( |
---|
| 4989 | x => from_register2_data_out_net_x0, |
---|
| 4990 | y(0) => slice6_y_net_x1 |
---|
| 4991 | ); |
---|
| 4992 | |
---|
| 4993 | slice7: entity work.xlslice |
---|
| 4994 | generic map ( |
---|
| 4995 | new_lsb => 9, |
---|
| 4996 | new_msb => 9, |
---|
| 4997 | x_width => 32, |
---|
| 4998 | y_width => 1 |
---|
| 4999 | ) |
---|
| 5000 | port map ( |
---|
| 5001 | x => from_register2_data_out_net_x0, |
---|
| 5002 | y(0) => slice7_y_net_x0 |
---|
| 5003 | ); |
---|
| 5004 | |
---|
| 5005 | slice8: entity work.xlslice |
---|
| 5006 | generic map ( |
---|
| 5007 | new_lsb => 10, |
---|
| 5008 | new_msb => 10, |
---|
| 5009 | x_width => 32, |
---|
| 5010 | y_width => 1 |
---|
| 5011 | ) |
---|
| 5012 | port map ( |
---|
| 5013 | x => from_register2_data_out_net_x0, |
---|
| 5014 | y(0) => slice8_y_net_x1 |
---|
| 5015 | ); |
---|
| 5016 | |
---|
| 5017 | slice9: entity work.xlslice |
---|
| 5018 | generic map ( |
---|
| 5019 | new_lsb => 11, |
---|
| 5020 | new_msb => 11, |
---|
| 5021 | x_width => 32, |
---|
| 5022 | y_width => 1 |
---|
| 5023 | ) |
---|
| 5024 | port map ( |
---|
| 5025 | x => from_register2_data_out_net_x0, |
---|
| 5026 | y(0) => slice9_y_net_x0 |
---|
| 5027 | ); |
---|
| 5028 | |
---|
| 5029 | timer1_a9ea58dee7: entity work.timer_entity_fee90fe8e7 |
---|
| 5030 | port map ( |
---|
| 5031 | ce_1 => ce_1_sg_x21, |
---|
| 5032 | clk_1 => clk_1_sg_x21, |
---|
| 5033 | countto => data_out_x0_net, |
---|
| 5034 | idlefordifs_inp => idlefordifs_net, |
---|
| 5035 | interruptreset => slice11_y_net_x1, |
---|
| 5036 | mode => slice10_y_net_x0, |
---|
| 5037 | pause => slice9_y_net_x0, |
---|
| 5038 | resume => slice8_y_net_x1, |
---|
| 5039 | start => slice6_y_net_x1, |
---|
| 5040 | stop => slice7_y_net_x0, |
---|
| 5041 | active => timer1_active_net, |
---|
| 5042 | interrupt => register_q_net_x5, |
---|
| 5043 | paused => logical4_y_net_x1, |
---|
| 5044 | timeleft => data_in_x0_net |
---|
| 5045 | ); |
---|
| 5046 | |
---|
| 5047 | timer2_15928ecc3b: entity work.timer_entity_fee90fe8e7 |
---|
| 5048 | port map ( |
---|
| 5049 | ce_1 => ce_1_sg_x21, |
---|
| 5050 | clk_1 => clk_1_sg_x21, |
---|
| 5051 | countto => data_out_x1_net, |
---|
| 5052 | idlefordifs_inp => idlefordifs_net, |
---|
| 5053 | interruptreset => slice17_y_net_x1, |
---|
| 5054 | mode => slice16_y_net_x0, |
---|
| 5055 | pause => slice15_y_net_x0, |
---|
| 5056 | resume => slice14_y_net_x1, |
---|
| 5057 | start => slice12_y_net_x1, |
---|
| 5058 | stop => slice13_y_net_x0, |
---|
| 5059 | active => timer2_active_net, |
---|
| 5060 | interrupt => register_q_net_x7, |
---|
| 5061 | paused => logical4_y_net_x2, |
---|
| 5062 | timeleft => data_in_x1_net |
---|
| 5063 | ); |
---|
| 5064 | |
---|
| 5065 | timer3_4ea9afe7c4: entity work.timer_entity_fee90fe8e7 |
---|
| 5066 | port map ( |
---|
| 5067 | ce_1 => ce_1_sg_x21, |
---|
| 5068 | clk_1 => clk_1_sg_x21, |
---|
| 5069 | countto => data_out_x2_net, |
---|
| 5070 | idlefordifs_inp => idlefordifs_net, |
---|
| 5071 | interruptreset => slice23_y_net_x1, |
---|
| 5072 | mode => slice22_y_net_x0, |
---|
| 5073 | pause => slice21_y_net_x0, |
---|
| 5074 | resume => slice20_y_net_x1, |
---|
| 5075 | start => slice18_y_net_x1, |
---|
| 5076 | stop => slice19_y_net_x0, |
---|
| 5077 | active => timer3_active_net, |
---|
| 5078 | interrupt => register_q_net_x9, |
---|
| 5079 | paused => logical4_y_net_x3, |
---|
| 5080 | timeleft => data_in_x2_net |
---|
| 5081 | ); |
---|
| 5082 | |
---|
| 5083 | timer_control_09b11c57d8: entity work.timer_control_entity_09b11c57d8 |
---|
| 5084 | port map ( |
---|
| 5085 | constant6_x0 => en_x9_net |
---|
| 5086 | ); |
---|
| 5087 | |
---|
| 5088 | timer_fee90fe8e7: entity work.timer_entity_fee90fe8e7 |
---|
| 5089 | port map ( |
---|
| 5090 | ce_1 => ce_1_sg_x21, |
---|
| 5091 | clk_1 => clk_1_sg_x21, |
---|
| 5092 | countto => data_out_net, |
---|
| 5093 | idlefordifs_inp => idlefordifs_net, |
---|
| 5094 | interruptreset => slice5_y_net_x1, |
---|
| 5095 | mode => slice4_y_net_x0, |
---|
| 5096 | pause => slice3_y_net_x0, |
---|
| 5097 | resume => slice2_y_net_x1, |
---|
| 5098 | start => slice_y_net_x1, |
---|
| 5099 | stop => slice1_y_net_x0, |
---|
| 5100 | active => timer0_active_net, |
---|
| 5101 | interrupt => register_q_net_x3, |
---|
| 5102 | paused => logical4_y_net_x0, |
---|
| 5103 | timeleft => data_in_net |
---|
| 5104 | ); |
---|
| 5105 | |
---|
| 5106 | end structural; |
---|
| 5107 | |
---|
| 5108 | ------------------------------------------------------------------- |
---|
| 5109 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 5110 | -- |
---|
| 5111 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 5112 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 5113 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 5114 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 5115 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 5116 | -- this text/file solely for design, simulation, implementation and |
---|
| 5117 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 5118 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 5119 | -- and immediately terminates your license unless covered by a separate |
---|
| 5120 | -- agreement. |
---|
| 5121 | -- |
---|
| 5122 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 5123 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 5124 | -- providing this design, code, or information as one possible |
---|
| 5125 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 5126 | -- making no representation that this implementation is free from any |
---|
| 5127 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 5128 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 5129 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 5130 | -- implementation, including but not limited to warranties of |
---|
| 5131 | -- merchantability or fitness for a particular purpose. |
---|
| 5132 | -- |
---|
| 5133 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 5134 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 5135 | -- |
---|
| 5136 | -- Any modifications that are made to the source code are done at the user's |
---|
| 5137 | -- sole risk and will be unsupported. |
---|
| 5138 | -- |
---|
| 5139 | -- This copyright and support notice must be retained as part of this |
---|
| 5140 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 5141 | -- reserved. |
---|
| 5142 | ------------------------------------------------------------------- |
---|
| 5143 | |
---|
| 5144 | ------------------------------------------------------------------- |
---|
| 5145 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 5146 | -- |
---|
| 5147 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 5148 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 5149 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 5150 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 5151 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 5152 | -- this text/file solely for design, simulation, implementation and |
---|
| 5153 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 5154 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 5155 | -- and immediately terminates your license unless covered by a separate |
---|
| 5156 | -- agreement. |
---|
| 5157 | -- |
---|
| 5158 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 5159 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 5160 | -- providing this design, code, or information as one possible |
---|
| 5161 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 5162 | -- making no representation that this implementation is free from any |
---|
| 5163 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 5164 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 5165 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 5166 | -- implementation, including but not limited to warranties of |
---|
| 5167 | -- merchantability or fitness for a particular purpose. |
---|
| 5168 | -- |
---|
| 5169 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 5170 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 5171 | -- |
---|
| 5172 | -- Any modifications that are made to the source code are done at the user's |
---|
| 5173 | -- sole risk and will be unsupported. |
---|
| 5174 | -- |
---|
| 5175 | -- This copyright and support notice must be retained as part of this |
---|
| 5176 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 5177 | -- reserved. |
---|
| 5178 | ------------------------------------------------------------------- |
---|
| 5179 | library IEEE; |
---|
| 5180 | use IEEE.std_logic_1164.all; |
---|
| 5181 | use work.conv_pkg.all; |
---|
| 5182 | use work.clock_pkg.all; |
---|
| 5183 | entity xlclkprobe is |
---|
| 5184 | port (clk : in std_logic; |
---|
| 5185 | clr : in std_logic; |
---|
| 5186 | ce : in std_logic; |
---|
| 5187 | fakeOutForXst : out std_logic); |
---|
| 5188 | end xlclkprobe; |
---|
| 5189 | architecture behavior of xlclkprobe is |
---|
| 5190 | begin |
---|
| 5191 | fakeOutForXst <= '0'; |
---|
| 5192 | -- synopsys translate_off |
---|
| 5193 | work.clock_pkg.int_clk <= clk; |
---|
| 5194 | -- synopsys translate_on |
---|
| 5195 | end behavior; |
---|
| 5196 | |
---|
| 5197 | ------------------------------------------------------------------- |
---|
| 5198 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 5199 | -- |
---|
| 5200 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 5201 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 5202 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 5203 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 5204 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 5205 | -- this text/file solely for design, simulation, implementation and |
---|
| 5206 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 5207 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 5208 | -- and immediately terminates your license unless covered by a separate |
---|
| 5209 | -- agreement. |
---|
| 5210 | -- |
---|
| 5211 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 5212 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 5213 | -- providing this design, code, or information as one possible |
---|
| 5214 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 5215 | -- making no representation that this implementation is free from any |
---|
| 5216 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 5217 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 5218 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 5219 | -- implementation, including but not limited to warranties of |
---|
| 5220 | -- merchantability or fitness for a particular purpose. |
---|
| 5221 | -- |
---|
| 5222 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 5223 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 5224 | -- |
---|
| 5225 | -- Any modifications that are made to the source code are done at the user's |
---|
| 5226 | -- sole risk and will be unsupported. |
---|
| 5227 | -- |
---|
| 5228 | -- This copyright and support notice must be retained as part of this |
---|
| 5229 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 5230 | -- reserved. |
---|
| 5231 | ------------------------------------------------------------------- |
---|
| 5232 | library IEEE; |
---|
| 5233 | use IEEE.std_logic_1164.all; |
---|
| 5234 | use IEEE.numeric_std.all; |
---|
| 5235 | use work.conv_pkg.all; |
---|
| 5236 | -- synopsys translate_off |
---|
| 5237 | library unisim; |
---|
| 5238 | use unisim.vcomponents.all; |
---|
| 5239 | -- synopsys translate_on |
---|
| 5240 | entity xlclockdriver is |
---|
| 5241 | generic ( |
---|
| 5242 | period: integer := 2; |
---|
| 5243 | log_2_period: integer := 0; |
---|
| 5244 | pipeline_regs: integer := 5; |
---|
| 5245 | use_bufg: integer := 0 |
---|
| 5246 | ); |
---|
| 5247 | port ( |
---|
| 5248 | sysclk: in std_logic; |
---|
| 5249 | sysclr: in std_logic; |
---|
| 5250 | sysce: in std_logic; |
---|
| 5251 | clk: out std_logic; |
---|
| 5252 | clr: out std_logic; |
---|
| 5253 | ce: out std_logic |
---|
| 5254 | ); |
---|
| 5255 | end xlclockdriver; |
---|
| 5256 | architecture behavior of xlclockdriver is |
---|
| 5257 | component bufg |
---|
| 5258 | port ( |
---|
| 5259 | i: in std_logic; |
---|
| 5260 | o: out std_logic |
---|
| 5261 | ); |
---|
| 5262 | end component; |
---|
| 5263 | component synth_reg_w_init |
---|
| 5264 | generic ( |
---|
| 5265 | width: integer; |
---|
| 5266 | init_index: integer; |
---|
| 5267 | init_value: bit_vector; |
---|
| 5268 | latency: integer |
---|
| 5269 | ); |
---|
| 5270 | port ( |
---|
| 5271 | i: in std_logic_vector(width - 1 downto 0); |
---|
| 5272 | ce: in std_logic; |
---|
| 5273 | clr: in std_logic; |
---|
| 5274 | clk: in std_logic; |
---|
| 5275 | o: out std_logic_vector(width - 1 downto 0) |
---|
| 5276 | ); |
---|
| 5277 | end component; |
---|
| 5278 | function size_of_uint(inp: integer; power_of_2: boolean) |
---|
| 5279 | return integer |
---|
| 5280 | is |
---|
| 5281 | constant inp_vec: std_logic_vector(31 downto 0) := |
---|
| 5282 | integer_to_std_logic_vector(inp,32, xlUnsigned); |
---|
| 5283 | variable result: integer; |
---|
| 5284 | begin |
---|
| 5285 | result := 32; |
---|
| 5286 | for i in 0 to 31 loop |
---|
| 5287 | if inp_vec(i) = '1' then |
---|
| 5288 | result := i; |
---|
| 5289 | end if; |
---|
| 5290 | end loop; |
---|
| 5291 | if power_of_2 then |
---|
| 5292 | return result; |
---|
| 5293 | else |
---|
| 5294 | return result+1; |
---|
| 5295 | end if; |
---|
| 5296 | end; |
---|
| 5297 | function is_power_of_2(inp: std_logic_vector) |
---|
| 5298 | return boolean |
---|
| 5299 | is |
---|
| 5300 | constant width: integer := inp'length; |
---|
| 5301 | variable vec: std_logic_vector(width - 1 downto 0); |
---|
| 5302 | variable single_bit_set: boolean; |
---|
| 5303 | variable more_than_one_bit_set: boolean; |
---|
| 5304 | variable result: boolean; |
---|
| 5305 | begin |
---|
| 5306 | vec := inp; |
---|
| 5307 | single_bit_set := false; |
---|
| 5308 | more_than_one_bit_set := false; |
---|
| 5309 | -- synopsys translate_off |
---|
| 5310 | if (is_XorU(vec)) then |
---|
| 5311 | return false; |
---|
| 5312 | end if; |
---|
| 5313 | -- synopsys translate_on |
---|
| 5314 | if width > 0 then |
---|
| 5315 | for i in 0 to width - 1 loop |
---|
| 5316 | if vec(i) = '1' then |
---|
| 5317 | if single_bit_set then |
---|
| 5318 | more_than_one_bit_set := true; |
---|
| 5319 | end if; |
---|
| 5320 | single_bit_set := true; |
---|
| 5321 | end if; |
---|
| 5322 | end loop; |
---|
| 5323 | end if; |
---|
| 5324 | if (single_bit_set and not(more_than_one_bit_set)) then |
---|
| 5325 | result := true; |
---|
| 5326 | else |
---|
| 5327 | result := false; |
---|
| 5328 | end if; |
---|
| 5329 | return result; |
---|
| 5330 | end; |
---|
| 5331 | function ce_reg_init_val(index, period : integer) |
---|
| 5332 | return integer |
---|
| 5333 | is |
---|
| 5334 | variable result: integer; |
---|
| 5335 | begin |
---|
| 5336 | result := 0; |
---|
| 5337 | if ((index mod period) = 0) then |
---|
| 5338 | result := 1; |
---|
| 5339 | end if; |
---|
| 5340 | return result; |
---|
| 5341 | end; |
---|
| 5342 | function remaining_pipe_regs(num_pipeline_regs, period : integer) |
---|
| 5343 | return integer |
---|
| 5344 | is |
---|
| 5345 | variable factor, result: integer; |
---|
| 5346 | begin |
---|
| 5347 | factor := (num_pipeline_regs / period); |
---|
| 5348 | result := num_pipeline_regs - (period * factor) + 1; |
---|
| 5349 | return result; |
---|
| 5350 | end; |
---|
| 5351 | |
---|
| 5352 | function sg_min(L, R: INTEGER) return INTEGER is |
---|
| 5353 | begin |
---|
| 5354 | if L < R then |
---|
| 5355 | return L; |
---|
| 5356 | else |
---|
| 5357 | return R; |
---|
| 5358 | end if; |
---|
| 5359 | end; |
---|
| 5360 | constant max_pipeline_regs : integer := 8; |
---|
| 5361 | constant pipe_regs : integer := 5; |
---|
| 5362 | constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); |
---|
| 5363 | constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); |
---|
| 5364 | constant period_floor: integer := max(2, period); |
---|
| 5365 | constant power_of_2_counter: boolean := |
---|
| 5366 | is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); |
---|
| 5367 | constant cnt_width: integer := |
---|
| 5368 | size_of_uint(period_floor, power_of_2_counter); |
---|
| 5369 | constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := |
---|
| 5370 | integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); |
---|
| 5371 | constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := |
---|
| 5372 | integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); |
---|
| 5373 | constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := |
---|
| 5374 | integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); |
---|
| 5375 | signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); |
---|
| 5376 | signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); |
---|
| 5377 | attribute MAX_FANOUT : string; |
---|
| 5378 | attribute MAX_FANOUT of ce_vec:signal is "REDUCE"; |
---|
| 5379 | signal internal_ce: std_logic_vector(0 downto 0); |
---|
| 5380 | signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); |
---|
| 5381 | begin |
---|
| 5382 | clk <= sysclk; |
---|
| 5383 | clr <= sysclr; |
---|
| 5384 | cntr_gen: process(sysclk) |
---|
| 5385 | begin |
---|
| 5386 | if sysclk'event and sysclk = '1' then |
---|
| 5387 | if (sysce = '1') then |
---|
| 5388 | if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then |
---|
| 5389 | clk_num <= (others => '0'); |
---|
| 5390 | else |
---|
| 5391 | clk_num <= clk_num + 1; |
---|
| 5392 | end if; |
---|
| 5393 | end if; |
---|
| 5394 | end if; |
---|
| 5395 | end process; |
---|
| 5396 | clr_gen: process(clk_num, sysclr) |
---|
| 5397 | begin |
---|
| 5398 | if power_of_2_counter then |
---|
| 5399 | cnt_clr(0) <= sysclr; |
---|
| 5400 | else |
---|
| 5401 | if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 |
---|
| 5402 | or sysclr = '1') then |
---|
| 5403 | cnt_clr(0) <= '1'; |
---|
| 5404 | else |
---|
| 5405 | cnt_clr(0) <= '0'; |
---|
| 5406 | end if; |
---|
| 5407 | end if; |
---|
| 5408 | end process; |
---|
| 5409 | clr_reg: synth_reg_w_init |
---|
| 5410 | generic map ( |
---|
| 5411 | width => 1, |
---|
| 5412 | init_index => 0, |
---|
| 5413 | init_value => b"0000", |
---|
| 5414 | latency => 1 |
---|
| 5415 | ) |
---|
| 5416 | port map ( |
---|
| 5417 | i => cnt_clr, |
---|
| 5418 | ce => sysce, |
---|
| 5419 | clr => sysclr, |
---|
| 5420 | clk => sysclk, |
---|
| 5421 | o => cnt_clr_dly |
---|
| 5422 | ); |
---|
| 5423 | pipelined_ce : if period > 1 generate |
---|
| 5424 | ce_gen: process(clk_num) |
---|
| 5425 | begin |
---|
| 5426 | if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then |
---|
| 5427 | ce_vec(num_pipeline_regs) <= '1'; |
---|
| 5428 | else |
---|
| 5429 | ce_vec(num_pipeline_regs) <= '0'; |
---|
| 5430 | end if; |
---|
| 5431 | end process; |
---|
| 5432 | ce_pipeline: for index in num_pipeline_regs downto 1 generate |
---|
| 5433 | ce_reg : synth_reg_w_init |
---|
| 5434 | generic map ( |
---|
| 5435 | width => 1, |
---|
| 5436 | init_index => ce_reg_init_val(index, period), |
---|
| 5437 | init_value => b"0000", |
---|
| 5438 | latency => 1 |
---|
| 5439 | ) |
---|
| 5440 | port map ( |
---|
| 5441 | i => ce_vec(index downto index), |
---|
| 5442 | ce => sysce, |
---|
| 5443 | clr => sysclr, |
---|
| 5444 | clk => sysclk, |
---|
| 5445 | o => ce_vec(index-1 downto index-1) |
---|
| 5446 | ); |
---|
| 5447 | end generate; |
---|
| 5448 | internal_ce <= ce_vec(0 downto 0); |
---|
| 5449 | end generate; |
---|
| 5450 | use_bufg_true: if period > 1 and use_bufg = 1 generate |
---|
| 5451 | ce_bufg_inst: bufg |
---|
| 5452 | port map ( |
---|
| 5453 | i => internal_ce(0), |
---|
| 5454 | o => ce |
---|
| 5455 | ); |
---|
| 5456 | end generate; |
---|
| 5457 | use_bufg_false: if period > 1 and (use_bufg = 0) generate |
---|
| 5458 | ce <= internal_ce(0); |
---|
| 5459 | end generate; |
---|
| 5460 | generate_system_clk: if period = 1 generate |
---|
| 5461 | ce <= sysce; |
---|
| 5462 | end generate; |
---|
| 5463 | end architecture behavior; |
---|
| 5464 | |
---|
| 5465 | ------------------------------------------------------------------- |
---|
| 5466 | -- System Generator version 10.1.2 VHDL source file. |
---|
| 5467 | -- |
---|
| 5468 | -- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This |
---|
| 5469 | -- text/file contains proprietary, confidential information of Xilinx, |
---|
| 5470 | -- Inc., is distributed under license from Xilinx, Inc., and may be used, |
---|
| 5471 | -- copied and/or disclosed only pursuant to the terms of a valid license |
---|
| 5472 | -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use |
---|
| 5473 | -- this text/file solely for design, simulation, implementation and |
---|
| 5474 | -- creation of design files limited to Xilinx devices or technologies. |
---|
| 5475 | -- Use with non-Xilinx devices or technologies is expressly prohibited |
---|
| 5476 | -- and immediately terminates your license unless covered by a separate |
---|
| 5477 | -- agreement. |
---|
| 5478 | -- |
---|
| 5479 | -- Xilinx is providing this design, code, or information "as is" solely |
---|
| 5480 | -- for use in developing programs and solutions for Xilinx devices. By |
---|
| 5481 | -- providing this design, code, or information as one possible |
---|
| 5482 | -- implementation of this feature, application or standard, Xilinx is |
---|
| 5483 | -- making no representation that this implementation is free from any |
---|
| 5484 | -- claims of infringement. You are responsible for obtaining any rights |
---|
| 5485 | -- you may require for your implementation. Xilinx expressly disclaims |
---|
| 5486 | -- any warranty whatsoever with respect to the adequacy of the |
---|
| 5487 | -- implementation, including but not limited to warranties of |
---|
| 5488 | -- merchantability or fitness for a particular purpose. |
---|
| 5489 | -- |
---|
| 5490 | -- Xilinx products are not intended for use in life support appliances, |
---|
| 5491 | -- devices, or systems. Use in such applications is expressly prohibited. |
---|
| 5492 | -- |
---|
| 5493 | -- Any modifications that are made to the source code are done at the user's |
---|
| 5494 | -- sole risk and will be unsupported. |
---|
| 5495 | -- |
---|
| 5496 | -- This copyright and support notice must be retained as part of this |
---|
| 5497 | -- text at all times. (c) Copyright 1995-2008 Xilinx, Inc. All rights |
---|
| 5498 | -- reserved. |
---|
| 5499 | ------------------------------------------------------------------- |
---|
| 5500 | library IEEE; |
---|
| 5501 | use IEEE.std_logic_1164.all; |
---|
| 5502 | entity xland2 is |
---|
| 5503 | port ( |
---|
| 5504 | a : in std_logic; |
---|
| 5505 | b : in std_logic; |
---|
| 5506 | dout : out std_logic |
---|
| 5507 | ); |
---|
| 5508 | end xland2; |
---|
| 5509 | architecture behavior of xland2 is |
---|
| 5510 | begin |
---|
| 5511 | dout <= a and b; |
---|
| 5512 | end behavior; |
---|
| 5513 | library IEEE; |
---|
| 5514 | use IEEE.std_logic_1164.all; |
---|
| 5515 | use work.conv_pkg.all; |
---|
| 5516 | |
---|
| 5517 | entity default_clock_driver is |
---|
| 5518 | port ( |
---|
| 5519 | sysce: in std_logic; |
---|
| 5520 | sysce_clr: in std_logic; |
---|
| 5521 | sysclk: in std_logic; |
---|
| 5522 | ce_1: out std_logic; |
---|
| 5523 | clk_1: out std_logic |
---|
| 5524 | ); |
---|
| 5525 | end default_clock_driver; |
---|
| 5526 | |
---|
| 5527 | architecture structural of default_clock_driver is |
---|
| 5528 | attribute syn_noprune: boolean; |
---|
| 5529 | attribute syn_noprune of structural : architecture is true; |
---|
| 5530 | attribute optimize_primitives: boolean; |
---|
| 5531 | attribute optimize_primitives of structural : architecture is false; |
---|
| 5532 | attribute dont_touch: boolean; |
---|
| 5533 | attribute dont_touch of structural : architecture is true; |
---|
| 5534 | |
---|
| 5535 | signal sysce_clr_x0: std_logic; |
---|
| 5536 | signal sysce_x0: std_logic; |
---|
| 5537 | signal sysclk_x0: std_logic; |
---|
| 5538 | signal xlclockdriver_1_ce: std_logic; |
---|
| 5539 | signal xlclockdriver_1_clk: std_logic; |
---|
| 5540 | |
---|
| 5541 | begin |
---|
| 5542 | sysce_x0 <= sysce; |
---|
| 5543 | sysce_clr_x0 <= sysce_clr; |
---|
| 5544 | sysclk_x0 <= sysclk; |
---|
| 5545 | ce_1 <= xlclockdriver_1_ce; |
---|
| 5546 | clk_1 <= xlclockdriver_1_clk; |
---|
| 5547 | |
---|
| 5548 | xlclockdriver_1: entity work.xlclockdriver |
---|
| 5549 | generic map ( |
---|
| 5550 | log_2_period => 1, |
---|
| 5551 | period => 1, |
---|
| 5552 | use_bufg => 0 |
---|
| 5553 | ) |
---|
| 5554 | port map ( |
---|
| 5555 | sysce => sysce_x0, |
---|
| 5556 | sysclk => sysclk_x0, |
---|
| 5557 | sysclr => sysce_clr_x0, |
---|
| 5558 | ce => xlclockdriver_1_ce, |
---|
| 5559 | clk => xlclockdriver_1_clk |
---|
| 5560 | ); |
---|
| 5561 | |
---|
| 5562 | end structural; |
---|
| 5563 | library IEEE; |
---|
| 5564 | use IEEE.std_logic_1164.all; |
---|
| 5565 | use work.conv_pkg.all; |
---|
| 5566 | |
---|
| 5567 | entity warp_timer_cw is |
---|
| 5568 | port ( |
---|
| 5569 | ce: in std_logic := '1'; |
---|
| 5570 | clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) |
---|
| 5571 | idlefordifs: in std_logic; |
---|
| 5572 | plb_abus: in std_logic_vector(31 downto 0); |
---|
| 5573 | plb_pavalid: in std_logic; |
---|
| 5574 | plb_rnw: in std_logic; |
---|
| 5575 | plb_wrdbus: in std_logic_vector(31 downto 0); |
---|
| 5576 | sg_plb_addrpref: in std_logic_vector(19 downto 0); |
---|
| 5577 | splb_rst: in std_logic; |
---|
| 5578 | sl_addrack: out std_logic; |
---|
| 5579 | sl_rdcomp: out std_logic; |
---|
| 5580 | sl_rddack: out std_logic; |
---|
| 5581 | sl_rddbus: out std_logic_vector(31 downto 0); |
---|
| 5582 | sl_wait: out std_logic; |
---|
| 5583 | sl_wrcomp: out std_logic; |
---|
| 5584 | sl_wrdack: out std_logic; |
---|
| 5585 | timer0_active: out std_logic; |
---|
| 5586 | timer1_active: out std_logic; |
---|
| 5587 | timer2_active: out std_logic; |
---|
| 5588 | timer3_active: out std_logic; |
---|
| 5589 | timerexpire: out std_logic |
---|
| 5590 | ); |
---|
| 5591 | end warp_timer_cw; |
---|
| 5592 | |
---|
| 5593 | architecture structural of warp_timer_cw is |
---|
| 5594 | component xlpersistentdff |
---|
| 5595 | port ( |
---|
| 5596 | clk: in std_logic; |
---|
| 5597 | d: in std_logic; |
---|
| 5598 | q: out std_logic |
---|
| 5599 | ); |
---|
| 5600 | end component; |
---|
| 5601 | attribute syn_black_box: boolean; |
---|
| 5602 | attribute syn_black_box of xlpersistentdff: component is true; |
---|
| 5603 | attribute box_type: string; |
---|
| 5604 | attribute box_type of xlpersistentdff: component is "black_box"; |
---|
| 5605 | attribute syn_noprune: boolean; |
---|
| 5606 | attribute optimize_primitives: boolean; |
---|
| 5607 | attribute dont_touch: boolean; |
---|
| 5608 | attribute syn_noprune of xlpersistentdff: component is true; |
---|
| 5609 | attribute optimize_primitives of xlpersistentdff: component is false; |
---|
| 5610 | attribute dont_touch of xlpersistentdff: component is true; |
---|
| 5611 | |
---|
| 5612 | signal ce_1_sg_x21: std_logic; |
---|
| 5613 | attribute MAX_FANOUT: string; |
---|
| 5614 | attribute MAX_FANOUT of ce_1_sg_x21: signal is "REDUCE"; |
---|
| 5615 | signal clkNet: std_logic; |
---|
| 5616 | signal clk_1_sg_x21: std_logic; |
---|
| 5617 | signal data_in_net: std_logic_vector(31 downto 0); |
---|
| 5618 | signal data_in_x0_net: std_logic_vector(31 downto 0); |
---|
| 5619 | signal data_in_x1_net: std_logic_vector(31 downto 0); |
---|
| 5620 | signal data_in_x2_net: std_logic_vector(31 downto 0); |
---|
| 5621 | signal data_in_x3_net: std_logic_vector(31 downto 0); |
---|
| 5622 | signal data_in_x4_net: std_logic_vector(31 downto 0); |
---|
| 5623 | signal data_in_x5_net: std_logic_vector(31 downto 0); |
---|
| 5624 | signal data_in_x6_net: std_logic_vector(31 downto 0); |
---|
| 5625 | signal data_in_x7_net: std_logic_vector(31 downto 0); |
---|
| 5626 | signal data_in_x8_net: std_logic_vector(31 downto 0); |
---|
| 5627 | signal data_out_net: std_logic_vector(31 downto 0); |
---|
| 5628 | signal data_out_x0_net: std_logic_vector(31 downto 0); |
---|
| 5629 | signal data_out_x1_net: std_logic_vector(31 downto 0); |
---|
| 5630 | signal data_out_x2_net: std_logic_vector(31 downto 0); |
---|
| 5631 | signal data_out_x3_net: std_logic_vector(31 downto 0); |
---|
| 5632 | signal data_out_x4_net: std_logic_vector(31 downto 0); |
---|
| 5633 | signal data_out_x5_net: std_logic_vector(31 downto 0); |
---|
| 5634 | signal data_out_x6_net: std_logic_vector(31 downto 0); |
---|
| 5635 | signal data_out_x7_net: std_logic_vector(31 downto 0); |
---|
| 5636 | signal data_out_x8_net: std_logic_vector(31 downto 0); |
---|
| 5637 | signal en_net: std_logic; |
---|
| 5638 | signal en_x0_net: std_logic; |
---|
| 5639 | signal en_x1_net: std_logic; |
---|
| 5640 | signal en_x2_net: std_logic; |
---|
| 5641 | signal en_x3_net: std_logic; |
---|
| 5642 | signal en_x4_net: std_logic; |
---|
| 5643 | signal en_x5_net: std_logic; |
---|
| 5644 | signal en_x6_net: std_logic; |
---|
| 5645 | signal en_x7_net: std_logic; |
---|
| 5646 | signal en_x8_net: std_logic; |
---|
| 5647 | signal en_x9_net: std_logic; |
---|
| 5648 | signal from_register2_data_out_net_x0: std_logic_vector(31 downto 0); |
---|
| 5649 | signal from_register2_data_out_net_x1: std_logic_vector(31 downto 0); |
---|
| 5650 | signal idlefordifs_net: std_logic; |
---|
| 5651 | signal persistentdff_inst_q: std_logic; |
---|
| 5652 | attribute syn_keep: boolean; |
---|
| 5653 | attribute syn_keep of persistentdff_inst_q: signal is true; |
---|
| 5654 | attribute keep: boolean; |
---|
| 5655 | attribute keep of persistentdff_inst_q: signal is true; |
---|
| 5656 | attribute preserve_signal: boolean; |
---|
| 5657 | attribute preserve_signal of persistentdff_inst_q: signal is true; |
---|
| 5658 | signal plb_abus_net: std_logic_vector(31 downto 0); |
---|
| 5659 | signal plb_pavalid_net: std_logic; |
---|
| 5660 | signal plb_rnw_net: std_logic; |
---|
| 5661 | signal plb_wrdbus_net: std_logic_vector(31 downto 0); |
---|
| 5662 | signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); |
---|
| 5663 | signal sl_addrack_net: std_logic; |
---|
| 5664 | signal sl_rdcomp_net: std_logic; |
---|
| 5665 | signal sl_rddack_net: std_logic; |
---|
| 5666 | signal sl_rddbus_net: std_logic_vector(31 downto 0); |
---|
| 5667 | signal sl_wait_net: std_logic; |
---|
| 5668 | signal sl_wrdack_x1: std_logic; |
---|
| 5669 | signal sl_wrdack_x2: std_logic; |
---|
| 5670 | signal splb_rst_net: std_logic; |
---|
| 5671 | signal timer0_active_net: std_logic; |
---|
| 5672 | signal timer0_countTo_reg_ce: std_logic; |
---|
| 5673 | signal timer0_timeLeft_reg_ce: std_logic; |
---|
| 5674 | signal timer1_active_net: std_logic; |
---|
| 5675 | signal timer1_countTo_reg_ce: std_logic; |
---|
| 5676 | signal timer1_timeLeft_reg_ce: std_logic; |
---|
| 5677 | signal timer2_active_net: std_logic; |
---|
| 5678 | signal timer2_countTo_reg_ce: std_logic; |
---|
| 5679 | signal timer2_timeLeft_reg_ce: std_logic; |
---|
| 5680 | signal timer3_active_net: std_logic; |
---|
| 5681 | signal timer3_countTo_reg_ce: std_logic; |
---|
| 5682 | signal timer3_timeLeft_reg_ce: std_logic; |
---|
| 5683 | signal timer_control_r_reg_ce: std_logic; |
---|
| 5684 | signal timer_control_w_reg_ce: std_logic; |
---|
| 5685 | signal timer_status_reg_ce: std_logic; |
---|
| 5686 | signal timerexpire_net: std_logic; |
---|
| 5687 | |
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| 5688 | begin |
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| 5689 | clkNet <= clk; |
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| 5690 | idlefordifs_net <= idlefordifs; |
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| 5691 | plb_abus_net <= plb_abus; |
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| 5692 | plb_pavalid_net <= plb_pavalid; |
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| 5693 | plb_rnw_net <= plb_rnw; |
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| 5694 | plb_wrdbus_net <= plb_wrdbus; |
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| 5695 | sg_plb_addrpref_net <= sg_plb_addrpref; |
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| 5696 | splb_rst_net <= splb_rst; |
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| 5697 | sl_addrack <= sl_addrack_net; |
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| 5698 | sl_rdcomp <= sl_rdcomp_net; |
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| 5699 | sl_rddack <= sl_rddack_net; |
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| 5700 | sl_rddbus <= sl_rddbus_net; |
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| 5701 | sl_wait <= sl_wait_net; |
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| 5702 | sl_wrcomp <= sl_wrdack_x2; |
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| 5703 | sl_wrdack <= sl_wrdack_x1; |
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| 5704 | timer0_active <= timer0_active_net; |
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| 5705 | timer1_active <= timer1_active_net; |
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| 5706 | timer2_active <= timer2_active_net; |
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| 5707 | timer3_active <= timer3_active_net; |
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| 5708 | timerexpire <= timerexpire_net; |
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| 5709 | |
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| 5710 | clk_probe: entity work.xlclkprobe |
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| 5711 | port map ( |
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| 5712 | ce => '1', |
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| 5713 | clk => clkNet, |
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| 5714 | clr => '0' |
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| 5715 | ); |
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| 5716 | |
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| 5717 | default_clock_driver_x0: entity work.default_clock_driver |
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| 5718 | port map ( |
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| 5719 | sysce => '1', |
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| 5720 | sysce_clr => '0', |
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| 5721 | sysclk => clkNet, |
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| 5722 | ce_1 => ce_1_sg_x21, |
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| 5723 | clk_1 => clk_1_sg_x21 |
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| 5724 | ); |
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| 5725 | |
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| 5726 | persistentdff_inst: xlpersistentdff |
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| 5727 | port map ( |
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| 5728 | clk => clkNet, |
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| 5729 | d => persistentdff_inst_q, |
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| 5730 | q => persistentdff_inst_q |
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| 5731 | ); |
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| 5732 | |
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| 5733 | timer0_countTo: entity work.synth_reg_w_init |
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| 5734 | generic map ( |
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| 5735 | width => 32, |
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| 5736 | init_index => 2, |
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| 5737 | init_value => b"00000000000000000000000000000000", |
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| 5738 | latency => 1 |
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| 5739 | ) |
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| 5740 | port map ( |
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| 5741 | ce => timer0_countTo_reg_ce, |
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| 5742 | clk => clk_1_sg_x21, |
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| 5743 | clr => '0', |
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| 5744 | i => data_in_x4_net, |
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| 5745 | o => data_out_net |
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| 5746 | ); |
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| 5747 | |
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| 5748 | timer0_countTo_ce_and2_comp: entity work.xland2 |
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| 5749 | port map ( |
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| 5750 | a => ce_1_sg_x21, |
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| 5751 | b => en_x4_net, |
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| 5752 | dout => timer0_countTo_reg_ce |
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| 5753 | ); |
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| 5754 | |
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| 5755 | timer0_timeLeft: entity work.synth_reg_w_init |
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| 5756 | generic map ( |
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| 5757 | width => 32, |
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| 5758 | init_index => 2, |
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| 5759 | init_value => b"00000000000000000000000000000000", |
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| 5760 | latency => 1 |
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| 5761 | ) |
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| 5762 | port map ( |
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| 5763 | ce => timer0_timeLeft_reg_ce, |
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| 5764 | clk => clk_1_sg_x21, |
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| 5765 | clr => '0', |
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| 5766 | i => data_in_net, |
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| 5767 | o => data_out_x3_net |
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| 5768 | ); |
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| 5769 | |
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| 5770 | timer0_timeLeft_ce_and2_comp: entity work.xland2 |
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| 5771 | port map ( |
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| 5772 | a => ce_1_sg_x21, |
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| 5773 | b => en_net, |
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| 5774 | dout => timer0_timeLeft_reg_ce |
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| 5775 | ); |
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| 5776 | |
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| 5777 | timer1_countTo: entity work.synth_reg_w_init |
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| 5778 | generic map ( |
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| 5779 | width => 32, |
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| 5780 | init_index => 2, |
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| 5781 | init_value => b"00000000000000000000000000000000", |
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| 5782 | latency => 1 |
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| 5783 | ) |
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| 5784 | port map ( |
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| 5785 | ce => timer1_countTo_reg_ce, |
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| 5786 | clk => clk_1_sg_x21, |
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| 5787 | clr => '0', |
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| 5788 | i => data_in_x5_net, |
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| 5789 | o => data_out_x0_net |
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| 5790 | ); |
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| 5791 | |
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| 5792 | timer1_countTo_ce_and2_comp: entity work.xland2 |
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| 5793 | port map ( |
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| 5794 | a => ce_1_sg_x21, |
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| 5795 | b => en_x5_net, |
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| 5796 | dout => timer1_countTo_reg_ce |
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| 5797 | ); |
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| 5798 | |
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| 5799 | timer1_timeLeft: entity work.synth_reg_w_init |
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| 5800 | generic map ( |
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| 5801 | width => 32, |
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| 5802 | init_index => 2, |
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| 5803 | init_value => b"00000000000000000000000000000000", |
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| 5804 | latency => 1 |
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| 5805 | ) |
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| 5806 | port map ( |
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| 5807 | ce => timer1_timeLeft_reg_ce, |
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| 5808 | clk => clk_1_sg_x21, |
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| 5809 | clr => '0', |
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| 5810 | i => data_in_x0_net, |
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| 5811 | o => data_out_x4_net |
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| 5812 | ); |
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| 5813 | |
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| 5814 | timer1_timeLeft_ce_and2_comp: entity work.xland2 |
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| 5815 | port map ( |
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| 5816 | a => ce_1_sg_x21, |
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| 5817 | b => en_x0_net, |
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| 5818 | dout => timer1_timeLeft_reg_ce |
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| 5819 | ); |
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| 5820 | |
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| 5821 | timer2_countTo: entity work.synth_reg_w_init |
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| 5822 | generic map ( |
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| 5823 | width => 32, |
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| 5824 | init_index => 2, |
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| 5825 | init_value => b"00000000000000000000000000000000", |
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| 5826 | latency => 1 |
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| 5827 | ) |
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| 5828 | port map ( |
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| 5829 | ce => timer2_countTo_reg_ce, |
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| 5830 | clk => clk_1_sg_x21, |
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| 5831 | clr => '0', |
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| 5832 | i => data_in_x6_net, |
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| 5833 | o => data_out_x1_net |
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| 5834 | ); |
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| 5835 | |
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| 5836 | timer2_countTo_ce_and2_comp: entity work.xland2 |
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| 5837 | port map ( |
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| 5838 | a => ce_1_sg_x21, |
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| 5839 | b => en_x6_net, |
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| 5840 | dout => timer2_countTo_reg_ce |
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| 5841 | ); |
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| 5842 | |
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| 5843 | timer2_timeLeft: entity work.synth_reg_w_init |
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| 5844 | generic map ( |
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| 5845 | width => 32, |
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| 5846 | init_index => 2, |
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| 5847 | init_value => b"00000000000000000000000000000000", |
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| 5848 | latency => 1 |
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| 5849 | ) |
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| 5850 | port map ( |
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| 5851 | ce => timer2_timeLeft_reg_ce, |
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| 5852 | clk => clk_1_sg_x21, |
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| 5853 | clr => '0', |
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| 5854 | i => data_in_x1_net, |
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| 5855 | o => data_out_x5_net |
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| 5856 | ); |
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| 5857 | |
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| 5858 | timer2_timeLeft_ce_and2_comp: entity work.xland2 |
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| 5859 | port map ( |
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| 5860 | a => ce_1_sg_x21, |
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| 5861 | b => en_x1_net, |
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| 5862 | dout => timer2_timeLeft_reg_ce |
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| 5863 | ); |
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| 5864 | |
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| 5865 | timer3_countTo: entity work.synth_reg_w_init |
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| 5866 | generic map ( |
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| 5867 | width => 32, |
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| 5868 | init_index => 2, |
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| 5869 | init_value => b"00000000000000000000000000000000", |
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| 5870 | latency => 1 |
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| 5871 | ) |
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| 5872 | port map ( |
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| 5873 | ce => timer3_countTo_reg_ce, |
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| 5874 | clk => clk_1_sg_x21, |
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| 5875 | clr => '0', |
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| 5876 | i => data_in_x7_net, |
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| 5877 | o => data_out_x2_net |
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| 5878 | ); |
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| 5879 | |
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| 5880 | timer3_countTo_ce_and2_comp: entity work.xland2 |
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| 5881 | port map ( |
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| 5882 | a => ce_1_sg_x21, |
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| 5883 | b => en_x7_net, |
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| 5884 | dout => timer3_countTo_reg_ce |
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| 5885 | ); |
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| 5886 | |
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| 5887 | timer3_timeLeft: entity work.synth_reg_w_init |
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| 5888 | generic map ( |
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| 5889 | width => 32, |
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| 5890 | init_index => 2, |
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| 5891 | init_value => b"00000000000000000000000000000000", |
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| 5892 | latency => 1 |
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| 5893 | ) |
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| 5894 | port map ( |
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| 5895 | ce => timer3_timeLeft_reg_ce, |
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| 5896 | clk => clk_1_sg_x21, |
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| 5897 | clr => '0', |
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| 5898 | i => data_in_x2_net, |
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| 5899 | o => data_out_x6_net |
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| 5900 | ); |
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| 5901 | |
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| 5902 | timer3_timeLeft_ce_and2_comp: entity work.xland2 |
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| 5903 | port map ( |
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| 5904 | a => ce_1_sg_x21, |
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| 5905 | b => en_x2_net, |
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| 5906 | dout => timer3_timeLeft_reg_ce |
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| 5907 | ); |
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| 5908 | |
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| 5909 | timer_control_r: entity work.synth_reg_w_init |
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| 5910 | generic map ( |
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| 5911 | width => 32, |
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| 5912 | init_index => 2, |
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| 5913 | init_value => b"00000000000000000000000000000000", |
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| 5914 | latency => 1 |
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| 5915 | ) |
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| 5916 | port map ( |
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| 5917 | ce => timer_control_r_reg_ce, |
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| 5918 | clk => clk_1_sg_x21, |
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| 5919 | clr => '0', |
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| 5920 | i => from_register2_data_out_net_x1, |
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| 5921 | o => data_out_x7_net |
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| 5922 | ); |
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| 5923 | |
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| 5924 | timer_control_r_ce_and2_comp: entity work.xland2 |
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| 5925 | port map ( |
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| 5926 | a => ce_1_sg_x21, |
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| 5927 | b => en_x9_net, |
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| 5928 | dout => timer_control_r_reg_ce |
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| 5929 | ); |
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| 5930 | |
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| 5931 | timer_control_w: entity work.synth_reg_w_init |
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| 5932 | generic map ( |
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| 5933 | width => 32, |
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| 5934 | init_index => 2, |
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| 5935 | init_value => b"00000000000000000000000000000000", |
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| 5936 | latency => 1 |
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| 5937 | ) |
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| 5938 | port map ( |
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| 5939 | ce => timer_control_w_reg_ce, |
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| 5940 | clk => clk_1_sg_x21, |
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| 5941 | clr => '0', |
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| 5942 | i => data_in_x8_net, |
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| 5943 | o => from_register2_data_out_net_x0 |
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| 5944 | ); |
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| 5945 | |
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| 5946 | timer_control_w_ce_and2_comp: entity work.xland2 |
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| 5947 | port map ( |
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| 5948 | a => ce_1_sg_x21, |
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| 5949 | b => en_x8_net, |
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| 5950 | dout => timer_control_w_reg_ce |
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| 5951 | ); |
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| 5952 | |
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| 5953 | timer_status: entity work.synth_reg_w_init |
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| 5954 | generic map ( |
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| 5955 | width => 32, |
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| 5956 | init_index => 2, |
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| 5957 | init_value => b"00000000000000000000000000000000", |
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| 5958 | latency => 1 |
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| 5959 | ) |
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| 5960 | port map ( |
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| 5961 | ce => timer_status_reg_ce, |
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| 5962 | clk => clk_1_sg_x21, |
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| 5963 | clr => '0', |
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| 5964 | i => data_in_x3_net, |
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| 5965 | o => data_out_x8_net |
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| 5966 | ); |
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| 5967 | |
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| 5968 | timer_status_ce_and2_comp: entity work.xland2 |
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| 5969 | port map ( |
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| 5970 | a => ce_1_sg_x21, |
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| 5971 | b => en_x3_net, |
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| 5972 | dout => timer_status_reg_ce |
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| 5973 | ); |
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| 5974 | |
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| 5975 | warp_timer_x0: entity work.warp_timer |
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| 5976 | port map ( |
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| 5977 | ce_1 => ce_1_sg_x21, |
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| 5978 | clk_1 => clk_1_sg_x21, |
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| 5979 | data_out => data_out_net, |
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| 5980 | data_out_x0 => data_out_x0_net, |
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| 5981 | data_out_x1 => data_out_x1_net, |
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| 5982 | data_out_x2 => data_out_x2_net, |
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| 5983 | data_out_x3 => data_out_x3_net, |
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| 5984 | data_out_x4 => data_out_x4_net, |
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| 5985 | data_out_x5 => data_out_x5_net, |
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| 5986 | data_out_x6 => data_out_x6_net, |
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| 5987 | data_out_x7 => data_out_x7_net, |
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| 5988 | data_out_x8 => data_out_x8_net, |
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| 5989 | data_out_x9 => from_register2_data_out_net_x0, |
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| 5990 | dout_x4 => data_out_net, |
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| 5991 | dout_x5 => data_out_x0_net, |
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| 5992 | dout_x6 => data_out_x1_net, |
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| 5993 | dout_x7 => data_out_x2_net, |
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| 5994 | dout_x8 => from_register2_data_out_net_x0, |
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| 5995 | idlefordifs => idlefordifs_net, |
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| 5996 | plb_abus => plb_abus_net, |
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| 5997 | plb_pavalid => plb_pavalid_net, |
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| 5998 | plb_rnw => plb_rnw_net, |
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| 5999 | plb_wrdbus => plb_wrdbus_net, |
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| 6000 | sg_plb_addrpref => sg_plb_addrpref_net, |
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| 6001 | splb_rst => splb_rst_net, |
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| 6002 | data_in => data_in_net, |
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| 6003 | data_in_x0 => data_in_x0_net, |
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| 6004 | data_in_x1 => data_in_x1_net, |
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| 6005 | data_in_x2 => data_in_x2_net, |
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| 6006 | data_in_x3 => data_in_x3_net, |
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| 6007 | data_in_x4 => data_in_x4_net, |
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| 6008 | data_in_x5 => data_in_x5_net, |
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| 6009 | data_in_x6 => data_in_x6_net, |
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| 6010 | data_in_x7 => data_in_x7_net, |
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| 6011 | data_in_x8 => data_in_x8_net, |
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| 6012 | data_in_x9 => from_register2_data_out_net_x1, |
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| 6013 | en => en_net, |
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| 6014 | en_x0 => en_x0_net, |
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| 6015 | en_x1 => en_x1_net, |
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| 6016 | en_x2 => en_x2_net, |
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| 6017 | en_x3 => en_x3_net, |
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| 6018 | en_x4 => en_x4_net, |
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| 6019 | en_x5 => en_x5_net, |
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| 6020 | en_x6 => en_x6_net, |
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| 6021 | en_x7 => en_x7_net, |
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| 6022 | en_x8 => en_x8_net, |
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| 6023 | en_x9 => en_x9_net, |
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| 6024 | sl_addrack => sl_addrack_net, |
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| 6025 | sl_rdcomp => sl_rdcomp_net, |
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| 6026 | sl_rddack => sl_rddack_net, |
---|
| 6027 | sl_rddbus => sl_rddbus_net, |
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| 6028 | sl_wait => sl_wait_net, |
---|
| 6029 | sl_wrcomp => sl_wrdack_x2, |
---|
| 6030 | sl_wrdack => sl_wrdack_x1, |
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| 6031 | timer0_active => timer0_active_net, |
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| 6032 | timer1_active => timer1_active_net, |
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| 6033 | timer2_active => timer2_active_net, |
---|
| 6034 | timer3_active => timer3_active_net, |
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| 6035 | timerexpire => timerexpire_net |
---|
| 6036 | ); |
---|
| 6037 | |
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| 6038 | end structural; |
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