source: PlatformSupport/Deprecated/pcores/clock_board_config_v1_02_a/data/clock_board_config_v2_1_0.mpd

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##
## Name     : clock_board_config
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN clock_board_config

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE)
OPTION IP_GROUP = USER
OPTION USAGE_LEVEL = BASE_USER

IO_INTERFACE IO_IF = CLKBRDCONFIG, IO_TYPE = WARP_CLKBRD_CONFIG_V1

## Bus Interfaces
# This core is not attached to any busses

## Generics for VHDL or Parameters for Verilog

#platgen will infer these hex values and defparam them in the Verilog like "defparam clkbrdconfig_0.fpga_radio_clk_source = 'h1AFF;"
#since they're 16 bits anyway, the ambiguous bit length in the defparam'd value is no problem
PARAMETER fpga_radio_clk_source = 0x1AFF, DT = std_logic_vector, DESC = Selects radio reference clock source, VALUES = (0x1AFF=Oscillator, 0x1DFF=External Coax), PERMIT = BASE_USER
PARAMETER fpga_logic_clk_source = 0x1AFF, DT = std_logic_vector, DESC = Selects FPGA/sampling clock source, VALUES = (0x1AFF=Oscillator, 0x1DFF=External Coax), PERMIT = BASE_USER

PARAMETER sys_clk_freq_hz = 0x05f5e100, DT = std_logic_vector, DESC = Frequency of clock at sys_clk input, VALUES = (0x05f5e100=100MHz, 0x1F78A40=33MHz), PERMIT = BASE_USER
PARAMETER scp_min_freq_hz = 0x002625a0, DT = std_logic_vector, DESC = Minimum serial I/O frequency, VALUES = (0x002625a0=25MHz), PERMIT = BASE_USER

PARAMETER scp_cyc_leng_a = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
PARAMETER scp_cyc_leng_b = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER
PARAMETER scp_cyc_leng = 0x00000028, DT = std_logic_vector, DESC = Length of serial I/O write cycle, VALUES = (0x00000028=40), PERMIT = BASE_USER

## Ports
PORT sys_clk = "", DIR = I, SIGIS = CLK
PORT sys_rst = "net_gnd", DIR = I, SIGIS = RST
PORT cfg_radio_dat_out = "", DIR = O
PORT cfg_radio_csb_out = "", DIR = O
PORT cfg_radio_en_out = "", DIR = O
PORT cfg_radio_clk_out = "", DIR = O
PORT cfg_logic_dat_out = "", DIR = O
PORT cfg_logic_csb_out = "", DIR = O
PORT cfg_logic_en_out = "", DIR = O
PORT cfg_logic_clk_out = "", DIR = O

PORT config_invalid = "", DIR = O

END