1 | //-------------------------------------------------------------------------- |
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2 | // -- |
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3 | // OneWireMaster -- |
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4 | // A synthesizable 1-wire master peripheral -- |
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5 | // Copyright 1999-2005 Dallas Semiconductor Corporation -- |
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6 | // -- |
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7 | //-------------------------------------------------------------------------- |
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8 | // -- |
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9 | // Purpose: Provides timing and control of Dallas 1-wire bus -- |
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10 | // through a memory-mapped peripheral -- |
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11 | // File: OneWireMaster.v -- |
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12 | // Date: February 1, 2005 -- |
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13 | // Version: v2.100 -- |
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14 | // Authors: Rick Downs and Charles Hill, -- |
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15 | // Dallas Semiconductor Corporation -- |
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16 | // -- |
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17 | // Note: This source code is available for use without license. -- |
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18 | // Dallas Semiconductor is not responsible for the -- |
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19 | // functionality or utility of this product. -- |
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20 | // -- |
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21 | // REV: Updated 1-Wire timings to match App Note 126 - SKH -- |
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22 | // Added in Async MR of DQ_CONTROL - GAG -- |
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23 | // Changed WriteZero TimeSlotCnt to 60 instead of only 30 to -- |
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24 | // match OneWire Spec. - GAG -- |
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25 | // Added in bit control mode, left dqz for other function - GAG-- |
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26 | // Added strong pullup enable signal - GAG -- |
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27 | // Modified pd so it will not fire until the entire PD routine -- |
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28 | // has completed - GAG -- |
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29 | // Added OW_LOW interrupt and OW_SHORT interrupt - GAG -- |
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30 | // Added PPM and LLM for long line situations - GAG -- |
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31 | // Changed logic for rsrf and rbf int flags - GAG -- |
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32 | // Significant changes to improve synthesis - English -- |
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33 | // Ported to Verilog - Sandelin -- |
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34 | //-------------------------------------------------------------------------- |
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35 | |
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36 | module onewiremaster ( |
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37 | BIT_CTL, clk_1us, clr_activate_intr, DQ_IN, EN_FOW, EOWL, |
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38 | EOWSH, epd, erbf, ersf, etbe, etmt, FOW, ias, LLM, MR, OD, |
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39 | owr, pd, PPM, rbf_reset, sr_a, STP_SPLY, STPEN, tbe, xmit_buffer, |
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40 | clear_interrupts, DQ_CONTROL, FSM_CLK, INTR, |
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41 | OneWireIO_eq_Load, OW_LOW, OW_SHORT, pdr, rbf, rcvr_buffer, reset_owr, |
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42 | rsrf, STPZ, temt); |
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43 | |
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44 | input BIT_CTL; // enable only single bit transmitions |
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45 | input clk_1us; // 1us reference clock |
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46 | input clr_activate_intr; |
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47 | input DQ_IN; // OW data input |
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48 | input EN_FOW; // enable force OW functionality |
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49 | input EOWL; // enable One wire bus low interrupt |
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50 | input EOWSH; // enable One Wire bus short interrupt |
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51 | input epd; // enable presence detect interrupt |
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52 | input erbf; // enable receive buffer full interrupt |
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53 | input ersf; // enable receive shift register full int. |
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54 | input etbe; // enable transmit buffer empty interrupt |
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55 | input etmt; // enable transmit shift inputister empty int. |
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56 | input FOW; // Force OW value low |
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57 | input ias; // INTR active state |
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58 | input LLM; // long line mode enable |
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59 | input MR; // master reset |
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60 | input OD; // enable overdrive |
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61 | input owr; // one wire reset ??? |
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62 | input pd; // presence detect interrupt |
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63 | input PPM; // presence pulse masking enable |
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64 | input rbf_reset; // clear for receive buffer full interrupt |
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65 | input sr_a; // search rom accelorator enable |
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66 | input STP_SPLY; // enable strong pull up supply mode |
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67 | input STPEN; // enable strong pull up output |
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68 | input tbe; // transmit buffer empty interrupt |
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69 | input [7:0] xmit_buffer; // transmit buffer |
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70 | |
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71 | |
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72 | output clear_interrupts; |
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73 | output DQ_CONTROL; // OW pulldown control |
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74 | output FSM_CLK; // state machine clk |
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75 | output INTR; // One wire master interrupt output signal |
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76 | output OneWireIO_eq_Load; |
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77 | output OW_LOW; // One wire low interrupt |
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78 | output OW_SHORT; // One wire short interrupt |
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79 | output pdr; // presence detect result |
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80 | output rbf; // receive buffer full int |
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81 | output [7:0] rcvr_buffer; // receive register |
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82 | output reset_owr; // |
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83 | output rsrf; // receive shift reg full interrupt |
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84 | output STPZ; // Strong pullup control (active low) |
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85 | output temt; // transmit shift reg empty interrupt |
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86 | |
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87 | // |
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88 | // Define the states |
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89 | // |
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90 | parameter [2:0] Idle = 3'b000, // Idle |
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91 | CheckOWR = 3'b001, // Check for shorted OW |
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92 | Reset_Low = 3'b010, // Start reset |
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93 | PD_Wait = 3'b011, // release line for 1T |
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94 | PD_Sample = 3'b100, // sample line after slowest 1T over |
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95 | Reset_High = 3'b101, // recover OW line level |
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96 | PD_Force = 3'b110, // mask the presence pulse |
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97 | PD_Release = 3'b111; // recover OW line level |
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98 | |
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99 | parameter [4:0] IdleS= 5'b00000, // Idle state |
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100 | Load= 5'b00001, // Load byte |
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101 | CheckOW= 5'b00010, // Check for shorted line |
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102 | DQLOW= 5'b00011, // Start of timeslot |
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103 | WriteZero= 5'b00100, // Write a zero to the 1-wire |
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104 | WriteOne= 5'b00101, // Write a one to the 1-wire |
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105 | ReadBit= 5'b00110, // Search Rom Accelerator read bit |
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106 | FirstPassSR=5'b00111, // Used by SRA |
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107 | WriteBitSR= 5'b01000, // Decide what bit value to write in SRA |
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108 | WriteBit= 5'b01001, // Writes the chosen bit in SRA |
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109 | WaitTS= 5'b01010, // Wait for end of time slot |
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110 | IndexInc= 5'b01011, // Increments bit index |
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111 | UpdateBuff= 5'b01100, // Updates states of rbf |
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112 | ODWriteZero=5'b01101, // Write a zero @ OD speed to OW |
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113 | ODWriteOne= 5'b01110, // Write a one @ OD speed to OW |
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114 | ClrLowDone= 5'b01111; // disable stpupz before pulldown |
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115 | |
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116 | |
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117 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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118 | // micro-second count for bit transitions and sample |
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119 | parameter [6:0] // Standard speed |
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120 | bit_ts_writeone_high = 7'b0000110, // release-1 @6 us |
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121 | bit_ts_writeone_high_ll = 7'b0001000, // rel-1-LLM @8 us |
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122 | bit_ts_sample = 7'b0001111, // sample @15 us |
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123 | bit_ts_sample_ll = 7'b0011000, // sample/llm @24 us |
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124 | bit_ts_writezero_high = 7'b0111100, // release-0 @60 us |
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125 | bit_ts_end = 7'b1000110, // end @70 us |
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126 | bit_ts_end_ll = 7'b1010000, // end @80 us |
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127 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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128 | // Overdrive speed |
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129 | // note that due to the state machine architecture, the |
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130 | // writeone_high_od and sample_od must be 1 and 2 us. |
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131 | // writezero_high_od and end_od are adjustable, so long |
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132 | // as writezero_high_od does not exceed a particular |
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133 | // 1-Wire device max low time. |
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134 | bit_ts_writeone_high_od = 7'b0000001, // release-1 @1 us |
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135 | bit_ts_sample_od = 7'b0000010, // sample @2 us |
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136 | bit_ts_writezero_high_od = 7'b0001000, // release-0 @8 us |
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137 | bit_ts_end_od = 7'b0001001; // end @10 us |
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138 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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139 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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140 | // micro-second count for reset transitions |
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141 | parameter [10:0] // Standard speed |
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142 | reset_ts_release = 11'b01001011000, // release @600 us |
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143 | reset_ts_no_stpz = 11'b01001100010, // stpz=1 @610 us |
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144 | reset_ts_ppm = 11'b01001101100, // pp-mask @620 us |
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145 | reset_ts_sample = 11'b01010011110, // sample @670 us |
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146 | reset_ts_llsample= 11'b01010101101, // sample @685 us |
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147 | reset_ts_ppm_end = 11'b01010110010, // ppm-end @690 us |
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148 | reset_ts_stpz = 11'b01110110110, // stpz @950 us |
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149 | reset_ts_recover = 11'b01111000000, // recover @960 us |
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150 | reset_ts_end = 11'b10000111000, // end @1080 us |
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151 | // Overdrive speed |
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152 | reset_ts_release_od = 11'b00001000110, // release @70 us |
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153 | reset_ts_no_stpz_od = 11'b00001001011, // stpz=1 @75 us |
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154 | reset_ts_sample_od = 11'b00001001111, // sample @79 us |
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155 | reset_ts_stpz_od = 11'b00001101001, // stpz @105 us |
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156 | reset_ts_recover_od = 11'b00001110011, // recover @115 us |
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157 | reset_ts_end_od = 11'b00010000000; // end @128 us |
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158 | // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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159 | |
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160 | |
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161 | wire owr; // 1W reset command |
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162 | wire sr_a; // search ROM accelerator command |
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163 | |
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164 | // interrupt register |
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165 | wire pd; // presence detect done flag |
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166 | reg pdr; // presence detect result |
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167 | wire tbe; // transmit buffer empty flag |
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168 | reg temt; // transmit shift register empty flag |
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169 | wire temt_ext; // temt extended flag |
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170 | reg rbf; // receive buffer full flag |
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171 | reg rsrf; // receive shift register full flag |
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172 | reg OW_SHORT; // OW line shorted interrupt |
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173 | reg OW_LOW; // OW line low interrupt |
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174 | reg INTR; |
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175 | |
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176 | //wire rsrf_reset; // clear signal for rsrf |
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177 | reg set_rbf; // set signal for rbf |
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178 | |
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179 | // interrupt enable register |
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180 | wire epd; // enable presence detect interrupt |
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181 | wire ias; // INTR active state |
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182 | wire etbe; // enable transmit buffer empty interrupt |
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183 | wire etmt; // enable transmit shift register empty int. |
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184 | wire erbf; // enable receive buffer full interrupt |
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185 | wire ersf; // enable receive shift register full int. |
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186 | wire EOWSH; // enable ow shorted interrupt |
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187 | wire EOWL; // enable ow low interrupt |
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188 | |
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189 | wire clr_activate_intr; |
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190 | reg reset_owr; |
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191 | |
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192 | reg activate_intr; |
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193 | reg dly_clr_activate_intr; |
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194 | reg clear_interrupts; |
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195 | |
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196 | reg SET_RSHRT; // set ow_short prior to ow reset |
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197 | reg SET_IOSHRT; // set ow_short prior to tx a bit |
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198 | |
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199 | wire [7:0] xmit_buffer; // transmit buffer |
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200 | reg [7:0] xmit_shiftreg; // transmit shift register |
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201 | |
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202 | reg [7:0] rcvr_buffer; // receive buffer |
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203 | reg [7:0] rcvr_shiftreg; // receive shift register |
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204 | |
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205 | reg last_rcvr_bit; // active on index = 7 to begin shift to rbe |
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206 | reg byte_done; |
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207 | reg byte_done_flag, bdext1; // signals to stretch byte_done |
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208 | |
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209 | reg First; // for Search ROM accelerator |
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210 | reg BitRead1; |
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211 | reg BitRead2; |
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212 | reg BitWrite; |
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213 | |
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214 | reg [2:0] OneWireReset; |
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215 | reg [4:0] OneWireIO; |
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216 | |
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217 | reg [10:0] count; |
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218 | //reg [4:0] smCnt; |
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219 | reg [3:0] index; |
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220 | reg [6:0] TimeSlotCnt; |
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221 | |
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222 | reg PD_READ; |
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223 | reg LOW_DONE; |
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224 | reg DQ_CONTROL_F; |
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225 | wire DQ_CONTROL; |
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226 | wire STPZ; |
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227 | reg DQ_IN_HIGH; |
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228 | reg OD_DQH; |
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229 | reg rbf_set; |
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230 | reg rsrf_reset; |
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231 | |
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232 | reg ROW; |
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233 | |
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234 | wire FSM_CLK = clk_1us; |
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235 | |
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236 | // |
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237 | // 1 wire control |
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238 | // |
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239 | assign DQ_CONTROL = MR ? 1'b1 : DQ_CONTROL_F; //GAG added in asynch RESET |
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240 | |
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241 | always @(posedge FSM_CLK) //GAG added in ODWriteZero |
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242 | DQ_CONTROL_F <= |
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243 | (EN_FOW == 1) && (FOW == 1)?0: |
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244 | OneWireReset == Reset_Low?0: |
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245 | OneWireReset == PD_Wait?1: |
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246 | OneWireReset == PD_Force?0: |
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247 | OneWireIO == DQLOW?0: |
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248 | OneWireIO == WriteZero?0: |
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249 | OneWireIO == ODWriteZero?0: |
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250 | OneWireIO == WriteBit?0: |
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251 | 1; |
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252 | |
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253 | wire OneWireIO_eq_Load = OneWireIO == Load; |
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254 | |
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255 | // |
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256 | // Strong Pullup control section - GAG |
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257 | // not pulling line low, not checking for pres detect, and |
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258 | // OW has recovered from read |
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259 | // SPLY is only for enabling STP when a slave requires high current |
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260 | // and STP_SPLY is enabled |
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261 | // |
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262 | wire SPLY = (STP_SPLY && (OneWireReset == Idle) && (OneWireIO == IdleS)); |
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263 | assign STPZ = !(STPEN && DQ_CONTROL && DQ_IN_HIGH |
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264 | && (PD_READ || LOW_DONE || SPLY)); |
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265 | |
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266 | always @(posedge MR or posedge FSM_CLK) |
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267 | if (MR) |
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268 | begin |
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269 | DQ_IN_HIGH <= 0; |
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270 | OD_DQH <=0; |
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271 | end |
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272 | else if (OD) |
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273 | if(DQ_IN && !DQ_IN_HIGH && !OD_DQH) |
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274 | begin |
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275 | DQ_IN_HIGH <= 1; |
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276 | OD_DQH <=1; |
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277 | end |
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278 | else if(OD_DQH && DQ_IN) |
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279 | DQ_IN_HIGH <= 0; |
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280 | else |
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281 | begin |
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282 | OD_DQH <=0; |
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283 | DQ_IN_HIGH <= 0; |
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284 | end |
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285 | else |
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286 | begin |
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287 | if(DQ_IN && !DQ_IN_HIGH) |
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288 | DQ_IN_HIGH <= 1; |
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289 | else if (DQ_IN && DQ_IN_HIGH) |
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290 | DQ_IN_HIGH <= DQ_IN_HIGH; |
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291 | else |
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292 | DQ_IN_HIGH <= 0; |
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293 | end |
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294 | |
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295 | // |
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296 | // Update receive buffer and the rsrf and rbf int flags |
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297 | // |
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298 | always @(posedge MR or posedge rbf_reset or posedge rbf_set) |
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299 | if (MR) |
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300 | rbf <= 0; |
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301 | else if (rbf_reset) //note that rbf resets at the beginning of the RX buff read |
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302 | rbf <= 0; |
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303 | else |
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304 | rbf <= 1; |
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305 | |
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306 | always @(posedge MR or posedge FSM_CLK) |
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307 | if (MR) |
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308 | rsrf <= 1'b0; |
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309 | else if (last_rcvr_bit || BIT_CTL) |
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310 | begin |
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311 | if (OneWireIO == IndexInc) |
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312 | rsrf <= 1'b1; |
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313 | else if (rsrf_reset) |
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314 | rsrf <= 1'b0; |
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315 | end |
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316 | else if (rsrf_reset || (OneWireIO == DQLOW)) |
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317 | rsrf <= 1'b0; |
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318 | |
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319 | always @(posedge FSM_CLK or posedge MR) |
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320 | if (MR) |
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321 | begin |
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322 | rcvr_buffer <= 0; |
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323 | rbf_set <= 0; |
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324 | end |
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325 | else |
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326 | if (rsrf && !rbf) |
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327 | begin |
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328 | rcvr_buffer <= rcvr_shiftreg; |
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329 | rbf_set <= 1'b1; |
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330 | rsrf_reset <= 1'b1; |
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331 | end |
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332 | else |
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333 | begin |
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334 | rbf_set <= 1'b0; |
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335 | if (!rsrf) |
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336 | rsrf_reset <= 1'b0; |
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337 | end |
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338 | |
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339 | // |
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340 | // Update OW shorted interrupt |
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341 | // |
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342 | always @(posedge MR or posedge FSM_CLK) |
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343 | begin |
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344 | if(MR) |
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345 | OW_SHORT <= 1'b0; |
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346 | else if (SET_RSHRT || SET_IOSHRT) |
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347 | OW_SHORT <= 1'b1; |
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348 | else if (clr_activate_intr) |
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349 | OW_SHORT <= 1'b0; |
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350 | else |
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351 | OW_SHORT <= OW_SHORT; |
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352 | end |
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353 | |
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354 | // |
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355 | // Update OW bus low interrupt |
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356 | // |
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357 | always @(posedge MR or posedge FSM_CLK) |
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358 | begin |
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359 | if (MR) |
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360 | OW_LOW <= 0; |
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361 | else if (!DQ_IN && (OneWireReset == Idle) && (OneWireIO == IdleS)) |
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362 | OW_LOW <= 1; |
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363 | else if (clr_activate_intr) |
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364 | OW_LOW <= 0; |
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365 | else |
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366 | OW_LOW <= OW_LOW; |
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367 | end |
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368 | |
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369 | /////////////////////////////////////////////////////////////// |
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370 | // The following section handles the interrupt itself |
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371 | /////////////////////////////////////////////////////////////// |
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372 | |
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373 | // |
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374 | // Create clear interrupts |
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375 | // |
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376 | always @(posedge MR or posedge FSM_CLK) |
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377 | if (MR) |
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378 | begin |
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379 | //dly_clr_activate_intr <= 1'b0; |
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380 | clear_interrupts <= 1'b0; |
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381 | end // if (MR) |
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382 | else |
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383 | begin |
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384 | //dly_clr_activate_intr<=clr_activate_intr; |
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385 | clear_interrupts<=clr_activate_intr; |
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386 | //clear_interrupts <= dly_clr_activate_intr ; |
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387 | end |
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388 | |
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389 | wire acint_reset = MR || clr_activate_intr; |
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390 | |
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391 | // |
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392 | // Check for active interrupt |
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393 | // |
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394 | always @(posedge acint_reset or posedge FSM_CLK) |
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395 | if(acint_reset) |
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396 | activate_intr <= 1'b0; |
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397 | else |
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398 | case(1) |
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399 | pd && epd: |
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400 | activate_intr <= 1'b1; |
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401 | tbe && etbe && !temt: |
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402 | activate_intr <= 1'b1; |
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403 | temt_ext && etmt: |
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404 | activate_intr <= 1'b1; |
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405 | rbf && erbf: |
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406 | activate_intr <= 1'b1; |
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407 | rsrf && ersf: |
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408 | activate_intr <= 1'b1; |
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409 | OW_LOW && EOWL: |
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410 | activate_intr <= 1'b1; |
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411 | OW_SHORT && EOWSH: |
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412 | activate_intr <= 1'b1; |
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413 | endcase // case(1) |
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414 | |
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415 | // |
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416 | // Create INTR signal by checking for active interrupt and active |
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417 | // state of INTR |
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418 | // |
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419 | always @(activate_intr or ias) |
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420 | case({activate_intr,ias}) |
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421 | 2'b11: |
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422 | INTR <= 1'b1; |
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423 | 2'b01: |
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424 | INTR <= 1'b0; |
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425 | 2'b10: |
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426 | INTR <= 1'b1; // shughes - 8-16-04 - was 1'b0 |
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427 | default: |
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428 | INTR <= 1'b0; // shughes - 8-16-04 - was 1'b1 |
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429 | endcase // case({activate_intr,ias}) |
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430 | |
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431 | |
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432 | |
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433 | //-------------------------------------------------------------------------- |
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434 | // |
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435 | // OneWireReset |
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436 | // |
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437 | // this state machine performs the 1-wire reset and presence detect |
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438 | // - Added OD for overdrive speed presence detect |
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439 | // - Added PD_LOW bit for strong pullup control |
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440 | // |
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441 | // Idle : OW high - waiting to issue a PD |
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442 | // CheckOWR : OW high - checks for shorted OW line |
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443 | // Reset_Low : OW low - held down for GT8 OW osc periods |
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444 | // PD_Wait : OW high - released and waits for 1T |
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445 | // PD_Sample : OW high - checks to see if a slave is out there pulling |
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446 | // OW low for 4T |
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447 | // Reset_High : OW high - slave, if any, release OW and host lets it recover |
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448 | //-------------------------------------------------------------------------- |
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449 | |
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450 | always @(posedge FSM_CLK or posedge MR) |
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451 | if(MR) begin |
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452 | pdr <= 1'b1; // Added default state to conform to spec - SDS |
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453 | OneWireReset <= Idle; |
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454 | //smCnt <= 0; // added to init simulations |
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455 | count <= 0; |
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456 | PD_READ <= 0; // Added PD_READ - GAG |
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457 | reset_owr <= 0; |
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458 | SET_RSHRT <= 0; // |
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459 | ROW <= 0; |
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460 | end |
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461 | else if(!owr) begin |
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462 | count <= 0; |
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463 | ROW <= 0; |
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464 | reset_owr <= 0; |
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465 | OneWireReset <= Idle; |
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466 | end |
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467 | else |
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468 | case(OneWireReset) |
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469 | Idle: begin |
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470 | if (ROW) |
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471 | reset_owr <= 1; |
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472 | else |
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473 | begin |
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474 | count <= 0; |
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475 | SET_RSHRT <=0; |
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476 | reset_owr <= 0; |
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477 | OneWireReset <= CheckOWR; |
---|
478 | end |
---|
479 | end |
---|
480 | |
---|
481 | CheckOWR: begin |
---|
482 | OneWireReset <= Reset_Low; |
---|
483 | if(!DQ_IN) |
---|
484 | SET_RSHRT <= 1; |
---|
485 | end |
---|
486 | |
---|
487 | Reset_Low: begin |
---|
488 | count <= count + 1; |
---|
489 | PD_READ <= 0; // Added PD_READ - GAG |
---|
490 | if(OD) // Added OD - GAG |
---|
491 | begin |
---|
492 | // tRSTL - OD |
---|
493 | if(count == reset_ts_release_od) |
---|
494 | begin |
---|
495 | OneWireReset <= PD_Wait; |
---|
496 | PD_READ <= 1; |
---|
497 | end |
---|
498 | end |
---|
499 | // tRSTL - STD |
---|
500 | else if(count == reset_ts_release) |
---|
501 | begin |
---|
502 | OneWireReset <= PD_Wait; |
---|
503 | PD_READ <= 1; |
---|
504 | end |
---|
505 | end |
---|
506 | |
---|
507 | PD_Wait: begin |
---|
508 | SET_RSHRT <= 0; |
---|
509 | count <= count + 1; |
---|
510 | if(!DQ_IN & DQ_CONTROL_F) begin |
---|
511 | OneWireReset <= PD_Sample; |
---|
512 | //smCnt <= 0; |
---|
513 | end |
---|
514 | else if(OD) |
---|
515 | begin |
---|
516 | // (tRSTL + pull-up time) - OD |
---|
517 | if(count==reset_ts_no_stpz_od) |
---|
518 | // disables stp_sply |
---|
519 | PD_READ <= 0; // Be sure to turn off 4 MPD mode |
---|
520 | // tMSP - OD |
---|
521 | else if(count == reset_ts_sample_od) |
---|
522 | begin |
---|
523 | OneWireReset <= PD_Sample; |
---|
524 | //smCnt <= 0; |
---|
525 | end |
---|
526 | end |
---|
527 | // (tRSTL + pull-up time) - STD |
---|
528 | else if(count == reset_ts_no_stpz) |
---|
529 | // disables stp_sply |
---|
530 | PD_READ <= 0; // Be sure to turn off 4 MPD mode |
---|
531 | // tPPM1 - STD |
---|
532 | else if((count == reset_ts_ppm) && PPM) |
---|
533 | OneWireReset <= PD_Force; |
---|
534 | // tMSP - STD |
---|
535 | else if(count == reset_ts_llsample && !LLM) |
---|
536 | begin |
---|
537 | OneWireReset <= PD_Sample; |
---|
538 | //smCnt <= 0; |
---|
539 | end |
---|
540 | else if(count == reset_ts_sample && LLM) |
---|
541 | begin |
---|
542 | OneWireReset <= PD_Sample; |
---|
543 | //smCnt <= 0; |
---|
544 | end |
---|
545 | end |
---|
546 | |
---|
547 | PD_Sample: begin |
---|
548 | PD_READ <= 0; |
---|
549 | count <= count + 1; |
---|
550 | //smCnt <= smCnt + 1; |
---|
551 | //if (OD) // Added OD - GAG |
---|
552 | // begin |
---|
553 | // if(smCnt == 3-1) |
---|
554 | // begin |
---|
555 | pdr <= DQ_IN; |
---|
556 | OneWireReset <= Reset_High; |
---|
557 | // end |
---|
558 | // end |
---|
559 | //else |
---|
560 | // if(smCnt == 30-1) |
---|
561 | // begin |
---|
562 | // pdr <= DQ_IN; |
---|
563 | // OneWireReset <= Reset_High; |
---|
564 | // end |
---|
565 | end |
---|
566 | |
---|
567 | Reset_High: begin |
---|
568 | count <= count + 1; |
---|
569 | if (OD) // Added OD - GAG |
---|
570 | begin |
---|
571 | if (count == reset_ts_stpz_od) |
---|
572 | begin |
---|
573 | if (DQ_IN) |
---|
574 | PD_READ <= 1; |
---|
575 | end |
---|
576 | else if (count == reset_ts_recover_od) |
---|
577 | begin |
---|
578 | PD_READ <= 0; |
---|
579 | end |
---|
580 | else if (count == reset_ts_end_od) |
---|
581 | begin |
---|
582 | PD_READ <= 0; |
---|
583 | OneWireReset <= Idle; |
---|
584 | ROW <= 1; |
---|
585 | end |
---|
586 | end |
---|
587 | else |
---|
588 | begin |
---|
589 | if(count == reset_ts_stpz) |
---|
590 | begin |
---|
591 | if (DQ_IN) |
---|
592 | PD_READ <= 1; |
---|
593 | end |
---|
594 | else if (count == reset_ts_recover) |
---|
595 | begin |
---|
596 | PD_READ <= 0; |
---|
597 | end |
---|
598 | else if (count == reset_ts_end) |
---|
599 | begin |
---|
600 | PD_READ <= 0; |
---|
601 | OneWireReset <= Idle; |
---|
602 | ROW <= 1; |
---|
603 | end |
---|
604 | end |
---|
605 | end |
---|
606 | |
---|
607 | PD_Force: begin |
---|
608 | count <= count + 1; |
---|
609 | // tPPM2 |
---|
610 | if (count == reset_ts_ppm_end) |
---|
611 | begin |
---|
612 | OneWireReset <= PD_Release; |
---|
613 | end |
---|
614 | end |
---|
615 | |
---|
616 | PD_Release: begin |
---|
617 | count <= count + 1; |
---|
618 | pdr <= 0; //force valid result |
---|
619 | if(count == reset_ts_stpz) |
---|
620 | begin |
---|
621 | if (DQ_IN) |
---|
622 | PD_READ <= 1; |
---|
623 | end |
---|
624 | else if (count == reset_ts_recover) |
---|
625 | begin |
---|
626 | PD_READ <= 0; |
---|
627 | end |
---|
628 | else if (count == reset_ts_end) |
---|
629 | begin |
---|
630 | PD_READ <= 0; |
---|
631 | OneWireReset <= Idle; |
---|
632 | ROW <= 1; |
---|
633 | end |
---|
634 | end |
---|
635 | |
---|
636 | endcase |
---|
637 | |
---|
638 | |
---|
639 | //-------------------------------------------------------------------------- |
---|
640 | // |
---|
641 | // OneWireIO |
---|
642 | // |
---|
643 | // this state machine performs the 1-wire writing and reading |
---|
644 | // - Added ODWriteZero and ODWriteOne for overdrive timing |
---|
645 | // |
---|
646 | // IdleS : Waiting for transmit byte to be loaded |
---|
647 | // ClrLowDone : Disables strong pullup before pulldown turns on |
---|
648 | // Load : Loads byte to shift reg |
---|
649 | // CheckOW : Checks for OW short |
---|
650 | // DQLOW : Starts time slot with OW = 0 |
---|
651 | // ODWriteZero : Completes write of 0 bit / read bit in OD speed |
---|
652 | // ODWriteOne : Completes write of 1 bit / read bit in OD speed |
---|
653 | // WriteZero : Completes write of 0 bit / read bit in standard speed |
---|
654 | // WriteOne : Completes write of 1 bit / read bit in standard speed |
---|
655 | // ReadBit : AutoSearchRom : Reads the first bit value |
---|
656 | // FirstPassSR : AutoSearchRom : Decides to do another read or the write |
---|
657 | // WriteBitSR : AutoSearchRom : Determines the bit to write |
---|
658 | // WriteBit : AutoSearchRom : Writes the bit |
---|
659 | // WatiTS : Allows OW to recover for the remainder of the time slot |
---|
660 | // IndexInc : Increment the index to send out next bit (in byte) |
---|
661 | // UpdateBuff : Allows other signals to update following finished byte/bit |
---|
662 | //-------------------------------------------------------------------------- |
---|
663 | |
---|
664 | // The following 2 registers are to stretch the temt signal to catch the |
---|
665 | // temt interrupt source - SDS |
---|
666 | |
---|
667 | always @(posedge MR or posedge FSM_CLK) |
---|
668 | if(MR) |
---|
669 | bdext1 <= 1'b0; |
---|
670 | else |
---|
671 | bdext1 <= byte_done; |
---|
672 | |
---|
673 | always @(posedge MR or posedge FSM_CLK) |
---|
674 | if(MR) |
---|
675 | byte_done_flag <= 1'b0; |
---|
676 | else |
---|
677 | byte_done_flag <= bdext1; |
---|
678 | |
---|
679 | assign temt_ext = temt && byte_done_flag; |
---|
680 | |
---|
681 | // The index variable has been decoded explicitly in this state machine |
---|
682 | // so that the code would compile on the Cypress warp compiler - SDS |
---|
683 | always @(posedge FSM_CLK or posedge MR) |
---|
684 | if(MR) begin |
---|
685 | index <= 0; |
---|
686 | TimeSlotCnt <= 0; |
---|
687 | temt <= 1'b1; |
---|
688 | last_rcvr_bit <= 1'b0; |
---|
689 | rcvr_shiftreg <= 0; |
---|
690 | OneWireIO <= IdleS; |
---|
691 | BitRead1<=0; |
---|
692 | BitRead2<=0; |
---|
693 | BitWrite<=0; |
---|
694 | First <= 1'b0; |
---|
695 | byte_done <= 1'b0; |
---|
696 | xmit_shiftreg<=0; |
---|
697 | LOW_DONE <= 0; |
---|
698 | SET_IOSHRT <= 0; |
---|
699 | end |
---|
700 | else |
---|
701 | case(OneWireIO) |
---|
702 | |
---|
703 | // IdleS state clears variables and waits for something to be |
---|
704 | // deposited in the transmit buffer. When something is there, |
---|
705 | // the next state is Load. |
---|
706 | IdleS: |
---|
707 | begin |
---|
708 | byte_done <= 1'b0; |
---|
709 | index <= 0; |
---|
710 | last_rcvr_bit <= 1'b0; |
---|
711 | First <= 1'b0; |
---|
712 | TimeSlotCnt <= 0; |
---|
713 | LOW_DONE <= 0; |
---|
714 | SET_IOSHRT <= 0; |
---|
715 | temt <= 1'b1; |
---|
716 | if(!tbe) |
---|
717 | begin |
---|
718 | if(STPEN) |
---|
719 | OneWireIO <= ClrLowDone; |
---|
720 | else |
---|
721 | OneWireIO <= Load; |
---|
722 | end |
---|
723 | else |
---|
724 | OneWireIO <= IdleS; |
---|
725 | end |
---|
726 | |
---|
727 | // New state added to be sure the strong pullup will be disabled |
---|
728 | // before the OW pulldown turns on |
---|
729 | ClrLowDone: |
---|
730 | begin |
---|
731 | LOW_DONE <= 0; |
---|
732 | if (!LOW_DONE) |
---|
733 | OneWireIO <= Load; |
---|
734 | end |
---|
735 | |
---|
736 | // Load transfers the transmit buffer to the transmit shift register, |
---|
737 | // then clears the transmit shift register empty interrupt. The next |
---|
738 | // state is then DQLOW. |
---|
739 | Load: |
---|
740 | begin |
---|
741 | xmit_shiftreg <= xmit_buffer; |
---|
742 | rcvr_shiftreg <= 0; |
---|
743 | temt <= 1'b0; |
---|
744 | LOW_DONE <= 0; |
---|
745 | OneWireIO <= CheckOW; |
---|
746 | end |
---|
747 | |
---|
748 | // Checks OW value before sending out every bit to see if line |
---|
749 | // was forced low by some other means at an incorrect time |
---|
750 | CheckOW: |
---|
751 | begin |
---|
752 | OneWireIO <= DQLOW; |
---|
753 | //TimeSlotCnt <= TimeSlotCnt + 1; |
---|
754 | if (!DQ_IN) |
---|
755 | SET_IOSHRT <= 1; |
---|
756 | end |
---|
757 | |
---|
758 | // DQLOW pulls the DQ line low for 1us, beginning a timeslot. |
---|
759 | // If sr_a is 0, it is a normal write/read operation. If sr_a |
---|
760 | // is a 1, then you must go into Search ROM accelerator mode. |
---|
761 | // If OD is 1, the part is in overdrive and must perform |
---|
762 | // ODWrites instead of normal Writes while OD is 0. |
---|
763 | DQLOW: |
---|
764 | begin |
---|
765 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
766 | LOW_DONE <= 0; |
---|
767 | if (OD) |
---|
768 | begin |
---|
769 | //if(TimeSlotCnt==bit_ts_writeone_high_od) |
---|
770 | //begin |
---|
771 | if(!sr_a) |
---|
772 | begin |
---|
773 | case(index) |
---|
774 | 0: |
---|
775 | if(!xmit_shiftreg[0]) |
---|
776 | OneWireIO <= ODWriteZero; |
---|
777 | else |
---|
778 | OneWireIO <= ODWriteOne; |
---|
779 | 1: |
---|
780 | if(!xmit_shiftreg[1]) |
---|
781 | OneWireIO <= ODWriteZero; |
---|
782 | else |
---|
783 | OneWireIO <= ODWriteOne; |
---|
784 | 2: |
---|
785 | if(!xmit_shiftreg[2]) |
---|
786 | OneWireIO <= ODWriteZero; |
---|
787 | else |
---|
788 | OneWireIO <= ODWriteOne; |
---|
789 | 3: |
---|
790 | if(!xmit_shiftreg[3]) |
---|
791 | OneWireIO <= ODWriteZero; |
---|
792 | else |
---|
793 | OneWireIO <= ODWriteOne; |
---|
794 | 4: |
---|
795 | if(!xmit_shiftreg[4]) |
---|
796 | OneWireIO <= ODWriteZero; |
---|
797 | else |
---|
798 | OneWireIO <= ODWriteOne; |
---|
799 | 5: |
---|
800 | if(!xmit_shiftreg[5]) |
---|
801 | OneWireIO <= ODWriteZero; |
---|
802 | else |
---|
803 | OneWireIO <= ODWriteOne; |
---|
804 | 6: |
---|
805 | if(!xmit_shiftreg[6]) |
---|
806 | OneWireIO <= ODWriteZero; |
---|
807 | else |
---|
808 | OneWireIO <= ODWriteOne; |
---|
809 | 7: |
---|
810 | if(!xmit_shiftreg[7]) |
---|
811 | OneWireIO <= ODWriteZero; |
---|
812 | else |
---|
813 | OneWireIO <= ODWriteOne; |
---|
814 | endcase // case(index) |
---|
815 | end |
---|
816 | else // Search Rom Accelerator mode |
---|
817 | OneWireIO <= ReadBit; |
---|
818 | end |
---|
819 | //end |
---|
820 | else if(((TimeSlotCnt==bit_ts_writeone_high) && !LLM) || |
---|
821 | ((TimeSlotCnt==bit_ts_writeone_high_ll) && LLM)) |
---|
822 | begin |
---|
823 | if(!sr_a) // Normal write |
---|
824 | begin |
---|
825 | case(index) |
---|
826 | 0: |
---|
827 | if(!xmit_shiftreg[0]) |
---|
828 | OneWireIO <= WriteZero; |
---|
829 | else |
---|
830 | OneWireIO <= WriteOne; |
---|
831 | 1: |
---|
832 | if(!xmit_shiftreg[1]) |
---|
833 | OneWireIO <= WriteZero; |
---|
834 | else |
---|
835 | OneWireIO <= WriteOne; |
---|
836 | 2: |
---|
837 | if(!xmit_shiftreg[2]) |
---|
838 | OneWireIO <= WriteZero; |
---|
839 | else |
---|
840 | OneWireIO <= WriteOne; |
---|
841 | 3: |
---|
842 | if(!xmit_shiftreg[3]) |
---|
843 | OneWireIO <= WriteZero; |
---|
844 | else |
---|
845 | OneWireIO <= WriteOne; |
---|
846 | 4: |
---|
847 | if(!xmit_shiftreg[4]) |
---|
848 | OneWireIO <= WriteZero; |
---|
849 | else |
---|
850 | OneWireIO <= WriteOne; |
---|
851 | 5: |
---|
852 | if(!xmit_shiftreg[5]) |
---|
853 | OneWireIO <= WriteZero; |
---|
854 | else |
---|
855 | OneWireIO <= WriteOne; |
---|
856 | 6: |
---|
857 | if(!xmit_shiftreg[6]) |
---|
858 | OneWireIO <= WriteZero; |
---|
859 | else |
---|
860 | OneWireIO <= WriteOne; |
---|
861 | 7: |
---|
862 | if(!xmit_shiftreg[7]) |
---|
863 | OneWireIO <= WriteZero; |
---|
864 | else |
---|
865 | OneWireIO <= WriteOne; |
---|
866 | endcase // case(index) |
---|
867 | end |
---|
868 | else // Search Rom Accelerator mode |
---|
869 | OneWireIO <= ReadBit; |
---|
870 | end |
---|
871 | end |
---|
872 | |
---|
873 | // WriteZero and WriteOne are identical, except for what they do to |
---|
874 | // DQ (assigned in concurrent assignments). They both read DQ after |
---|
875 | // 15us, then move on to wait for the end of the timeslot, unless |
---|
876 | // running in Long Line mode which extends the sample time out to 22 |
---|
877 | WriteZero: |
---|
878 | begin |
---|
879 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
880 | if(((TimeSlotCnt==bit_ts_sample) && !sr_a && !LLM) || |
---|
881 | ((TimeSlotCnt==bit_ts_sample_ll) && !sr_a && LLM)) |
---|
882 | case(index) |
---|
883 | 0: |
---|
884 | rcvr_shiftreg[0] <= DQ_IN; |
---|
885 | 1: |
---|
886 | rcvr_shiftreg[1] <= DQ_IN; |
---|
887 | 2: |
---|
888 | rcvr_shiftreg[2] <= DQ_IN; |
---|
889 | 3: |
---|
890 | rcvr_shiftreg[3] <= DQ_IN; |
---|
891 | 4: |
---|
892 | rcvr_shiftreg[4] <= DQ_IN; |
---|
893 | 5: |
---|
894 | rcvr_shiftreg[5] <= DQ_IN; |
---|
895 | 6: |
---|
896 | rcvr_shiftreg[6] <= DQ_IN; |
---|
897 | 7: |
---|
898 | rcvr_shiftreg[7] <= DQ_IN; |
---|
899 | endcase |
---|
900 | if(TimeSlotCnt == bit_ts_writezero_high) //62 7_25_01 |
---|
901 | OneWireIO <= WaitTS; |
---|
902 | if(DQ_IN) |
---|
903 | LOW_DONE <= 1; |
---|
904 | end |
---|
905 | |
---|
906 | WriteOne: |
---|
907 | begin |
---|
908 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
909 | if(((TimeSlotCnt==bit_ts_sample) && !sr_a && !LLM) || |
---|
910 | ((TimeSlotCnt==bit_ts_sample_ll) && !sr_a && LLM)) |
---|
911 | case(index) |
---|
912 | 0: |
---|
913 | rcvr_shiftreg[0] <= DQ_IN; |
---|
914 | 1: |
---|
915 | rcvr_shiftreg[1] <= DQ_IN; |
---|
916 | 2: |
---|
917 | rcvr_shiftreg[2] <= DQ_IN; |
---|
918 | 3: |
---|
919 | rcvr_shiftreg[3] <= DQ_IN; |
---|
920 | 4: |
---|
921 | rcvr_shiftreg[4] <= DQ_IN; |
---|
922 | 5: |
---|
923 | rcvr_shiftreg[5] <= DQ_IN; |
---|
924 | 6: |
---|
925 | rcvr_shiftreg[6] <= DQ_IN; |
---|
926 | 7: |
---|
927 | rcvr_shiftreg[7] <= DQ_IN; |
---|
928 | endcase |
---|
929 | if(TimeSlotCnt == bit_ts_writezero_high) //62 7_25_01 |
---|
930 | OneWireIO <= WaitTS; |
---|
931 | if(DQ_IN) |
---|
932 | LOW_DONE <= 1; |
---|
933 | end |
---|
934 | |
---|
935 | // ADDED ODWRITE states here GAG |
---|
936 | // ODWriteZero and ODWriteOne are identical, except for what they |
---|
937 | // do to DQ (assigned in concurrent assignments). They both read |
---|
938 | // DQ after 3us, then move on to wait for the end of the timeslot. |
---|
939 | ODWriteZero: |
---|
940 | begin |
---|
941 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
942 | if((TimeSlotCnt == bit_ts_sample_od) && !sr_a) |
---|
943 | case(index) |
---|
944 | 0: |
---|
945 | rcvr_shiftreg[0] <= DQ_IN; |
---|
946 | 1: |
---|
947 | rcvr_shiftreg[1] <= DQ_IN; |
---|
948 | 2: |
---|
949 | rcvr_shiftreg[2] <= DQ_IN; |
---|
950 | 3: |
---|
951 | rcvr_shiftreg[3] <= DQ_IN; |
---|
952 | 4: |
---|
953 | rcvr_shiftreg[4] <= DQ_IN; |
---|
954 | 5: |
---|
955 | rcvr_shiftreg[5] <= DQ_IN; |
---|
956 | 6: |
---|
957 | rcvr_shiftreg[6] <= DQ_IN; |
---|
958 | 7: |
---|
959 | rcvr_shiftreg[7] <= DQ_IN; |
---|
960 | endcase |
---|
961 | if(TimeSlotCnt == bit_ts_writezero_high_od) |
---|
962 | OneWireIO <= WaitTS; |
---|
963 | if(DQ_IN) |
---|
964 | LOW_DONE <= 1; |
---|
965 | end |
---|
966 | |
---|
967 | ODWriteOne: |
---|
968 | begin |
---|
969 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
970 | if((TimeSlotCnt == bit_ts_sample_od) && !sr_a) |
---|
971 | case(index) |
---|
972 | 0: |
---|
973 | rcvr_shiftreg[0] <= DQ_IN; |
---|
974 | 1: |
---|
975 | rcvr_shiftreg[1] <= DQ_IN; |
---|
976 | 2: |
---|
977 | rcvr_shiftreg[2] <= DQ_IN; |
---|
978 | 3: |
---|
979 | rcvr_shiftreg[3] <= DQ_IN; |
---|
980 | 4: |
---|
981 | rcvr_shiftreg[4] <= DQ_IN; |
---|
982 | 5: |
---|
983 | rcvr_shiftreg[5] <= DQ_IN; |
---|
984 | 6: |
---|
985 | rcvr_shiftreg[6] <= DQ_IN; |
---|
986 | 7: |
---|
987 | rcvr_shiftreg[7] <= DQ_IN; |
---|
988 | endcase |
---|
989 | if(TimeSlotCnt == bit_ts_writezero_high_od) |
---|
990 | OneWireIO <= WaitTS; |
---|
991 | if(DQ_IN) |
---|
992 | LOW_DONE <= 1; |
---|
993 | end |
---|
994 | |
---|
995 | // ReadBit used by the SRA to do the required bit reads |
---|
996 | ReadBit: |
---|
997 | begin |
---|
998 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
999 | if(DQ_IN) |
---|
1000 | LOW_DONE <= 1; |
---|
1001 | if(OD) |
---|
1002 | begin |
---|
1003 | if(TimeSlotCnt == bit_ts_sample_od) |
---|
1004 | if(!First) |
---|
1005 | BitRead1 <= DQ_IN; |
---|
1006 | else |
---|
1007 | BitRead2 <= DQ_IN; |
---|
1008 | if(TimeSlotCnt == bit_ts_writezero_high_od) //7 7_25_01 |
---|
1009 | OneWireIO <= FirstPassSR; |
---|
1010 | end |
---|
1011 | else |
---|
1012 | begin |
---|
1013 | if(((TimeSlotCnt == bit_ts_sample)&&!LLM) || ((TimeSlotCnt == bit_ts_sample_ll)&&LLM)) |
---|
1014 | if(!First) |
---|
1015 | BitRead1 <= DQ_IN; |
---|
1016 | else |
---|
1017 | BitRead2 <= DQ_IN; |
---|
1018 | if(TimeSlotCnt == bit_ts_writezero_high) |
---|
1019 | OneWireIO <= FirstPassSR; |
---|
1020 | end |
---|
1021 | end |
---|
1022 | |
---|
1023 | // FirstPassSR decides whether to do another read or to do the |
---|
1024 | // bit write. |
---|
1025 | FirstPassSR: |
---|
1026 | begin |
---|
1027 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
1028 | LOW_DONE <= 0; |
---|
1029 | if(OD) |
---|
1030 | begin |
---|
1031 | if(TimeSlotCnt == bit_ts_end_od) |
---|
1032 | begin |
---|
1033 | TimeSlotCnt <= 0; |
---|
1034 | if(!First) |
---|
1035 | begin |
---|
1036 | First <= 1'b1; |
---|
1037 | OneWireIO <= DQLOW; |
---|
1038 | end |
---|
1039 | else |
---|
1040 | begin |
---|
1041 | OneWireIO <= WriteBitSR; |
---|
1042 | end |
---|
1043 | end |
---|
1044 | end |
---|
1045 | else |
---|
1046 | begin |
---|
1047 | if(((TimeSlotCnt==bit_ts_end) && !LLM) || ((TimeSlotCnt==bit_ts_end_ll) && LLM)) |
---|
1048 | begin |
---|
1049 | TimeSlotCnt <= 0; |
---|
1050 | if(!First) |
---|
1051 | begin |
---|
1052 | First <= 1'b1; |
---|
1053 | OneWireIO <= DQLOW; |
---|
1054 | end |
---|
1055 | else |
---|
1056 | begin |
---|
1057 | OneWireIO <= WriteBitSR; |
---|
1058 | end // else: !if(!First) |
---|
1059 | end |
---|
1060 | end |
---|
1061 | end |
---|
1062 | |
---|
1063 | // WriteBitSR will now determine the bit necessary to write |
---|
1064 | // for the Search ROM to proceed. |
---|
1065 | WriteBitSR: |
---|
1066 | begin |
---|
1067 | case({BitRead1,BitRead2}) |
---|
1068 | 2'b00: begin |
---|
1069 | case(index) |
---|
1070 | 0: begin |
---|
1071 | BitWrite <= xmit_shiftreg[1]; |
---|
1072 | rcvr_shiftreg[0] <= 1'b1; |
---|
1073 | end |
---|
1074 | 1: begin |
---|
1075 | BitWrite <= xmit_shiftreg[2]; |
---|
1076 | rcvr_shiftreg[1] <= 1'b1; |
---|
1077 | end |
---|
1078 | 2: begin |
---|
1079 | BitWrite <= xmit_shiftreg[3]; |
---|
1080 | rcvr_shiftreg[2] <= 1'b1; |
---|
1081 | end |
---|
1082 | 3: begin |
---|
1083 | BitWrite <= xmit_shiftreg[4]; |
---|
1084 | rcvr_shiftreg[3] <= 1'b1; |
---|
1085 | end |
---|
1086 | 4: begin |
---|
1087 | BitWrite <= xmit_shiftreg[5]; |
---|
1088 | rcvr_shiftreg[4] <= 1'b1; |
---|
1089 | end |
---|
1090 | 5: begin |
---|
1091 | BitWrite <= xmit_shiftreg[6]; |
---|
1092 | rcvr_shiftreg[5] <= 1'b1; |
---|
1093 | end |
---|
1094 | 6: begin |
---|
1095 | BitWrite <= xmit_shiftreg[7]; |
---|
1096 | rcvr_shiftreg[6] <= 1'b1; |
---|
1097 | end |
---|
1098 | 7: begin |
---|
1099 | BitWrite <= xmit_shiftreg[0]; |
---|
1100 | rcvr_shiftreg[7] <= 1'b1; |
---|
1101 | end |
---|
1102 | endcase |
---|
1103 | end |
---|
1104 | 2'b01: begin |
---|
1105 | BitWrite <= 1'b0; |
---|
1106 | case(index) |
---|
1107 | 0: |
---|
1108 | rcvr_shiftreg[0] <= 1'b0; |
---|
1109 | 1: |
---|
1110 | rcvr_shiftreg[1] <= 1'b0; |
---|
1111 | 2: |
---|
1112 | rcvr_shiftreg[2] <= 1'b0; |
---|
1113 | 3: |
---|
1114 | rcvr_shiftreg[3] <= 1'b0; |
---|
1115 | 4: |
---|
1116 | rcvr_shiftreg[4] <= 1'b0; |
---|
1117 | 5: |
---|
1118 | rcvr_shiftreg[5] <= 1'b0; |
---|
1119 | 6: |
---|
1120 | rcvr_shiftreg[6] <= 1'b0; |
---|
1121 | 7: |
---|
1122 | rcvr_shiftreg[7] <= 1'b0; |
---|
1123 | endcase |
---|
1124 | end |
---|
1125 | 2'b10: begin |
---|
1126 | BitWrite <= 1'b1; |
---|
1127 | case(index) |
---|
1128 | 0: |
---|
1129 | rcvr_shiftreg[0] <= 1'b0; |
---|
1130 | 1: |
---|
1131 | rcvr_shiftreg[1] <= 1'b0; |
---|
1132 | 2: |
---|
1133 | rcvr_shiftreg[2] <= 1'b0; |
---|
1134 | 3: |
---|
1135 | rcvr_shiftreg[3] <= 1'b0; |
---|
1136 | 4: |
---|
1137 | rcvr_shiftreg[4] <= 1'b0; |
---|
1138 | 5: |
---|
1139 | rcvr_shiftreg[5] <= 1'b0; |
---|
1140 | 6: |
---|
1141 | rcvr_shiftreg[6] <= 1'b0; |
---|
1142 | 7: |
---|
1143 | rcvr_shiftreg[7] <= 1'b0; |
---|
1144 | endcase |
---|
1145 | end |
---|
1146 | 2'b11: begin |
---|
1147 | BitWrite <= 1'b1; |
---|
1148 | case(index) |
---|
1149 | 0: begin |
---|
1150 | rcvr_shiftreg[0] <= 1'b1; |
---|
1151 | rcvr_shiftreg[1] <= 1'b1; |
---|
1152 | end |
---|
1153 | 1: begin |
---|
1154 | rcvr_shiftreg[1] <= 1'b1; |
---|
1155 | rcvr_shiftreg[2] <= 1'b1; |
---|
1156 | end |
---|
1157 | 2: begin |
---|
1158 | rcvr_shiftreg[2] <= 1'b1; |
---|
1159 | rcvr_shiftreg[3] <= 1'b1; |
---|
1160 | end |
---|
1161 | 3: begin |
---|
1162 | rcvr_shiftreg[3] <= 1'b1; |
---|
1163 | rcvr_shiftreg[4] <= 1'b1; |
---|
1164 | end |
---|
1165 | 4: begin |
---|
1166 | rcvr_shiftreg[4] <= 1'b1; |
---|
1167 | rcvr_shiftreg[5] <= 1'b1; |
---|
1168 | end |
---|
1169 | 5: begin |
---|
1170 | rcvr_shiftreg[5] <= 1'b1; |
---|
1171 | rcvr_shiftreg[6] <= 1'b1; |
---|
1172 | end |
---|
1173 | 6: begin |
---|
1174 | rcvr_shiftreg[6] <= 1'b1; |
---|
1175 | rcvr_shiftreg[7] <= 1'b1; |
---|
1176 | end |
---|
1177 | 7: begin |
---|
1178 | rcvr_shiftreg[7] <= 1'b1; |
---|
1179 | rcvr_shiftreg[0] <= 1'b1; |
---|
1180 | end |
---|
1181 | endcase |
---|
1182 | end |
---|
1183 | endcase // case({BitRead1,BitRead2}) |
---|
1184 | OneWireIO <= WriteBit; |
---|
1185 | end |
---|
1186 | |
---|
1187 | // WriteBit actually writes the chosen bit to the One Wire bus. |
---|
1188 | WriteBit: |
---|
1189 | begin |
---|
1190 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
1191 | case(index) |
---|
1192 | 0: |
---|
1193 | rcvr_shiftreg[1] <= BitWrite; |
---|
1194 | 1: |
---|
1195 | rcvr_shiftreg[2] <= BitWrite; |
---|
1196 | 2: |
---|
1197 | rcvr_shiftreg[3] <= BitWrite; |
---|
1198 | 3: |
---|
1199 | rcvr_shiftreg[4] <= BitWrite; |
---|
1200 | 4: |
---|
1201 | rcvr_shiftreg[5] <= BitWrite; |
---|
1202 | 5: |
---|
1203 | rcvr_shiftreg[6] <= BitWrite; |
---|
1204 | 6: |
---|
1205 | rcvr_shiftreg[7] <= BitWrite; |
---|
1206 | 7: |
---|
1207 | rcvr_shiftreg[0] <= BitWrite; |
---|
1208 | endcase |
---|
1209 | if(!BitWrite) |
---|
1210 | begin |
---|
1211 | if(OD) |
---|
1212 | OneWireIO <= ODWriteZero; |
---|
1213 | else |
---|
1214 | OneWireIO <= WriteZero; |
---|
1215 | end |
---|
1216 | else |
---|
1217 | begin |
---|
1218 | if(OD && (TimeSlotCnt == bit_ts_writeone_high_od)) |
---|
1219 | OneWireIO <= ODWriteOne; |
---|
1220 | else if (!LLM && (TimeSlotCnt == bit_ts_writeone_high)) //5 7_25_01 |
---|
1221 | OneWireIO <= WriteOne; |
---|
1222 | else if (LLM && (TimeSlotCnt == bit_ts_writeone_high_ll)) |
---|
1223 | OneWireIO <= WriteOne; |
---|
1224 | end |
---|
1225 | end |
---|
1226 | |
---|
1227 | // WaitTS waits until the timeslot is completed, 80us. When done with |
---|
1228 | // that timeslot, the index will be incremented. |
---|
1229 | WaitTS: |
---|
1230 | begin |
---|
1231 | SET_IOSHRT <= 0; |
---|
1232 | TimeSlotCnt <= TimeSlotCnt + 1; |
---|
1233 | if(OD) |
---|
1234 | begin |
---|
1235 | if(TimeSlotCnt == bit_ts_end_od) //11 7_25_01 |
---|
1236 | OneWireIO <= IndexInc; |
---|
1237 | end |
---|
1238 | else |
---|
1239 | if(((TimeSlotCnt == bit_ts_end) && !LLM) || ((TimeSlotCnt==bit_ts_end_ll) && LLM)) |
---|
1240 | OneWireIO <= IndexInc; |
---|
1241 | if(DQ_IN) |
---|
1242 | LOW_DONE <= 1; |
---|
1243 | end |
---|
1244 | |
---|
1245 | // IndexInc incs the index by 1 if normal write, by 2 if in SRA |
---|
1246 | IndexInc: |
---|
1247 | begin |
---|
1248 | if(!sr_a) |
---|
1249 | index <= index + 1; |
---|
1250 | else |
---|
1251 | begin |
---|
1252 | index <= index + 2; |
---|
1253 | First <= 1'b0; |
---|
1254 | end |
---|
1255 | |
---|
1256 | if(BIT_CTL || (index == 8-1 && !sr_a) || (index == 8-2 && sr_a) ) |
---|
1257 | begin // Added BIT_CTL - GAG |
---|
1258 | byte_done <= 1'b1; |
---|
1259 | OneWireIO <= UpdateBuff; |
---|
1260 | end |
---|
1261 | else |
---|
1262 | begin |
---|
1263 | if((index == 7-1) && !sr_a) |
---|
1264 | last_rcvr_bit <= 1'b1; |
---|
1265 | else |
---|
1266 | if((index == 6-2) && sr_a) |
---|
1267 | last_rcvr_bit <= 1'b1; |
---|
1268 | OneWireIO <= DQLOW; |
---|
1269 | TimeSlotCnt <= 0; |
---|
1270 | end |
---|
1271 | |
---|
1272 | LOW_DONE <= 0; |
---|
1273 | end |
---|
1274 | |
---|
1275 | UpdateBuff: |
---|
1276 | begin |
---|
1277 | OneWireIO <= IdleS; |
---|
1278 | if(DQ_IN && STP_SPLY) |
---|
1279 | LOW_DONE <= 1; |
---|
1280 | end |
---|
1281 | endcase |
---|
1282 | endmodule |
---|