1 | /*! \file ofdm_txrx_mimo_regMacros.h |
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2 | \brief Header file for PHY register access |
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3 | |
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4 | @author Patrick Murphy |
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5 | |
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6 | This header file contains macros using the naming scheme previously used by sysgen2opb. These are the macros warpphy/warpmac call to interact with the PHY. |
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7 | This file will only be used with EDK 10.1+ designs. For projects built using sysgen2opb and EDK 9.1, these macros will be defined by the ofdm_txrx_mimo.h header |
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8 | created by sysgen2opb during the EDK export from sysgen. |
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9 | */ |
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10 | |
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11 | #include "xbasic_types.h" |
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12 | #include "xstatus.h" |
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13 | #include "xio.h" |
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14 | |
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15 | //PKTDET MACROS |
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16 | |
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17 | //Shortcuts for register bit masks |
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18 | // Masks for pktDet_status read-only register XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_STATUS |
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19 | #define PKTDET_IDLEDIFS 0x1 |
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20 | #define PKTDET_DETANTA 0x2 |
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21 | #define PKTDET_DETANTB 0x4 |
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22 | #define PKTDET_IDLECOUNT 0x3FF0 |
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23 | |
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24 | // Masks for pktDet_controlBits read-write register XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS_W |
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25 | #define PKTDET_RESETSUM 0x01 //1=Reset running averagers |
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26 | #define PKTDET_IGNOREDET 0x02 //1=disable pktDet output |
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27 | #define PKTDET_RSSICLKRATIO 0x04 //0=sys_clk/4, 1=sys_clk/8 |
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28 | #define PKTDET_CSMAENIDLE 0x08 //Enable IDLE output & register |
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29 | #define PKTDET_DETMODE 0x10 //1=OR ANTA/ANTB, 0=AND ANTA/ANTB |
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30 | #define PKTDET_MASK_ANTA 0x20 //1=listen to AntA for pktDet |
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31 | #define PKTDET_MASK_ANTB 0x40 //1=listen to AntB for pktDet |
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32 | #define PKTDET_ANTMASKS (PKTDET_MASK_ANTA | PKTDET_MASK_ANTB) //1=listen to ANT A for detections, 2=listen to ANT B, 3=listen to both |
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33 | #define PKTDET_EXTDETEN 0x80 |
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34 | #define PKTDET_RSSIDETEN 0x100 |
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35 | #define PKTDET_CORRDETEN 0x200 |
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36 | |
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37 | // Masks for pktDet_durations read-write register XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_DURATIONS_W |
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38 | #define PKTDET_MINDURATION_MASK 0x00007FF //UFix11_0, 11 LSB |
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39 | #define PKTDET_DIFSPERIOD_MASK 0x01FF800 //UFix10_0, ll-bits offset from LSB |
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40 | #define PKTDET_RSSIAVGLENGTH_MASK 0x3E00000 //UFix5_0, 21-bits offset from LSB |
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41 | |
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42 | //Masks for pktDet_thresholds read-write register XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_THRESHOLDS_W |
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43 | #define PKTDET_DETTHRESH_MASK 0xFFFF //UFix16_0, 16LSB |
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44 | #define PKTDET_CSMATHRESH_MASK 0xFFFF0000 //UFix16_0, 16MSB |
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45 | |
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46 | //The packet detector captures the output of its running RSSI sums when the incoming packet's payload starts (after the preamble) |
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47 | #define ofdm_txrx_mimo_ReadReg_Rx_PktDet_midPktRSSI_antA() (XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_MIDPACKETRSSI)&0xFFFF) //16 LSB is antenna A |
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48 | #define ofdm_txrx_mimo_ReadReg_Rx_PktDet_midPktRSSI_antB() ( (XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_MIDPACKETRSSI)&0xFFFF0000) >> 16) //16 MSB is antenna B |
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49 | |
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50 | #define ofdm_txrx_mimo_ReadReg_Rx_PktDet_idleForDifs() (XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_STATUS)&PKTDET_IDLEDIFS) |
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51 | |
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52 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_resetSum(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_RESETSUM))|((Value<<0)&PKTDET_RESETSUM))) |
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53 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_ignoreDet(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_IGNOREDET))|((Value<<1)&PKTDET_IGNOREDET))) |
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54 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_setRSSIclkRatio(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_RSSICLKRATIO))|((Value<<2)&PKTDET_RSSICLKRATIO))) |
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55 | #define ofdm_txrx_mimo_WriteReg_Rx_CSMA_enableIdle(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_CSMAENIDLE))|((Value<<3)&PKTDET_CSMAENIDLE))) |
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56 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_setMode(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_DETMODE))|((Value<<4)&PKTDET_DETMODE))) |
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57 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_setMask(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_ANTMASKS))|((Value)&PKTDET_ANTMASKS))) |
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58 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_extDetEn(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_EXTDETEN))|((Value)*PKTDET_EXTDETEN))) |
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59 | |
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60 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_rssiDetEn(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_RSSIDETEN))|((Value)*PKTDET_RSSIDETEN))) |
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61 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_corrDetEn(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_CONTROLBITS)&(~PKTDET_CORRDETEN))|((Value)*PKTDET_CORRDETEN))) |
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62 | |
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63 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_setMinDuration(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_DURATIONS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_DURATIONS)&(~PKTDET_MINDURATION_MASK))|((Value<<0)&PKTDET_MINDURATION_MASK))) |
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64 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_setDIFSPeriod(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_DURATIONS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_DURATIONS)&(~PKTDET_DIFSPERIOD_MASK))|((Value<<11)&PKTDET_DIFSPERIOD_MASK))) |
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65 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_setAvgLen(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_DURATIONS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_DURATIONS)&(~PKTDET_RSSIAVGLENGTH_MASK))|((Value<<21)&PKTDET_RSSIAVGLENGTH_MASK))) |
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66 | |
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67 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_setThresh(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_THRESHOLDS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_THRESHOLDS)&(~PKTDET_DETTHRESH_MASK))|((Value<<0)&PKTDET_DETTHRESH_MASK))) |
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68 | #define ofdm_txrx_mimo_WriteReg_Rx_CSMA_setThresh(Value) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_THRESHOLDS,(XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_THRESHOLDS)&(~PKTDET_CSMATHRESH_MASK))|((Value<<16)&PKTDET_CSMATHRESH_MASK))) |
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69 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDetCorr_params(corrThresh, corrMinPower) (XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTDET_AUTOCORRPARAMS, ((corrThresh & 0xFF) | ((corrMinPower&0xFFFF)<<8)))) |
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70 | |
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71 | //Macros to write PHY registers, using naming scheme from sysgen2opb's auto-generated driver header |
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72 | #define ofdm_txrx_mimo_WriteReg_Rx_ControlBits(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CONTROLBITS, (Xuint32)(Value)) |
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73 | #define ofdm_txrx_mimo_WriteReg_Rx_OFDM_SymbolCounts(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_OFDM_SYMBOLCOUNTS, (Xuint32)(Value)) |
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74 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PKTDET_DELAY, (Xuint32)(Value)) |
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75 | #define ofdm_txrx_mimo_WriteReg_Rx_PktDet_LongCorr_Params(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PKTDET_LONGCORR_PARAMS, (Xuint32)(Value)) |
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76 | #define ofdm_txrx_mimo_WriteReg_Rx_pktByteNums(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PKTBYTENUMS, (Xuint32)(Value)) |
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77 | #define ofdm_txrx_mimo_WriteReg_Rx_pktDet_Tresholds(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PKTDET_TRESHOLDS, (Xuint32)(Value)) |
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78 | #define ofdm_txrx_mimo_WriteReg_TxRx_FFT_Scaling(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_FFT_SCALING, (Xuint32)(Value)) |
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79 | #define ofdm_txrx_mimo_WriteReg_TxRx_Interrupt_PktBuf_Ctrl(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_INTERRUPT_PKTBUF_CTRL, (Xuint32)(Value)) |
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80 | #define ofdm_txrx_mimo_WriteReg_Rx_Constellation_Scaling(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CONSTELLATION_SCALING, (Xuint32)(Value)) |
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81 | #define ofdm_txrx_mimo_WriteReg_Tx_Scaling(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_SCALING, (Xuint32)(Value)) |
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82 | |
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83 | #define ofdm_txrx_mimo_WriteReg_TxRx_Pilots_Index(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_PILOTS_INDEX, (Xuint32)(Value)) |
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84 | #define ofdm_txrx_mimo_WriteReg_TxRx_Pilots_Values(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_PILOTS_VALUES, (Xuint32)(Value)) |
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85 | #define ofdm_rx_mimo_WriteReg_Rx_AFScaling(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_AF_TXSCALING, (Xuint32)(Value)) |
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86 | #define ofdm_rx_mimo_WriteReg_Rx_PilotCalcParams(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PILOTCALCPARAMS, (Xuint32)(Value)) |
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87 | |
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88 | #define ofdm_txrx_mimo_Readreg_Rx_CFOest_Coarse(BaseAddress, Value) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_COARSECFOEST) |
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89 | #define ofdm_txrx_mimo_Readreg_Rx_CFOest_Pilots(BaseAddress, Value) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PILOTCFOEST) |
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90 | |
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91 | #define ofdm_txrx_mimo_WriteReg_Tx_OFDM_SymCounts(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_OFDM_SYMCOUNTS, (Xuint32)(Value)) |
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92 | #define ofdm_txrx_mimo_WriteReg_Tx_PreambleMasking(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_PREAMBLEMASKING, (Xuint32)(Value)) |
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93 | #define ofdm_txrx_mimo_WriteReg_Tx_Start_Reset_Control(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_START_RESET_CONTROL, (Xuint32)(Value)) |
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94 | #define ofdm_txrx_mimo_WriteReg_Tx_ControlBits(BaseAddress, Value) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_CONTROLBITS, (Xuint32)(Value)) |
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95 | |
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96 | //Macros to read PHY registers, using naming scheme from sysgen2opb's auto-generated driver header |
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97 | #define ofdm_txrx_mimo_ReadReg_Rx_ControlBits(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CONTROLBITS) |
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98 | #define ofdm_txrx_mimo_ReadReg_Rx_OFDM_SymbolCounts(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_OFDM_SYMBOLCOUNTS) |
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99 | #define ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PKTDET_DELAY) |
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100 | #define ofdm_txrx_mimo_ReadReg_Rx_PktDet_LongCorr_Params(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PKTDET_LONGCORR_PARAMS) |
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101 | #define ofdm_txrx_mimo_ReadReg_Rx_pktByteNums(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PKTBYTENUMS) |
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102 | #define ofdm_txrx_mimo_ReadReg_TxRx_Interrupt_PktBuf_Ctrl(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_INTERRUPT_PKTBUF_CTRL) |
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103 | #define ofdm_txrx_mimo_ReadReg_Tx_OFDM_SymCounts(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_OFDM_SYMCOUNTS) |
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104 | #define ofdm_txrx_mimo_ReadReg_Tx_Start_Reset_Control(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_START_RESET_CONTROL) |
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105 | #define ofdm_txrx_mimo_ReadReg_Tx_ControlBits(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_CONTROLBITS) |
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106 | #define ofdm_txrx_mimo_ReadReg_Rx_Gains(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_GAINS) |
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107 | #define ofdm_txrx_mimo_ReadReg_Rx_BER_Errors(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_BER_ERRORS) |
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108 | #define ofdm_txrx_mimo_ReadReg_Rx_BER_TotalBits(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_BER_TOTALBITS) |
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109 | #define ofdm_txrx_mimo_ReadReg_Rx_packet_done(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PKTDONE_INTERRUPTSTATUS) |
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110 | #define ofdm_txrx_mimo_ReadReg_Tx_PktRunning(BaseAddress) XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_PKTRUNNING) |
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