1 | /** @file wlan_phy_util.c |
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2 | * @brief Physical Layer Utility |
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3 | * |
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4 | * This contains code for configuring low-level parameters in the PHY and hardware. |
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5 | * |
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6 | * @copyright Copyright 2013-2019, Mango Communications. All rights reserved. |
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7 | * Distributed under the Mango Communications Reference Design License |
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8 | * See LICENSE.txt included in the design archive or |
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9 | * at http://mangocomm.com/802.11/license |
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10 | * |
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11 | * This file is part of the Mango 802.11 Reference Design (https://mangocomm.com/802.11) |
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12 | */ |
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13 | /***************************** Include Files *********************************/ |
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14 | |
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15 | // Xilinx SDK includes |
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16 | #include "xio.h" |
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17 | #include "xparameters.h" |
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18 | |
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19 | // WLAN includes |
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20 | #include "wlan_platform_low.h" |
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21 | #include "wlan_platform_common.h" |
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22 | #include "wlan_mac_mailbox_util.h" |
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23 | #include "wlan_phy_util.h" |
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24 | #include "wlan_mac_low.h" |
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25 | #include "wlan_mac_common.h" |
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26 | #include "w3_low.h" |
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27 | #include "w3_mac_phy_regs.h" |
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28 | #include "wlan_common_types.h" |
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29 | #include "w3_phy_util.h" |
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30 | #include "wlan_mac_pkt_buf_util.h" |
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31 | |
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32 | |
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33 | /*****************************************************************************/ |
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34 | /** |
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35 | * Initialize the PHY |
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36 | * |
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37 | * @param None |
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38 | * |
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39 | * @return None |
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40 | * |
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41 | *****************************************************************************/ |
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42 | void wlan_phy_init() { |
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43 | |
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44 | // Assert Tx and Rx resets |
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45 | REG_SET_BITS(WLAN_RX_REG_CTRL, WLAN_RX_REG_CTRL_RESET); |
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46 | REG_SET_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_RESET); |
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47 | |
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48 | /************ PHY Rx ************/ |
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49 | |
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50 | // Set the max Tx/Rx packet sizes to 2KB (sane default for standard 802.11a/g links) |
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51 | wlan_phy_rx_set_max_pkt_len_kB( MAX_PKT_SIZE_KB ); |
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52 | wlan_phy_rx_set_max_pktbuf_addr( PKT_BUF_SIZE - sizeof(rx_frame_info_t) - PHY_RX_PKT_BUF_PHY_HDR_SIZE ); |
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53 | |
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54 | // WLAN_RX_DSSS_CFG reg |
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55 | // Configure the DSSS Rx pipeline |
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56 | // wlan_phy_DSSS_rx_config(sync_score_thresh, sync_timeout, sfd_timeout, search_time) |
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57 | wlan_phy_DSSS_rx_config(48, 45, 52, 39); |
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58 | |
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59 | // WLAN_RX_PKT_DET_DSSS_CFG reg |
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60 | // Configure the DSSS auto-correlation packet detector |
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61 | // wlan_phy_pktDet_autoCorr_dsss_cfg(corr_thresh, energy_thresh) |
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62 | // |
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63 | // Note: the below parameters will configure the packet detector such that |
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64 | // around 50% of short DSSS frames are successfully decoded at -82dBm. The |
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65 | // DSSS receiver can be made more sensitive by lowering the energy requirement |
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66 | // argument or clearing the WLAN_RX_REG_CFG_DSSS_RX_REQ_PKT_DET bit. |
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67 | wlan_phy_rx_pktDet_autoCorr_dsss_cfg(110, 60); |
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68 | |
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69 | // WLAN_RX_PKT_DET_OFDM_CFG reg |
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70 | // args: (corr_thresh, energy_thresh, min_dur, post_wait) |
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71 | // Using defaults from set_phy_samp_rate(20) |
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72 | wlan_phy_rx_pktDet_autoCorr_ofdm_cfg(100, 15, 4, 0x3F); |
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73 | |
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74 | // WLAN_RX_REG_CFG reg |
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75 | // Configure DSSS Rx to not wait for DSSS pkt det |
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76 | REG_CLEAR_BITS(WLAN_RX_REG_CFG, (WLAN_RX_REG_CFG_DSSS_RX_REQ_PKT_DET)); |
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77 | |
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78 | // Configure OFDM Rx to wait for pkt det before starting Rx |
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79 | REG_CLEAR_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_OFDM_RX_REQ_PKT_DET); |
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80 | |
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81 | // Enable the OFDM Rx pipeline |
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82 | REG_CLEAR_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_DISABLE_OFDM_RX); |
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83 | |
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84 | // Enable LTS-based CFO correction |
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85 | REG_CLEAR_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_CFO_EST_BYPASS); |
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86 | |
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87 | // Enable byte order swap for payloads and chan ests |
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88 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_BUF_WEN_SWAP); |
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89 | REG_CLEAR_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_CHAN_EST_WEN_SWAP); |
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90 | |
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91 | // Enable writing OFDM chan ests to Rx pkt buffer |
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92 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_RECORD_CHAN_EST); |
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93 | |
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94 | // The rate/length BUSY logic should hold the pkt det signal high to avoid |
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95 | // spurious AGC and detection events during an unsupported waveform |
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96 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_BUSY_HOLD_PKT_DET); |
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97 | |
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98 | // Block Rx inputs during Tx |
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99 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_USE_TX_SIG_BLOCK); |
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100 | |
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101 | // Enable HTMF waveform (11n waveform) detection in the PHY Rx |
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102 | // Disabling HTMF detection reverts the PHY to <v1.3 behavior where |
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103 | // every reception is handled as NONHT (11a) |
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104 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_ENABLE_HTMF_DET); |
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105 | |
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106 | // Enable VHT waveform detection - the PHY can't decode VHT waveforms |
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107 | // but enabling detection allows early termination with a header error |
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108 | // instead of attempting to decode the VHT waveform as NONHT |
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109 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_ENABLE_VHT_DET); |
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110 | |
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111 | // Keep CCA.BUSY asserted when DSSS Rx is active |
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112 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_DSSS_ASSERTS_CCA); |
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113 | |
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114 | // WLAN_RX_FFT_CFG reg |
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115 | // FFT config |
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116 | wlan_phy_rx_config_fft(64, 16); |
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117 | wlan_phy_rx_set_fft_window_offset(7); |
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118 | wlan_phy_rx_set_fft_scaling(5); |
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119 | |
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120 | // WLAN_RX_LTS_CFG reg |
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121 | // Set LTS correlation threshold, timeout and allowed peak separation times |
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122 | // 1023 disables LTS threshold switch (one threshold worked across SNRs in our testing) |
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123 | // Timeout value is doubled in hardware (350/2 becomes a timeout of 350 sample periods) |
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124 | // Peak separation is 3-bit mask, allowing 63/64/65 sample periods between peaks |
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125 | wlan_phy_rx_lts_corr_config(1023 * PHY_RX_RSSI_SUM_LEN, 350/2, 0x7); |
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126 | |
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127 | // WLAN_RX_LTS_THRESH reg |
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128 | // LTS correlation thresholds (low NSR, high SNR) |
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129 | wlan_phy_rx_lts_corr_thresholds(9000, 9000); |
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130 | |
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131 | // WLAN_RX_LTS_PEAKTYPE_THRESH reg |
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132 | // LTS correlation peak-type (big vs small) thresholds (low NSR, high SNR) |
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133 | // TODO: We can explore the peaktype dimension further in a future release |
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134 | wlan_phy_rx_lts_corr_peaktype_thresholds(5000, 5000); //0xFFFF arguments to disable |
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135 | |
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136 | // WLAN_RX_PKT_DET_OFDM_CFG reg |
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137 | // Configure RSSI pkt det |
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138 | // RSSI pkt det disabled by default (auto-corr detection worked across SNRs in our testing) |
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139 | // The summing logic realizes a sum of the length specified + 1 |
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140 | wlan_phy_rx_pktDet_RSSI_cfg( (PHY_RX_RSSI_SUM_LEN-1), ( PHY_RX_RSSI_SUM_LEN * 1023), 1); |
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141 | |
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142 | // WLAN_RX_PHY_CCA_CFG reg |
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143 | // Set physical carrier sensing threshold |
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144 | // CS thresh set by wlan_platform_set_phy_cs_thresh() - register field set to 0xFFFF here to disable |
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145 | // PHY CS assert until MAC code configures the desired threshold |
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146 | wlan_phy_rx_set_cca_thresh(0xFFFF); |
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147 | wlan_phy_rx_set_extension((6*20) - 64); // Overridden later by set_phy_samp_rate() |
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148 | |
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149 | // WLAN_RX_FEC_CFG reg |
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150 | // Set pre-quantizer scaling for decoder inputs |
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151 | // These values were found empirically by vs PER by sweeping scaling and attenuation |
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152 | wlan_phy_rx_set_fec_scaling(15, 15, 18, 22); |
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153 | |
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154 | // WLAN_RX_PKT_BUF_SEL reg |
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155 | // Configure channel estimate capture (64 subcarriers, 4 bytes each) |
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156 | // Chan ests start at sizeof(rx_frame_info) - sizeof(chan_est) |
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157 | wlan_phy_rx_pkt_buf_h_est_offset((PHY_RX_PKT_BUF_PHY_HDR_OFFSET - (64*4))); |
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158 | |
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159 | // WLAN_RX_CHAN_EST_SMOOTHING reg |
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160 | //Disable channel estimate smoothing |
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161 | wlan_phy_rx_chan_est_smoothing(0xFFF, 0x0); |
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162 | wlan_phy_rx_phy_mode_det_thresh(12); |
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163 | |
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164 | // WLAN_RX_PKT_BUF_MAXADDR reg |
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165 | wlan_phy_rx_set_max_pktbuf_addr(3800); |
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166 | |
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167 | // Configure the default antenna selections as SISO Tx/Rx on RF A |
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168 | wlan_rx_config_ant_mode(RX_ANTMODE_SISO_ANTA); |
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169 | |
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170 | /************ PHY Tx ************/ |
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171 | |
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172 | // De-assert all starts |
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173 | REG_CLEAR_BITS(WLAN_TX_REG_START, 0xFFFFFFFF); |
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174 | |
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175 | // TX_OUTPUT_SCALING register |
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176 | // Set digital scaling of preamble/payload signals before DACs (UFix12_0) |
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177 | wlan_phy_tx_set_scaling(0x2000, 0x2000); // Scaling of 2.0 |
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178 | |
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179 | // TX_CONFIG register |
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180 | // Enable the Tx PHY 4-bit TxEn port that captures the MAC's selection of active antennas per Tx |
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181 | REG_SET_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_USE_MAC_ANT_MASKS); |
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182 | |
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183 | // TX_FFT_CONFIG register |
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184 | // Configure the IFFT scaling and control logic |
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185 | // Current PHY design requires 64 subcarriers, 16-sample cyclic prefix |
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186 | wlan_phy_tx_config_fft(0x2A, 64, 16); |
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187 | |
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188 | // TX_TIMING register |
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189 | // Timing values overridden later in set_phy_samp_rate() |
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190 | wlan_phy_tx_set_extension(112); |
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191 | wlan_phy_tx_set_txen_extension(50); |
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192 | wlan_phy_tx_set_rx_invalid_extension(150); |
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193 | |
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194 | // TX_PKT_BUF_SEL register |
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195 | wlan_phy_tx_pkt_buf_phy_hdr_offset(PHY_TX_PKT_BUF_PHY_HDR_OFFSET); |
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196 | wlan_phy_tx_pkt_buf(0); |
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197 | |
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198 | |
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199 | /************ Wrap Up ************/ |
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200 | |
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201 | |
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202 | // De-assert resets |
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203 | REG_CLEAR_BITS(WLAN_RX_REG_CTRL, WLAN_RX_REG_CTRL_RESET); |
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204 | REG_CLEAR_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_RESET); |
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205 | |
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206 | // Let PHY Tx take control of radio TXEN/RXEN |
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207 | REG_CLEAR_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_SET_RC_RXEN); |
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208 | REG_SET_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_SET_RC_RXEN); |
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209 | |
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210 | return; |
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211 | } |
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212 | |
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213 | /*****************************************************************************/ |
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214 | /** |
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215 | * Configure the Rx Antenna Mode |
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216 | * |
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217 | * @param ant_mode - Antenna mode to set |
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218 | * |
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219 | * @return None |
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220 | * |
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221 | * @note There is no corresponding wlan_tx_config_ant_mode() because the transmit |
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222 | * antenna is set by the MAC software (ie mac_sw -> mac_hw -> phy_tx) for every packet |
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223 | * |
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224 | *****************************************************************************/ |
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225 | void wlan_rx_config_ant_mode(u32 ant_mode) { |
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226 | |
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227 | // Hold the Rx PHY in reset before changing any pkt det or radio enables |
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228 | REG_SET_BITS(WLAN_RX_REG_CTRL, WLAN_RX_REG_CTRL_RESET); |
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229 | |
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230 | wlan_platform_low_set_rx_ant_mode(ant_mode); |
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231 | |
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232 | // Disable all Rx modes first; selectively re-enabled in switch below |
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233 | REG_CLEAR_BITS(WLAN_RX_REG_CFG, (WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A | |
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234 | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B | |
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235 | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_C | |
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236 | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_D | |
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237 | WLAN_RX_REG_CFG_SWITCHING_DIV_EN | |
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238 | WLAN_RX_REG_CFG_PKT_DET_EN_EXT | |
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239 | WLAN_RX_REG_CFG_ANT_SEL_MASK)); |
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240 | |
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241 | // Set the antenna mode |
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242 | // |
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243 | // For each antenna mode: |
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244 | // - Enable packet detection |
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245 | // - Select I/Q stream for Rx PHY |
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246 | // - Give PHY control of Tx/Rx status |
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247 | // - Configure AGC |
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248 | // |
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249 | switch (ant_mode) { |
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250 | case RX_ANTMODE_SISO_ANTA: |
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251 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A); |
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252 | wlan_phy_select_rx_antenna(RX_ANTMODE_SISO_ANTA); |
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253 | break; |
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254 | |
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255 | case RX_ANTMODE_SISO_ANTB: |
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256 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B); |
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257 | wlan_phy_select_rx_antenna(RX_ANTMODE_SISO_ANTB); |
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258 | break; |
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259 | |
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260 | case RX_ANTMODE_SISO_ANTC: |
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261 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_C); |
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262 | wlan_phy_select_rx_antenna(RX_ANTMODE_SISO_ANTC); |
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263 | break; |
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264 | |
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265 | case RX_ANTMODE_SISO_ANTD: |
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266 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_D); |
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267 | wlan_phy_select_rx_antenna(RX_ANTMODE_SISO_ANTD); |
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268 | break; |
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269 | |
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270 | case RX_ANTMODE_SISO_SELDIV_2ANT: |
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271 | REG_SET_BITS(WLAN_RX_REG_CFG, (WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B | WLAN_RX_REG_CFG_SWITCHING_DIV_EN)); |
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272 | break; |
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273 | |
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274 | case RX_ANTMODE_SISO_SELDIV_4ANT: |
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275 | REG_SET_BITS(WLAN_RX_REG_CFG, (WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_C | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_D | WLAN_RX_REG_CFG_SWITCHING_DIV_EN)); |
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276 | break; |
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277 | |
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278 | default: |
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279 | // Default to SISO on A if user provides invalid mode |
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280 | xil_printf("wlan_rx_config_ant_mode ERROR: Invalid Mode - Defaulting to SISO on A\n"); |
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281 | |
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282 | REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A); |
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283 | wlan_phy_select_rx_antenna(RX_ANTMODE_SISO_ANTA); |
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284 | break; |
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285 | } |
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286 | |
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287 | // Release the PHY Rx reset |
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288 | REG_CLEAR_BITS(WLAN_RX_REG_CTRL, WLAN_RX_REG_CTRL_RESET); |
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289 | |
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290 | return; |
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291 | } |
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292 | |
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293 | /*****************************************************************************/ |
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294 | /** |
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295 | * Transmission debug methods |
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296 | * |
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297 | * @param Variable |
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298 | * |
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299 | * @return Variable |
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300 | * |
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301 | * @note These function is for debug use only. |
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302 | * |
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303 | *****************************************************************************/ |
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304 | inline void wlan_tx_start() { |
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305 | // Start the PHY Tx immediately; this bypasses the mac_hw MPDU Tx state machine |
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306 | // This should only be used for debug - normal transmissions should use mac_hw |
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307 | // |
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308 | REG_SET_BITS(WLAN_TX_REG_START, WLAN_TX_REG_START_VIA_RC); |
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309 | REG_CLEAR_BITS(WLAN_TX_REG_START, WLAN_TX_REG_START_VIA_RC); |
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310 | |
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311 | return; |
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312 | } |
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