[2086] | 1 |
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[4733] | 2 | # ##############################################################################
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[3394] | 3 | # Mango 802.11 Reference Design
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| 4 | # XPS Hardware Specification (system.mhs)
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[6308] | 5 | # Copyright 2018 Mango Communications
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[3394] | 6 | # Distributed under the Mango Research License:
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| 7 | # http://mangocomm.com/802.11/license
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[4733] | 8 | # ##############################################################################
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[2086] | 9 | PARAMETER VERSION = 2.1.0
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| 10 |
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| 11 |
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[4733] | 12 | # ##############################################################################
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| 13 | # Top Level Ports
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| 14 | # ##############################################################################
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[2086] | 15 | PORT reset_pb = reset_pb, DIR = I, SIGIS = RST, RST_POLARITY = 1
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| 16 | # USERIO
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| 17 | PORT userio_pb_d = userio_pb_d, DIR = I
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| 18 | PORT userio_pb_m = userio_pb_m, DIR = I
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| 19 | PORT userio_pb_u = userio_pb_u, DIR = I
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| 20 | PORT userio_leds_green = userio_leds_green, DIR = O, VEC = [3:0]
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| 21 | PORT userio_leds_red = userio_leds_red, DIR = O, VEC = [3:0]
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| 22 | # PORT userio_dipsw = userio_dipsw, DIR = I, VEC = [0:3]
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| 23 | PORT userio_dipsw = userio_dipsw_b0 & userio_dipsw_b1 & userio_dipsw_b2 & userio_dipsw_b3, DIR = I, VEC = [0:3]
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| 24 | PORT userio_hexdisp_left = userio_hexdisp_left, DIR = O, VEC = [6:0]
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| 25 | PORT userio_hexdisp_right = userio_hexdisp_right, DIR = O, VEC = [6:0]
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| 26 | PORT userio_hexdisp_left_dp = userio_hexdisp_left_dp, DIR = O
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| 27 | PORT userio_hexdisp_right_dp = userio_hexdisp_right_dp, DIR = O
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| 28 | PORT userio_rfa_led_red = userio_rfa_led_red, DIR = O
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| 29 | PORT userio_rfa_led_green = userio_rfa_led_green, DIR = O
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| 30 | PORT userio_rfb_led_red = userio_rfb_led_red, DIR = O
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| 31 | PORT userio_rfb_led_green = userio_rfb_led_green, DIR = O
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| 32 | # Ethernet pins
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| 33 | PORT ETH_COMA = net_gnd, DIR = O
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| 34 | # ETH_A
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| 35 | PORT ETH_A_PHY_RST_N = ETH_A_PHY_RST_N, DIR = O
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| 36 | PORT ETH_A_MDIO = ETH_A_MDIO, DIR = IO
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| 37 | PORT ETH_A_MDC = ETH_A_MDC, DIR = O
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| 38 | PORT ETH_A_RGMII_TXC = ETH_A_RGMII_TXC, DIR = O
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| 39 | PORT ETH_A_RGMII_TX_CTL = ETH_A_RGMII_TX_CTL, DIR = O
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| 40 | PORT ETH_A_RGMII_TXD = ETH_A_RGMII_TXD, DIR = O, VEC = [3:0]
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| 41 | PORT ETH_A_RGMII_RXC = ETH_A_RGMII_RXC, DIR = I
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| 42 | PORT ETH_A_RGMII_RX_CTL = ETH_A_RGMII_RX_CTL, DIR = I
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| 43 | PORT ETH_A_RGMII_RXD = ETH_A_RGMII_RXD, DIR = I, VEC = [3:0]
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| 44 | PORT ETH_A_PD = net_gnd, DIR = O
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[2254] | 45 | # ETH_B
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| 46 | PORT ETH_B_MDIO = ETH_B_MDIO, DIR = IO
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| 47 | PORT ETH_B_MDC = ETH_B_MDC, DIR = O
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| 48 | PORT ETH_B_RGMII_TXC = ETH_B_RGMII_TXC, DIR = O
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| 49 | PORT ETH_B_RGMII_TX_CTL = ETH_B_RGMII_TX_CTL, DIR = O
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| 50 | PORT ETH_B_RGMII_TXD = ETH_B_RGMII_TXD, DIR = O, VEC = [3:0]
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| 51 | PORT ETH_B_RGMII_RXC = ETH_B_RGMII_RXC, DIR = I
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| 52 | PORT ETH_B_RGMII_RX_CTL = ETH_B_RGMII_RX_CTL, DIR = I
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| 53 | PORT ETH_B_RGMII_RXD = ETH_B_RGMII_RXD, DIR = I, VEC = [3:0]
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| 54 | PORT ETH_B_PD = net_gnd, DIR = O
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[2086] | 55 | # USB UART
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| 56 | PORT usb_uart_rx = usb_uart_rx, DIR = I
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| 57 | PORT usb_uart_tx = usb_uart_tx, DIR = O
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| 58 | # AD9512 clock buffer control pins (RF reference & sampling clocks)
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[4705] | 59 | PORT clk_rfref_spi_cs_n = clk_rfref_spi_cs_n, DIR = O
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| 60 | PORT clk_rfref_spi_mosi = clk_rfref_spi_mosi, DIR = O
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| 61 | PORT clk_rfref_spi_sclk = clk_rfref_spi_sclk, DIR = O
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| 62 | PORT clk_rfref_spi_miso = clk_rfref_spi_miso, DIR = I
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| 63 | PORT clk_rfref_func = net_vcc, DIR = O
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| 64 | PORT clk_samp_spi_cs_n = clk_samp_spi_cs_n, DIR = O
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| 65 | PORT clk_samp_spi_mosi = clk_samp_spi_mosi, DIR = O
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| 66 | PORT clk_samp_spi_sclk = clk_samp_spi_sclk, DIR = O
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| 67 | PORT clk_samp_spi_miso = clk_samp_spi_miso, DIR = I
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| 68 | PORT clk_samp_func = net_vcc, DIR = O
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| 69 | # CM-PLL pins
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| 70 | PORT cm_spi_sclk = cm_spi_sclk, DIR = O
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| 71 | PORT cm_spi_mosi = cm_spi_mosi, DIR = O
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| 72 | PORT cm_spi_miso = cm_spi_miso, DIR = I
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| 73 | PORT cm_spi_cs_n = cm_spi_cs_n, DIR = O
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| 74 | PORT cm_pll_status = cm_pll_status, DIR = I
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| 75 | PORT cm_switch = cm_switch, DIR = I, VEC = [2:0]
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| 76 | PORT pll_refclk_p = pll_refclk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
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| 77 | PORT pll_refclk_n = pll_refclk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
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[2797] | 78 | # IIC EEPROM pins on-board
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[4705] | 79 | PORT iic_eeprom_onboard_scl = iic_eeprom_onboard_scl, DIR = IO
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| 80 | PORT iic_eeprom_onboard_sda = iic_eeprom_onboard_sda, DIR = IO
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[2086] | 81 | # 80MHz sampling clock from AD9512
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[4705] | 82 | PORT samp_clk_p = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
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| 83 | PORT samp_clk_n = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
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[2086] | 84 | # 200MHz LVDS oscillator input
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[4705] | 85 | PORT osc200_p = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
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| 86 | PORT osc200_n = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
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[2086] | 87 | # AD9963 ADC/DAC control pins (RFA & RFB)
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[4705] | 88 | PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n, DIR = O
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[2086] | 89 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO
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[4705] | 90 | PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk, DIR = O
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| 91 | PORT RFA_AD_reset_n = RFA_AD_reset_n, DIR = O
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| 92 | PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n, DIR = O
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[2086] | 93 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO
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[4705] | 94 | PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk, DIR = O
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| 95 | PORT RFB_AD_reset_n = RFB_AD_reset_n, DIR = O
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[2086] | 96 | # RFA AD pins
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| 97 | PORT RFA_AD_TRXD = rfa_trxd, DIR = I, VEC = [11:0]
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| 98 | PORT RFA_AD_TRXCLK = rfa_trxclk, DIR = I
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| 99 | PORT RFA_AD_TRXIQ = rfa_trxiq, DIR = I
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| 100 | PORT RFA_AD_TXD = rfa_txd, DIR = O, VEC = [11:0]
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| 101 | PORT RFA_AD_TXIQ = rfa_txiq, DIR = O
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| 102 | PORT RFA_AD_TXCLK = rfa_txclk, DIR = O
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| 103 | # RFB AD pins
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| 104 | PORT RFB_AD_TRXD = rfb_trxd, DIR = I, VEC = [11:0]
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| 105 | PORT RFB_AD_TRXCLK = rfb_trxclk, DIR = I
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| 106 | PORT RFB_AD_TRXIQ = rfb_trxiq, DIR = I
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| 107 | PORT RFB_AD_TXD = rfb_txd, DIR = O, VEC = [11:0]
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| 108 | PORT RFB_AD_TXIQ = rfb_txiq, DIR = O
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| 109 | PORT RFB_AD_TXCLK = rfb_txclk, DIR = O
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| 110 | # RSSI ADC pins
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| 111 | PORT RFA_RSSI_D = RFA_RSSI_D, DIR = I, VEC = [9:0]
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| 112 | PORT RFB_RSSI_D = RFB_RSSI_D, DIR = I, VEC = [9:0]
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[2797] | 113 | PORT RF_RSSI_CLK = wlan_rssi_clk, DIR = O
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[2086] | 114 | PORT RF_RSSI_PD = net_gnd, DIR = O
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| 115 | # RFA transceiver and front-end
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[4705] | 116 | PORT RFA_TxEn = RFA_TxEn, DIR = O
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| 117 | PORT RFA_RxEn = RFA_RxEn, DIR = O
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| 118 | PORT RFA_RxHP = RFA_RxHP, DIR = O
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| 119 | PORT RFA_SHDN = RFA_SHDN, DIR = O
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| 120 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK, DIR = O
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| 121 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI, DIR = O
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| 122 | PORT RFA_SPI_CSn = RFA_SPI_CSn, DIR = O
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| 123 | PORT RFA_B = RFA_B, DIR = O, VEC = [0:6]
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| 124 | PORT RFA_LD = RFA_LD, DIR = I
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| 125 | PORT RFA_PAEn_24 = RFA_PAEn_24, DIR = O
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| 126 | PORT RFA_PAEn_5 = RFA_PAEn_5, DIR = O
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| 127 | PORT RFA_AntSw = RFA_AntSw, DIR = O, VEC = [0:1]
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[2086] | 128 | # RFB transceiver and front-end
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[4705] | 129 | PORT RFB_TxEn = RFB_TxEn, DIR = O
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| 130 | PORT RFB_RxEn = RFB_RxEn, DIR = O
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| 131 | PORT RFB_RxHP = RFB_RxHP, DIR = O
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| 132 | PORT RFB_SHDN = RFB_SHDN, DIR = O
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| 133 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK, DIR = O
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| 134 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI, DIR = O
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| 135 | PORT RFB_SPI_CSn = RFB_SPI_CSn, DIR = O
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| 136 | PORT RFB_B = RFB_B, DIR = O, VEC = [0:6]
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| 137 | PORT RFB_LD = RFB_LD, DIR = I
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| 138 | PORT RFB_PAEn_24 = RFB_PAEn_24, DIR = O
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| 139 | PORT RFB_PAEn_5 = RFB_PAEn_5, DIR = O
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| 140 | PORT RFB_AntSw = RFB_AntSw, DIR = O, VEC = [0:1]
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[2254] | 141 | # DDR3 SODIMM
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| 142 | PORT ddr3_sodimm_ck_p = ddr3_sodimm_ck_p, DIR = O, SIGIS = CLK, VEC = [1:0]
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| 143 | PORT ddr3_sodimm_ck_n = ddr3_sodimm_ck_n, DIR = O, SIGIS = CLK, VEC = [1:0]
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| 144 | PORT ddr3_sodimm_cke = ddr3_sodimm_cke, DIR = O
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| 145 | PORT ddr3_sodimm_cs_n = ddr3_sodimm_cs_n, DIR = O
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| 146 | PORT ddr3_sodimm_odt = ddr3_sodimm_odt, DIR = O
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| 147 | PORT ddr3_sodimm_ras_n = ddr3_sodimm_ras_n, DIR = O
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| 148 | PORT ddr3_sodimm_cas_n = ddr3_sodimm_cas_n, DIR = O
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| 149 | PORT ddr3_sodimm_we_n = ddr3_sodimm_we_n, DIR = O
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| 150 | PORT ddr3_sodimm_ba = ddr3_sodimm_ba, DIR = O, VEC = [2:0]
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| 151 | PORT ddr3_sodimm_addr = ddr3_sodimm_addr, DIR = O, VEC = [14:0]
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| 152 | PORT ddr3_sodimm_dq = ddr3_sodimm_dq, DIR = IO, VEC = [63:0]
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| 153 | PORT ddr3_sodimm_dm = ddr3_sodimm_dm, DIR = O, VEC = [7:0]
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| 154 | PORT ddr3_sodimm_reset_n = ddr3_sodimm_reset_n, DIR = O
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| 155 | PORT ddr3_sodimm_dqs_p = ddr3_sodimm_dqs_p, DIR = IO, VEC = [7:0]
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| 156 | PORT ddr3_sodimm_dqs_n = ddr3_sodimm_dqs_n, DIR = IO, VEC = [7:0]
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[5594] | 157 | # Debug pins (connected through w3_userio core)
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| 158 | PORT dbg_hdr = dbg_hdr, DIR = IO, VEC = [15:0]
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[2086] | 159 |
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| 160 |
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[4733] | 161 | # ##############################################################################
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| 162 | # WLAN Sysgen Peripherals
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| 163 | # ##############################################################################
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[5490] | 164 | BEGIN wlan_phy_tx_pmd_axiw
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[2086] | 165 | PARAMETER INSTANCE = wlan_phy_tx
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[6110] | 166 | PARAMETER HW_VER = 4.01.a
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[2086] | 167 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
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| 168 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
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| 169 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
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| 170 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
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| 171 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
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[4733] | 172 | PARAMETER C_BASEADDR = 0x40000000
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| 173 | PARAMETER C_HIGHADDR = 0x4000FFFF
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[2086] | 174 | BUS_INTERFACE PORTB = WLAN_TX_PKT_BUF_PORTB
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| 175 | BUS_INTERFACE S_AXI = mb_low_axi_periph
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| 176 | PORT axi_aclk = clk_160MHz
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| 177 | PORT sysgen_clk = clk_160MHz
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[5490] | 178 | PORT samp_ce = RF_AD_samp_ce
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[2405] | 179 | PORT rfa_dac_i = RFA_TX_I
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| 180 | PORT rfa_dac_q = RFA_TX_Q
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| 181 | PORT rfb_dac_i = RFB_TX_I
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| 182 | PORT rfb_dac_q = RFB_TX_Q
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[2254] | 183 | PORT rx_sigs_invalid = rx_sigs_invalid
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[2086] | 184 | # RC -> PHY start
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[2405] | 185 | PORT RC_PHY_START = tx_phy_start
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[2086] | 186 | # PHY -> RC state ctrl
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[2405] | 187 | PORT rc_usr_rxen = rc_usr_rxen
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[3596] | 188 | PORT rc_usr_txen_a = phy_rc_txen_a
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| 189 | PORT rc_usr_txen_b = phy_rc_txen_b
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[3602] | 190 | PORT rc_tx_gain_a = phy_rc_tx_gain_a
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| 191 | PORT rc_tx_gain_b = phy_rc_tx_gain_b
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[2086] | 192 | # MAC <-> Tx PHY ports
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[3602] | 193 | PORT phy_tx_gain_a = mac_phy_tx_gain_a
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| 194 | PORT phy_tx_gain_b = mac_phy_tx_gain_b
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[2086] | 195 | PORT phy_tx_pkt_buf = mac_phy_tx_pkt_buf
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[5490] | 196 | PORT phy_tx_phy_mode = mac_phy_tx_phy_mode
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[2086] | 197 | PORT phy_tx_start = mac_phy_tx_start
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| 198 | PORT phy_tx_done = mac_phy_tx_done
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| 199 | PORT phy_tx_started = mac_phy_tx_started
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[3596] | 200 | PORT phy_tx_ant_mask = mac_phy_tx_ant_mask
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[2086] | 201 | # Debug ports
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| 202 | PORT dbg_tx_running = dbg_tx_running
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| 203 | END
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| 204 |
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[5490] | 205 | BEGIN wlan_phy_rx_pmd_axiw
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[2086] | 206 | PARAMETER INSTANCE = wlan_phy_rx
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[6308] | 207 | PARAMETER HW_VER = 4.01.z
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[2086] | 208 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
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| 209 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
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| 210 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
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| 211 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
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| 212 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
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[4733] | 213 | PARAMETER C_BASEADDR = 0x41000000
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| 214 | PARAMETER C_HIGHADDR = 0x4100FFFF
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[2086] | 215 | BUS_INTERFACE PORTB = WLAN_RX_PKT_BUF_PORTB
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| 216 | BUS_INTERFACE S_AXI = mb_low_axi_periph
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| 217 | PORT axi_aclk = clk_160MHz
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| 218 | PORT sysgen_clk = clk_160MHz
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[5090] | 219 | # PORT pkt_det_in = net_wlan_phy_rx_pkt_det_in
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| 220 | PORT pkt_det_in = net_gnd
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[2254] | 221 | PORT rx_sigs_invalid = rx_sigs_invalid
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[5490] | 222 | PORT rx_iq_samp_ce = agc_iq_valid_out
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[2086] | 223 | PORT rfa_rx_i = agc_rfa_i
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| 224 | PORT rfa_rx_q = agc_rfa_q
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[4853] | 225 | PORT rfa_rssi = RFA_RSSI_D_REG
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[2405] | 226 | PORT rfb_rx_i = agc_rfb_i
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| 227 | PORT rfb_rx_q = agc_rfb_q
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[4853] | 228 | PORT rfb_rssi = RFB_RSSI_D_REG
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[2797] | 229 | PORT rssi_adc_clk = wlan_rssi_clk
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[2086] | 230 | PORT pkt_det_o = phy_rx_pkt_det
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| 231 | PORT rfa_g_rf = agc_rfa_g_rf
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| 232 | PORT rfa_g_bb = agc_rfa_g_bb
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[2405] | 233 | PORT rfb_g_rf = agc_rfb_g_rf
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| 234 | PORT rfb_g_bb = agc_rfb_g_bb
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| 235 | PORT agc_done = agc_done
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[5490] | 236 | # MAC <-> PHY ports
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| 237 | PORT phy_rx_reset = phy_rx_reset
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[3596] | 238 | PORT phy_rx_block_pktdet = phy_rx_block_pktdet
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[2086] | 239 | PORT phy_cca_ind_busy = mac_phy_cca_ind_busy
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| 240 | PORT phy_rx_data_byte = mac_phy_rx_data_byte
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| 241 | PORT phy_rx_data_bytenum = mac_phy_rx_data_bytenum
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| 242 | PORT phy_rx_data_done_ind = mac_phy_rx_data_done_ind
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| 243 | PORT phy_rx_data_ind = mac_phy_rx_data_ind
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| 244 | PORT phy_rx_end_ind = mac_phy_rx_end_ind
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| 245 | PORT phy_rx_end_rxerror = mac_phy_rx_end_rxerror
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| 246 | PORT phy_rx_fcs_good_ind = mac_phy_rx_fcs_good_ind
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[5490] | 247 | PORT phy_rx_phy_hdr_ind = mac_phy_rx_phy_hdr_ind
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| 248 | PORT phy_rx_phy_hdr_length = mac_phy_rx_phy_hdr_length
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| 249 | PORT phy_rx_phy_hdr_mcs = mac_phy_rx_phy_hdr_mcs
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| 250 | PORT phy_rx_phy_hdr_phy_mode = mac_phy_rx_phy_hdr_phy_mode
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| 251 | PORT phy_rx_phy_hdr_unsupported = mac_phy_rx_phy_hdr_unsupported
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[2086] | 252 | PORT phy_rx_start_ind = mac_phy_rx_start_ind
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| 253 | PORT phy_rx_start_phy_sel = phy_rx_start_phy_sel
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| 254 | # Debug ports
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[2797] | 255 | PORT dbg_dsss_rx_active = dbg_dsss_rx_active
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[2086] | 256 | PORT dbg_lts_timeout = dbg_lts_timeout
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[3596] | 257 | PORT dbg_pkt_det_dsss = dbg_pkt_det_dsss
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| 258 | PORT dbg_pkt_det_ofdm = dbg_pkt_det_ofdm
|
---|
[3758] | 259 | PORT dbg_payload = dbg_ofdm_rx_active
|
---|
[2086] | 260 | PORT dbg_rssi_det = dbg_rssi_det
|
---|
[2254] | 261 | PORT dbg_signal_err_disp = dbg_signal_err_disp
|
---|
[2086] | 262 | END
|
---|
| 263 |
|
---|
[4705] | 264 | BEGIN wlan_mac_hw_axiw
|
---|
| 265 | PARAMETER INSTANCE = wlan_mac_hw
|
---|
[6308] | 266 | PARAMETER HW_VER = 2.01.m
|
---|
[2086] | 267 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 268 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 269 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 270 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 271 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[4733] | 272 | PARAMETER C_BASEADDR = 0x42000000
|
---|
| 273 | PARAMETER C_HIGHADDR = 0x4200FFFF
|
---|
[2086] | 274 | BUS_INTERFACE S_AXI = mb_low_axi_periph
|
---|
| 275 | PORT axi_aclk = clk_160MHz
|
---|
| 276 | PORT sysgen_clk = clk_160MHz
|
---|
| 277 | PORT phy_cca_ind_busy = mac_phy_cca_ind_busy
|
---|
| 278 | PORT phy_rx_data_byte = mac_phy_rx_data_byte
|
---|
| 279 | PORT phy_rx_data_bytenum = mac_phy_rx_data_bytenum
|
---|
| 280 | PORT phy_rx_data_done_ind = mac_phy_rx_data_done_ind
|
---|
| 281 | PORT phy_rx_data_ind = mac_phy_rx_data_ind
|
---|
| 282 | PORT phy_rx_end_ind = mac_phy_rx_end_ind
|
---|
| 283 | PORT phy_rx_end_rxerror = mac_phy_rx_end_rxerror
|
---|
| 284 | PORT phy_rx_fcs_good_ind = mac_phy_rx_fcs_good_ind
|
---|
| 285 | PORT phy_rx_start_ind = mac_phy_rx_start_ind
|
---|
[4705] | 286 | PORT phy_rx_start_phy_sel = phy_rx_start_phy_sel
|
---|
[5490] | 287 | PORT phy_rx_reset = phy_rx_reset
|
---|
| 288 | PORT phy_rx_phy_hdr_ind = mac_phy_rx_phy_hdr_ind
|
---|
| 289 | PORT phy_rx_phy_hdr_length = mac_phy_rx_phy_hdr_length
|
---|
| 290 | PORT phy_rx_phy_hdr_mcs = mac_phy_rx_phy_hdr_mcs
|
---|
| 291 | PORT phy_rx_phy_hdr_phy_mode = mac_phy_rx_phy_hdr_phy_mode
|
---|
| 292 | PORT phy_rx_phy_hdr_unsupported = mac_phy_rx_phy_hdr_unsupported
|
---|
[2086] | 293 | PORT phy_tx_done = mac_phy_tx_done
|
---|
| 294 | PORT phy_tx_started = mac_phy_tx_started
|
---|
| 295 | PORT phy_tx_pkt_buf = mac_phy_tx_pkt_buf
|
---|
[5490] | 296 | PORT phy_tx_phy_mode = mac_phy_tx_phy_mode
|
---|
[2086] | 297 | PORT phy_tx_start = mac_phy_tx_start
|
---|
[3602] | 298 | PORT phy_tx_gain_a = mac_phy_tx_gain_a
|
---|
| 299 | PORT phy_tx_gain_b = mac_phy_tx_gain_b
|
---|
[3596] | 300 | PORT phy_tx_ant_mask = mac_phy_tx_ant_mask
|
---|
[2086] | 301 | PORT phy_rx_block_pktdet = phy_rx_block_pktdet
|
---|
[4733] | 302 | PORT mac_time_usec_lsb = mac_time_usec_lsb
|
---|
| 303 | PORT mac_time_usec_msb = mac_time_usec_msb
|
---|
[5010] | 304 | PORT mac_time_usec_frac = mac_time_usec_frac
|
---|
[6203] | 305 | PORT force_cca_busy = net_gnd
|
---|
| 306 | PORT force_start_postrx_timer1 = net_gnd
|
---|
| 307 | PORT aux_mac_hw_status0 = net_gnd
|
---|
| 308 | PORT aux_mac_hw_status1 = net_gnd
|
---|
[6308] | 309 | PORT aux_mac_hw_status2 = net_gnd
|
---|
| 310 | PORT aux_mac_hw_status3 = net_gnd
|
---|
[5594] | 311 | # # Debug outputs - can be routed to debug header
|
---|
| 312 | PORT dbg_backoff_a_active = dbg_mac_backoff_a_active
|
---|
| 313 | PORT dbg_backoff_c_active = dbg_mac_backoff_c_active
|
---|
| 314 | PORT dbg_eifs_sel = dbg_mac_eifs_sel
|
---|
| 315 | PORT dbg_idle_for_difs = dbg_mac_idle_for_difs
|
---|
| 316 | PORT dbg_nav_active = dbg_mac_nav_active
|
---|
| 317 | PORT dbg_tx_a_pending = dbg_mac_tx_a_pending
|
---|
| 318 | PORT dbg_tx_b_pending = dbg_mac_tx_b_pending
|
---|
| 319 | PORT dbg_tx_c_pending = dbg_mac_tx_c_pending
|
---|
[5743] | 320 | PORT dbg_tx_d_pending = dbg_mac_tx_d_pending
|
---|
[2086] | 321 | END
|
---|
| 322 |
|
---|
[5490] | 323 | BEGIN wlan_agc_axiw
|
---|
[2086] | 324 | PARAMETER INSTANCE = wlan_agc
|
---|
[6203] | 325 | PARAMETER HW_VER = 2.00.d
|
---|
[2086] | 326 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 327 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 328 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 329 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 330 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[4733] | 331 | PARAMETER C_BASEADDR = 0x43000000
|
---|
| 332 | PARAMETER C_HIGHADDR = 0x4300FFFF
|
---|
[2086] | 333 | BUS_INTERFACE S_AXI = mb_low_axi_periph
|
---|
| 334 | PORT axi_aclk = clk_160MHz
|
---|
| 335 | PORT sysgen_clk = clk_160MHz
|
---|
| 336 | PORT agc_run = phy_rx_pkt_det
|
---|
[2405] | 337 | PORT agc_done = agc_done
|
---|
| 338 | # IQ Inputs from radio
|
---|
[5090] | 339 | PORT adc_iq_valid = RF_AD_samp_ce
|
---|
[4853] | 340 | PORT rfa_rssi = RFA_RSSI_D_REG
|
---|
[2086] | 341 | PORT rfa_rx_i_in = RFA_RX_I
|
---|
| 342 | PORT rfa_rx_q_in = RFA_RX_Q
|
---|
[4853] | 343 | PORT rfb_rssi = RFB_RSSI_D_REG
|
---|
[2405] | 344 | PORT rfb_rx_i_in = RFB_RX_I
|
---|
| 345 | PORT rfb_rx_q_in = RFB_RX_Q
|
---|
[2086] | 346 | # DCO-corrected IQ outputs
|
---|
[2797] | 347 | PORT iq_valid_out = agc_iq_valid_out
|
---|
[2086] | 348 | PORT rfa_rx_i_out = agc_rfa_i
|
---|
| 349 | PORT rfa_rx_q_out = agc_rfa_q
|
---|
[2405] | 350 | PORT rfb_rx_i_out = agc_rfb_i
|
---|
| 351 | PORT rfb_rx_q_out = agc_rfb_q
|
---|
[2086] | 352 | # Gain outputs
|
---|
[2797] | 353 | PORT rfa_agc_g_bb = agc_rfa_g_bb
|
---|
[2086] | 354 | PORT rfa_agc_g_rf = agc_rfa_g_rf
|
---|
| 355 | PORT rfa_agc_rxhp = agc_rfa_rxhp
|
---|
[2797] | 356 | PORT rfb_agc_g_bb = agc_rfb_g_bb
|
---|
[2405] | 357 | PORT rfb_agc_g_rf = agc_rfb_g_rf
|
---|
| 358 | PORT rfb_agc_rxhp = agc_rfb_rxhp
|
---|
[2086] | 359 | END
|
---|
| 360 |
|
---|
[4733] | 361 | # ##############################################################################
|
---|
| 362 | # Radio Control Logic
|
---|
| 363 | # ##############################################################################
|
---|
[2086] | 364 | BEGIN w3_clock_controller_axi
|
---|
[5490] | 365 | PARAMETER INSTANCE = w3_clock_controller
|
---|
[4705] | 366 | PARAMETER HW_VER = 4.00.a
|
---|
[2086] | 367 | PARAMETER C_DPHASE_TIMEOUT = 0
|
---|
[4733] | 368 | PARAMETER C_BASEADDR = 0x22100000
|
---|
| 369 | PARAMETER C_HIGHADDR = 0x2210FFFF
|
---|
[2254] | 370 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 371 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 372 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 373 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 374 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[2086] | 375 | BUS_INTERFACE S_AXI = mb_low_axi_periph
|
---|
| 376 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 377 | PORT samp_spi_cs_n = clk_samp_spi_cs_n
|
---|
| 378 | PORT samp_spi_mosi = clk_samp_spi_mosi
|
---|
[4705] | 379 | PORT samp_spi_miso = clk_samp_spi_miso
|
---|
| 380 | PORT samp_spi_sclk = clk_samp_spi_sclk
|
---|
| 381 | PORT samp_func = samp_func
|
---|
| 382 | PORT rfref_spi_cs_n = clk_rfref_spi_cs_n
|
---|
[2086] | 383 | PORT rfref_spi_mosi = clk_rfref_spi_mosi
|
---|
[4705] | 384 | PORT rfref_spi_miso = clk_rfref_spi_miso
|
---|
[2086] | 385 | PORT rfref_spi_sclk = clk_rfref_spi_sclk
|
---|
[4705] | 386 | PORT rfref_func = rfref_func
|
---|
| 387 | PORT cm_spi_cs_n = cm_spi_cs_n
|
---|
| 388 | PORT cm_spi_mosi = cm_spi_mosi
|
---|
| 389 | PORT cm_spi_miso = cm_spi_miso
|
---|
| 390 | PORT cm_spi_sclk = cm_spi_sclk
|
---|
| 391 | PORT cm_pll_status = cm_pll_status
|
---|
| 392 | PORT pll_refclk = pll_refclk
|
---|
[2086] | 393 | PORT usr_status = net_gnd
|
---|
| 394 | PORT at_boot_clk_in = clk_200MHz
|
---|
| 395 | PORT at_boot_clk_in_valid = clk_gen_async_clks_locked
|
---|
[4705] | 396 | PORT at_boot_config_sw = cm_switch
|
---|
[2086] | 397 | PORT at_boot_clkbuf_clocks_invalid = mmcm_inputs_invalid
|
---|
[4705] | 398 | # Communication ports
|
---|
| 399 | PORT uart_tx = clk_cfg_uart_tx
|
---|
| 400 | PORT iic_eeprom_scl_I = clk_cfg_iic_eeprom_scl_I
|
---|
| 401 | PORT iic_eeprom_scl_T = clk_cfg_iic_eeprom_scl_T
|
---|
| 402 | PORT iic_eeprom_scl_O = clk_cfg_iic_eeprom_scl_O
|
---|
| 403 | PORT iic_eeprom_sda_I = clk_cfg_iic_eeprom_sda_I
|
---|
| 404 | PORT iic_eeprom_sda_T = clk_cfg_iic_eeprom_sda_T
|
---|
| 405 | PORT iic_eeprom_sda_O = clk_cfg_iic_eeprom_sda_O
|
---|
[2086] | 406 | END
|
---|
| 407 |
|
---|
| 408 | BEGIN w3_ad_controller_axi
|
---|
[5490] | 409 | PARAMETER INSTANCE = w3_ad_controller
|
---|
[3394] | 410 | PARAMETER HW_VER = 3.02.a
|
---|
[4733] | 411 | PARAMETER C_BASEADDR = 0x22200000
|
---|
| 412 | PARAMETER C_HIGHADDR = 0x2220FFFF
|
---|
[2254] | 413 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 414 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 415 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 416 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 417 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[3394] | 418 | PARAMETER INCLUDE_RFC_RFD_IO = 0
|
---|
[2086] | 419 | BUS_INTERFACE S_AXI = mb_low_axi_periph
|
---|
| 420 | PORT S_AXI_ACLK = clk_160MHz
|
---|
[3758] | 421 | PORT RF_AD_TXCLK_out_en = RF_AD_TXCLK_out_en
|
---|
[2086] | 422 | PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n
|
---|
| 423 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio
|
---|
| 424 | PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk
|
---|
| 425 | PORT RFA_AD_reset_n = RFA_AD_reset_n
|
---|
[3758] | 426 | PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n
|
---|
| 427 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio
|
---|
[2086] | 428 | PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk
|
---|
[3758] | 429 | PORT RFB_AD_reset_n = RFB_AD_reset_n
|
---|
[2086] | 430 | END
|
---|
| 431 |
|
---|
| 432 | BEGIN w3_ad_bridge
|
---|
[2405] | 433 | PARAMETER INSTANCE = ad_bridge_onBoard
|
---|
[5856] | 434 | PARAMETER HW_VER = 3.03.b
|
---|
[2086] | 435 | # Clock ports (inputs to w3_ad_bridge)
|
---|
[5090] | 436 | PORT sys_clk = clk_160MHz
|
---|
| 437 | PORT samp_ce = RF_AD_samp_ce
|
---|
[3394] | 438 | PORT ad_TXCLK_out_en = RF_AD_TXCLK_out_en
|
---|
[2086] | 439 | # Top-level AD9963 ports
|
---|
| 440 | PORT ad_RFA_TXD = rfa_txd
|
---|
| 441 | PORT ad_RFA_TXCLK = rfa_txclk
|
---|
| 442 | PORT ad_RFA_TXIQ = rfa_txiq
|
---|
| 443 | PORT ad_RFA_TRXD = rfa_trxd
|
---|
| 444 | PORT ad_RFA_TRXCLK = rfa_trxclk
|
---|
| 445 | PORT ad_RFA_TRXIQ = rfa_trxiq
|
---|
| 446 | PORT ad_RFB_TXD = rfb_txd
|
---|
| 447 | PORT ad_RFB_TXCLK = rfb_txclk
|
---|
| 448 | PORT ad_RFB_TXIQ = rfb_txiq
|
---|
| 449 | PORT ad_RFB_TRXD = rfb_trxd
|
---|
| 450 | PORT ad_RFB_TRXCLK = rfb_trxclk
|
---|
| 451 | PORT ad_RFB_TRXIQ = rfb_trxiq
|
---|
| 452 | PORT user_RFA_TXD_I = RFA_TX_I
|
---|
| 453 | PORT user_RFA_TXD_Q = RFA_TX_Q
|
---|
| 454 | PORT user_RFA_RXD_I = RFA_RX_I
|
---|
| 455 | PORT user_RFA_RXD_Q = RFA_RX_Q
|
---|
[2405] | 456 | PORT user_RFB_TXD_I = RFB_TX_I
|
---|
| 457 | PORT user_RFB_TXD_Q = RFB_TX_Q
|
---|
[2086] | 458 | PORT user_RFB_RXD_I = RFB_RX_I
|
---|
| 459 | PORT user_RFB_RXD_Q = RFB_RX_Q
|
---|
| 460 | END
|
---|
| 461 |
|
---|
| 462 | BEGIN radio_controller_axi
|
---|
[5490] | 463 | PARAMETER INSTANCE = radio_controller
|
---|
[3394] | 464 | PARAMETER HW_VER = 3.01.a
|
---|
[4733] | 465 | PARAMETER C_BASEADDR = 0x22300000
|
---|
| 466 | PARAMETER C_HIGHADDR = 0x2230FFFF
|
---|
[2254] | 467 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 468 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 469 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 470 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 471 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[2086] | 472 | BUS_INTERFACE S_AXI = mb_low_axi_periph
|
---|
| 473 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 474 | PORT RFA_TxEn = RFA_TxEn
|
---|
| 475 | PORT RFA_RxEn = RFA_RxEn
|
---|
| 476 | PORT RFA_RxHP = RFA_RxHP
|
---|
| 477 | PORT RFA_SHDN = RFA_SHDN
|
---|
| 478 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK
|
---|
| 479 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI
|
---|
| 480 | PORT RFA_SPI_CSn = RFA_SPI_CSn
|
---|
| 481 | PORT RFA_B = RFA_B
|
---|
| 482 | PORT RFA_LD = RFA_LD
|
---|
| 483 | PORT RFA_PAEn_24 = RFA_PAEn_24
|
---|
| 484 | PORT RFA_PAEn_5 = RFA_PAEn_5
|
---|
| 485 | PORT RFA_AntSw = RFA_AntSw
|
---|
| 486 | PORT RFB_TxEn = RFB_TxEn
|
---|
| 487 | PORT RFB_RxEn = RFB_RxEn
|
---|
| 488 | PORT RFB_RxHP = RFB_RxHP
|
---|
| 489 | PORT RFB_SHDN = RFB_SHDN
|
---|
| 490 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK
|
---|
| 491 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI
|
---|
| 492 | PORT RFB_SPI_CSn = RFB_SPI_CSn
|
---|
| 493 | PORT RFB_B = RFB_B
|
---|
| 494 | PORT RFB_LD = RFB_LD
|
---|
| 495 | PORT RFB_PAEn_24 = RFB_PAEn_24
|
---|
| 496 | PORT RFB_PAEn_5 = RFB_PAEn_5
|
---|
| 497 | PORT RFB_AntSw = RFB_AntSw
|
---|
| 498 | PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
|
---|
| 499 | PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
|
---|
| 500 | PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
|
---|
| 501 | PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
|
---|
| 502 | # Inter-core ports for hardware radio control
|
---|
[2405] | 503 | PORT usr_any_PHYStart = tx_phy_start
|
---|
[3596] | 504 | PORT usr_RFA_TxEn = phy_rc_txen_a
|
---|
[2405] | 505 | PORT usr_RFA_RxEn = rc_usr_rxen
|
---|
[2086] | 506 | PORT usr_RFA_RxHP = agc_rfa_rxhp
|
---|
| 507 | PORT usr_RFA_RxGainBB = agc_rfa_g_bb
|
---|
| 508 | PORT usr_RFA_RxGainRF = agc_rfa_g_rf
|
---|
[3602] | 509 | PORT usr_RFA_TxGain = phy_rc_tx_gain_a
|
---|
[3596] | 510 | PORT usr_RFB_TxEn = phy_rc_txen_b
|
---|
[2405] | 511 | PORT usr_RFB_RxEn = rc_usr_rxen
|
---|
| 512 | PORT usr_RFB_RxHP = agc_rfb_rxhp
|
---|
| 513 | PORT usr_RFB_RxGainBB = agc_rfb_g_bb
|
---|
| 514 | PORT usr_RFB_RxGainRF = agc_rfb_g_rf
|
---|
[3602] | 515 | PORT usr_RFB_TxGain = phy_rc_tx_gain_b
|
---|
[2086] | 516 | END
|
---|
| 517 |
|
---|
[4733] | 518 | # ##############################################################################
|
---|
| 519 | # Clocks and Reset
|
---|
| 520 | # ##############################################################################
|
---|
| 521 | BEGIN proc_sys_reset
|
---|
| 522 | PARAMETER INSTANCE = sys_reset
|
---|
| 523 | PARAMETER HW_VER = 3.00.a
|
---|
| 524 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 525 | PORT MB_Debug_Sys_Rst = sys_reset_debug_rst
|
---|
| 526 | PORT Dcm_locked = clk_gen_all_locked
|
---|
| 527 | PORT MB_Reset = sys_reset_MB_Reset
|
---|
[5090] | 528 | PORT Slowest_sync_clk = clk_80MHz
|
---|
[4733] | 529 | PORT Interconnect_aresetn = sys_reset_Interconnect_aresetn
|
---|
| 530 | PORT Ext_Reset_In = reset_pb
|
---|
| 531 | PORT BUS_STRUCT_RESET = sys_reset_BUS_STRUCT_RESET
|
---|
| 532 | END
|
---|
| 533 |
|
---|
| 534 | BEGIN clock_generator
|
---|
[5490] | 535 | PARAMETER INSTANCE = clock_generator_dram_clocks
|
---|
[4733] | 536 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 537 | PARAMETER HW_VER = 4.03.a
|
---|
| 538 | # 80MHz clock input (driven by other clock generator)
|
---|
| 539 | PARAMETER C_CLKIN_FREQ = 80000000
|
---|
[5490] | 540 | # MIG DRAM clock (2x bus)
|
---|
[4733] | 541 | PARAMETER C_CLKOUT0_FREQ = 320000000
|
---|
| 542 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
| 543 | PARAMETER C_CLKOUT0_GROUP = MMCM0
|
---|
| 544 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
[5490] | 545 | # MIG DRAM clock (2x bus, variable phase)
|
---|
[4733] | 546 | PARAMETER C_CLKOUT1_FREQ = 320000000
|
---|
| 547 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
| 548 | PARAMETER C_CLKOUT1_GROUP = MMCM0
|
---|
| 549 | PARAMETER C_CLKOUT1_BUF = FALSE
|
---|
| 550 | PARAMETER C_CLKOUT1_VARIABLE_PHASE = TRUE
|
---|
| 551 | PARAMETER C_PSDONE_GROUP = MMCM0
|
---|
| 552 | PORT CLKIN = clk_80MHz
|
---|
| 553 | PORT PSCLK = clk_80MHz
|
---|
| 554 | PORT RST = mmcm_inputs_invalid
|
---|
[5490] | 555 | PORT LOCKED = clk_gen_dram_clks_locked
|
---|
| 556 | PORT CLKOUT0 = clk_dram_320MHz_clk_mem
|
---|
| 557 | PORT CLKOUT1 = clk_dram_320MHz_clk_rd_base
|
---|
[4733] | 558 | PORT PSEN = MMCM_PSEN
|
---|
| 559 | PORT PSINCDEC = MMCM_PSINCDEC
|
---|
| 560 | PORT PSDONE = MMCM_PSDONE
|
---|
| 561 | END
|
---|
| 562 |
|
---|
| 563 | BEGIN clock_generator
|
---|
| 564 | PARAMETER INSTANCE = clk_gen_proc_bus_clks
|
---|
| 565 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 566 | PARAMETER HW_VER = 4.03.a
|
---|
| 567 | # 80MHz clock input (driven by AD9512 for sampling clock)
|
---|
| 568 | PARAMETER C_CLKIN_FREQ = 80000000
|
---|
| 569 | # MB and primary bus
|
---|
| 570 | PARAMETER C_CLKOUT0_FREQ = 80000000
|
---|
| 571 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
| 572 | PARAMETER C_CLKOUT0_GROUP = MMCM0
|
---|
| 573 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
| 574 | # MB and primary bus
|
---|
| 575 | PARAMETER C_CLKOUT1_FREQ = 160000000
|
---|
| 576 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
| 577 | PARAMETER C_CLKOUT1_GROUP = MMCM0
|
---|
| 578 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
| 579 | PORT CLKIN = ad_refclk_in
|
---|
| 580 | PORT CLKOUT0 = clk_80MHz
|
---|
| 581 | PORT CLKOUT1 = clk_160MHz
|
---|
| 582 | PORT RST = mmcm_inputs_invalid
|
---|
| 583 | PORT LOCKED = clk_gen_proc_bus_clks_locked
|
---|
| 584 | END
|
---|
| 585 |
|
---|
| 586 | BEGIN clock_generator
|
---|
| 587 | PARAMETER INSTANCE = clk_gen_async_clks
|
---|
| 588 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 589 | PARAMETER HW_VER = 4.03.a
|
---|
| 590 | # 200MHz clock input (driven by 200MHz LVDS oscillator)
|
---|
| 591 | PARAMETER C_CLKIN_FREQ = 200000000
|
---|
| 592 | # TEMAC TxClk
|
---|
| 593 | PARAMETER C_CLKOUT0_FREQ = 125000000
|
---|
| 594 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
| 595 | PARAMETER C_CLKOUT0_GROUP = NONE
|
---|
| 596 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
| 597 | # IDELAYCTRL refclk
|
---|
| 598 | PARAMETER C_CLKOUT1_FREQ = 200000000
|
---|
| 599 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
| 600 | PARAMETER C_CLKOUT1_GROUP = NONE
|
---|
| 601 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
| 602 | PORT CLKIN = osc200_in
|
---|
| 603 | PORT CLKOUT0 = clk_125MHz
|
---|
| 604 | PORT CLKOUT1 = clk_200MHz
|
---|
| 605 | PORT RST = reset_pb
|
---|
| 606 | PORT LOCKED = clk_gen_async_clks_locked
|
---|
| 607 | END
|
---|
| 608 |
|
---|
| 609 | # ##############################################################################
|
---|
| 610 | # Shared Cores
|
---|
| 611 | # ##############################################################################
|
---|
| 612 | BEGIN axi_interconnect
|
---|
| 613 | PARAMETER INSTANCE = mb_shared_axi
|
---|
| 614 | PARAMETER HW_VER = 1.06.a
|
---|
| 615 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 616 | PORT INTERCONNECT_ARESETN = sys_reset_Interconnect_aresetn
|
---|
| 617 | END
|
---|
| 618 |
|
---|
| 619 | BEGIN mailbox
|
---|
| 620 | PARAMETER INSTANCE = mb_mailbox
|
---|
| 621 | PARAMETER HW_VER = 1.01.b
|
---|
| 622 | PARAMETER C_INTERCONNECT_PORT_0 = 2
|
---|
| 623 | PARAMETER C_INTERCONNECT_PORT_1 = 2
|
---|
| 624 | PARAMETER C_IMPL_STYLE = 1
|
---|
[5010] | 625 | PARAMETER C_MAILBOX_DEPTH = 512
|
---|
[4733] | 626 | PARAMETER C_S0_AXI_BASEADDR = 0x30000000
|
---|
| 627 | PARAMETER C_S0_AXI_HIGHADDR = 0x3000FFFF
|
---|
| 628 | PARAMETER C_S1_AXI_BASEADDR = 0x30000000
|
---|
| 629 | PARAMETER C_S1_AXI_HIGHADDR = 0x3000FFFF
|
---|
| 630 | PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 8
|
---|
| 631 | PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 8
|
---|
| 632 | PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 8
|
---|
| 633 | PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 8
|
---|
| 634 | PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 8
|
---|
| 635 | PARAMETER C_INTERCONNECT_S1_AXI_AW_REGISTER = 7
|
---|
| 636 | PARAMETER C_INTERCONNECT_S1_AXI_AR_REGISTER = 7
|
---|
| 637 | PARAMETER C_INTERCONNECT_S1_AXI_W_REGISTER = 7
|
---|
| 638 | PARAMETER C_INTERCONNECT_S1_AXI_R_REGISTER = 7
|
---|
| 639 | PARAMETER C_INTERCONNECT_S1_AXI_B_REGISTER = 7
|
---|
| 640 | BUS_INTERFACE S0_AXI = mb_high_axi_periph
|
---|
| 641 | BUS_INTERFACE S1_AXI = mb_low_axi_periph
|
---|
| 642 | PORT S0_AXI_ACLK = clk_160MHz
|
---|
| 643 | PORT S1_AXI_ACLK = clk_160MHz
|
---|
| 644 | PORT Interrupt_0 = mb_mailbox_Interrupt_0
|
---|
| 645 | END
|
---|
| 646 |
|
---|
[2086] | 647 | BEGIN mutex
|
---|
| 648 | PARAMETER INSTANCE = pkt_buffer_mutex
|
---|
| 649 | PARAMETER HW_VER = 1.00.a
|
---|
| 650 | PARAMETER C_NUM_PLB = 0
|
---|
| 651 | PARAMETER C_NUM_AXI = 2
|
---|
| 652 | PARAMETER C_NUM_MUTEX = 32
|
---|
| 653 | PARAMETER C_ENABLE_USER = 1
|
---|
| 654 | PARAMETER C_ENABLE_HW_PROT = 1
|
---|
| 655 | PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 8
|
---|
| 656 | PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 8
|
---|
| 657 | PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 8
|
---|
| 658 | PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 8
|
---|
| 659 | PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 8
|
---|
[4733] | 660 | PARAMETER C_S0_AXI_BASEADDR = 0x31000000
|
---|
| 661 | PARAMETER C_S0_AXI_HIGHADDR = 0x3100FFFF
|
---|
| 662 | PARAMETER C_S1_AXI_BASEADDR = 0x31000000
|
---|
| 663 | PARAMETER C_S1_AXI_HIGHADDR = 0x3100FFFF
|
---|
[2254] | 664 | PARAMETER C_INTERCONNECT_S1_AXI_AW_REGISTER = 7
|
---|
| 665 | PARAMETER C_INTERCONNECT_S1_AXI_AR_REGISTER = 7
|
---|
| 666 | PARAMETER C_INTERCONNECT_S1_AXI_W_REGISTER = 7
|
---|
| 667 | PARAMETER C_INTERCONNECT_S1_AXI_R_REGISTER = 7
|
---|
| 668 | PARAMETER C_INTERCONNECT_S1_AXI_B_REGISTER = 7
|
---|
[2086] | 669 | BUS_INTERFACE S0_AXI = mb_high_axi_periph
|
---|
| 670 | BUS_INTERFACE S1_AXI = mb_low_axi_periph
|
---|
| 671 | PORT S0_AXI_ACLK = clk_160MHz
|
---|
| 672 | PORT S1_AXI_ACLK = clk_160MHz
|
---|
| 673 | END
|
---|
| 674 |
|
---|
| 675 | BEGIN axi_bram_ctrl
|
---|
| 676 | PARAMETER INSTANCE = pkt_buff_TX_bram_ctrl
|
---|
| 677 | PARAMETER HW_VER = 1.03.a
|
---|
| 678 | PARAMETER C_SINGLE_PORT_BRAM = 1
|
---|
| 679 | PARAMETER C_S_AXI_DATA_WIDTH = 64
|
---|
[2405] | 680 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 681 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
[2086] | 682 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 683 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
[2405] | 684 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[5743] | 685 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = mb_high.M_AXI_DC & mb_low.M_AXI_DC & axi_cdma_0.M_AXI
|
---|
[4733] | 686 | PARAMETER C_S_AXI_BASEADDR = 0x91000000
|
---|
[5743] | 687 | PARAMETER C_S_AXI_HIGHADDR = 0x9100FFFF
|
---|
[2086] | 688 | BUS_INTERFACE BRAM_PORTA = PKT_BUFF_TX_CTRL_PORTA
|
---|
| 689 | BUS_INTERFACE S_AXI = mb_shared_axi
|
---|
| 690 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 691 | END
|
---|
| 692 |
|
---|
[4733] | 693 | BEGIN bram_block
|
---|
| 694 | PARAMETER INSTANCE = pkt_buffer_TX_bram
|
---|
| 695 | PARAMETER HW_VER = 1.00.a
|
---|
| 696 | BUS_INTERFACE PORTA = PKT_BUFF_TX_CTRL_PORTA
|
---|
| 697 | BUS_INTERFACE PORTB = WLAN_TX_PKT_BUF_PORTB
|
---|
| 698 | PORT BRAM_Clk_B = clk_160MHz
|
---|
| 699 | END
|
---|
| 700 |
|
---|
[2086] | 701 | BEGIN axi_bram_ctrl
|
---|
| 702 | PARAMETER INSTANCE = pkt_buff_RX_bram_ctrl
|
---|
| 703 | PARAMETER HW_VER = 1.03.a
|
---|
| 704 | PARAMETER C_SINGLE_PORT_BRAM = 1
|
---|
| 705 | PARAMETER C_S_AXI_DATA_WIDTH = 64
|
---|
[2405] | 706 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 707 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
[2086] | 708 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 709 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
[2405] | 710 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[5743] | 711 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = mb_low.M_AXI_DC & mb_high.M_AXI_DC & axi_cdma_0.M_AXI & axi2axi_eth_a_dma.M_AXI
|
---|
[4733] | 712 | PARAMETER C_S_AXI_BASEADDR = 0x90000000
|
---|
| 713 | PARAMETER C_S_AXI_HIGHADDR = 0x90007FFF
|
---|
[2086] | 714 | BUS_INTERFACE BRAM_PORTA = PKT_BUFF_RX_CTRL_PORTA
|
---|
| 715 | BUS_INTERFACE S_AXI = mb_shared_axi
|
---|
| 716 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 717 | END
|
---|
| 718 |
|
---|
[2405] | 719 | BEGIN bram_block
|
---|
[4733] | 720 | PARAMETER INSTANCE = pkt_buffer_RX_bram
|
---|
[2405] | 721 | PARAMETER HW_VER = 1.00.a
|
---|
[4733] | 722 | BUS_INTERFACE PORTA = PKT_BUFF_RX_CTRL_PORTA
|
---|
| 723 | BUS_INTERFACE PORTB = WLAN_RX_PKT_BUF_PORTB
|
---|
| 724 | PORT BRAM_Clk_B = clk_160MHz
|
---|
[2405] | 725 | END
|
---|
| 726 |
|
---|
[5090] | 727 | BEGIN axi_interconnect
|
---|
| 728 | PARAMETER INSTANCE = mb_shared_axi_periph
|
---|
| 729 | PARAMETER HW_VER = 1.06.a
|
---|
| 730 | PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
|
---|
| 731 | PORT INTERCONNECT_ARESETN = sys_reset_Interconnect_aresetn
|
---|
| 732 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 733 | END
|
---|
| 734 |
|
---|
| 735 | BEGIN axi2axi_connector
|
---|
[5490] | 736 | PARAMETER INSTANCE = axi2axi_connector_shared_periphs
|
---|
[5090] | 737 | PARAMETER HW_VER = 1.00.a
|
---|
| 738 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = mb_low.M_AXI_DC & mb_high.M_AXI_DC
|
---|
| 739 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0x80000000
|
---|
| 740 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x8FFFFFFF
|
---|
| 741 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 742 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 743 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 744 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 745 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
| 746 | BUS_INTERFACE S_AXI = mb_shared_axi
|
---|
| 747 | BUS_INTERFACE M_AXI = mb_shared_axi_periph
|
---|
| 748 | END
|
---|
| 749 |
|
---|
[4733] | 750 | BEGIN w3_userio_axi
|
---|
[4853] | 751 | PARAMETER INSTANCE = w3_userio
|
---|
[5594] | 752 | PARAMETER HW_VER = 1.03.a
|
---|
[4733] | 753 | PARAMETER INCLUDE_DNA_READ_LOGIC = 0
|
---|
| 754 | PARAMETER C_BASEADDR = 0x80000000
|
---|
| 755 | PARAMETER C_HIGHADDR = 0x80000FFF
|
---|
[2254] | 756 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 757 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 758 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 759 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 760 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[5090] | 761 | BUS_INTERFACE S_AXI = mb_shared_axi_periph
|
---|
[2086] | 762 | PORT S_AXI_ACLK = clk_160MHz
|
---|
[4733] | 763 | PORT leds_red = userio_leds_red
|
---|
| 764 | PORT leds_green = userio_leds_green
|
---|
| 765 | PORT hexdisp_left = userio_hexdisp_left
|
---|
| 766 | PORT hexdisp_right = userio_hexdisp_right
|
---|
| 767 | PORT hexdisp_left_dp = userio_hexdisp_left_dp
|
---|
| 768 | PORT hexdisp_right_dp = userio_hexdisp_right_dp
|
---|
| 769 | PORT rfa_led_red = userio_rfa_led_red
|
---|
| 770 | PORT rfa_led_green = userio_rfa_led_green
|
---|
| 771 | PORT rfb_led_red = userio_rfb_led_red
|
---|
| 772 | PORT rfb_led_green = userio_rfb_led_green
|
---|
| 773 | PORT dipsw = userio_dipsw_b0 & userio_dipsw_b1 & userio_dipsw_b2 & userio_dipsw_b3
|
---|
| 774 | PORT pb_u = userio_pb_u
|
---|
| 775 | PORT pb_m = userio_pb_m
|
---|
| 776 | PORT pb_d = userio_pb_d
|
---|
| 777 | PORT usr_rfa_led_red = RFA_statLED_Rx
|
---|
| 778 | PORT usr_rfa_led_green = RFA_statLED_Tx
|
---|
| 779 | PORT usr_rfb_led_red = RFB_statLED_Rx
|
---|
| 780 | PORT usr_rfb_led_green = RFB_statLED_Tx
|
---|
| 781 | PORT usr_leds_red = dbg_signal_err_disp
|
---|
[5743] | 782 | PORT usr_dbg_hdr_out = dbg_mac_tx_d_pending & dbg_mac_tx_c_pending & dbg_mac_backoff_c_active & dbg_mac_tx_b_pending & dbg_mac_nav_active & dbg_mac_backoff_a_active & dbg_mac_idle_for_difs & dbg_mac_tx_a_pending & dbg_rssi_det & mac_phy_rx_fcs_good_ind & dbg_lts_timeout & dbg_pkt_det_dsss & dbg_pkt_det_ofdm & dbg_dsss_rx_active & dbg_ofdm_rx_active & dbg_tx_running
|
---|
[5594] | 783 | PORT dbg_hdr = dbg_hdr
|
---|
[2086] | 784 | END
|
---|
| 785 |
|
---|
[4733] | 786 | BEGIN wlan_mac_time_hw_axiw
|
---|
| 787 | PARAMETER INSTANCE = wlan_mac_time_hw
|
---|
[5010] | 788 | PARAMETER HW_VER = 1.00.d
|
---|
[5090] | 789 | PARAMETER C_BASEADDR = 0x81000000
|
---|
| 790 | PARAMETER C_HIGHADDR = 0x81000FFF
|
---|
[2254] | 791 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 792 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 793 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 794 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 795 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[5090] | 796 | BUS_INTERFACE S_AXI = mb_shared_axi_periph
|
---|
[4733] | 797 | PORT axi_aclk = clk_160MHz
|
---|
| 798 | PORT sysgen_clk = clk_160MHz
|
---|
| 799 | PORT mac_time_lsb = mac_time_usec_lsb
|
---|
| 800 | PORT mac_time_msb = mac_time_usec_msb
|
---|
[5010] | 801 | PORT time_usec_frac = mac_time_usec_frac
|
---|
[2086] | 802 | END
|
---|
| 803 |
|
---|
[5090] | 804 | BEGIN w3_iic_eeprom_axi
|
---|
| 805 | PARAMETER INSTANCE = w3_iic_eeprom_onBoard
|
---|
| 806 | PARAMETER HW_VER = 1.02.a
|
---|
| 807 | PARAMETER C_BASEADDR = 0x82000000
|
---|
| 808 | PARAMETER C_HIGHADDR = 0x8200FFFF
|
---|
| 809 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 810 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 811 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 812 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 813 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
| 814 | BUS_INTERFACE S_AXI = mb_shared_axi_periph
|
---|
| 815 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 816 | PORT iic_scl_I = axi_iic_eeprom_scl_I
|
---|
| 817 | PORT iic_scl_O = axi_iic_eeprom_scl_O
|
---|
| 818 | PORT iic_scl_T = axi_iic_eeprom_scl_T
|
---|
| 819 | PORT iic_sda_I = axi_iic_eeprom_sda_I
|
---|
| 820 | PORT iic_sda_O = axi_iic_eeprom_sda_O
|
---|
| 821 | PORT iic_sda_T = axi_iic_eeprom_sda_T
|
---|
| 822 | END
|
---|
| 823 |
|
---|
| 824 | BEGIN axi_sysmon_adc
|
---|
[5490] | 825 | PARAMETER INSTANCE = axi_sysmon
|
---|
[5090] | 826 | PARAMETER HW_VER = 2.00.a
|
---|
| 827 | PARAMETER C_INCLUDE_INTR = 1
|
---|
| 828 | PARAMETER C_BASEADDR = 0x83000000
|
---|
| 829 | PARAMETER C_HIGHADDR = 0x83000FFF
|
---|
| 830 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 831 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 832 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 833 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 834 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
| 835 | BUS_INTERFACE S_AXI = mb_shared_axi_periph
|
---|
| 836 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 837 | PORT VAUXP = net_gnd
|
---|
| 838 | PORT VAUXN = net_gnd
|
---|
| 839 | PORT CONVST = net_gnd
|
---|
| 840 | END
|
---|
| 841 |
|
---|
[4733] | 842 | # ##############################################################################
|
---|
| 843 | # Microblaze Low
|
---|
| 844 | # ##############################################################################
|
---|
| 845 | BEGIN microblaze
|
---|
| 846 | PARAMETER INSTANCE = mb_low
|
---|
| 847 | PARAMETER HW_VER = 8.40.b
|
---|
| 848 | PARAMETER C_INTERCONNECT = 2
|
---|
| 849 | PARAMETER C_DEBUG_ENABLED = 1
|
---|
| 850 | PARAMETER C_USE_DCACHE = 1
|
---|
| 851 | PARAMETER C_USE_ICACHE = 0
|
---|
| 852 | # Little endian
|
---|
| 853 | PARAMETER C_ENDIANNESS = 1
|
---|
| 854 | # MMU Settings
|
---|
| 855 | PARAMETER C_USE_MMU = 0
|
---|
| 856 | PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1
|
---|
| 857 | PARAMETER C_ILL_OPCODE_EXCEPTION = 1
|
---|
| 858 | PARAMETER C_UNALIGNED_EXCEPTIONS = 1
|
---|
| 859 | PARAMETER C_OPCODE_0x0_ILLEGAL = 1
|
---|
| 860 | PARAMETER C_USE_BARREL = 1
|
---|
| 861 | PARAMETER C_PVR = 2
|
---|
| 862 | PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 7
|
---|
| 863 | PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 7
|
---|
| 864 | PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1
|
---|
| 865 | PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1
|
---|
| 866 | PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 7
|
---|
| 867 | PARAMETER C_NUMBER_OF_PC_BRK = 4
|
---|
| 868 | PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2
|
---|
| 869 | PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2
|
---|
| 870 | PARAMETER C_CACHE_BYTE_SIZE = 64
|
---|
| 871 | PARAMETER C_DCACHE_BYTE_SIZE = 64
|
---|
| 872 | PARAMETER C_DCACHE_BASEADDR = 0x80000000
|
---|
| 873 | PARAMETER C_DCACHE_HIGHADDR = 0xffffffff
|
---|
| 874 | PARAMETER C_DCACHE_ALWAYS_USED = 1
|
---|
| 875 | PARAMETER C_USE_STACK_PROTECTION = 1
|
---|
| 876 | PARAMETER C_USE_DIV = 1
|
---|
| 877 | BUS_INTERFACE M_AXI_DC = mb_shared_axi
|
---|
| 878 | BUS_INTERFACE M_AXI_DP = mb_low_axi_periph
|
---|
| 879 | BUS_INTERFACE DEBUG = mb_low_debug
|
---|
| 880 | BUS_INTERFACE DLMB = mb_low_dlmb
|
---|
| 881 | BUS_INTERFACE ILMB = mb_low_ilmb
|
---|
| 882 | PORT MB_RESET = sys_reset_MB_Reset
|
---|
| 883 | PORT CLK = clk_160MHz
|
---|
| 884 | PORT INTERRUPT = net_gnd
|
---|
| 885 | END
|
---|
| 886 |
|
---|
[2086] | 887 | BEGIN bram_block
|
---|
| 888 | PARAMETER INSTANCE = mb_low_lmb_bram
|
---|
| 889 | PARAMETER HW_VER = 1.00.a
|
---|
| 890 | BUS_INTERFACE PORTA = mb_low_ilmb_bram_PORT
|
---|
| 891 | BUS_INTERFACE PORTB = mb_low_dlmb_bram_PORT
|
---|
| 892 | END
|
---|
| 893 |
|
---|
| 894 | BEGIN lmb_bram_if_cntlr
|
---|
| 895 | PARAMETER INSTANCE = mb_low_ilmb_bram_cntlr
|
---|
| 896 | PARAMETER HW_VER = 3.10.c
|
---|
| 897 | PARAMETER C_BASEADDR = 0x00000000
|
---|
[5856] | 898 | PARAMETER C_HIGHADDR = 0x0001ffff
|
---|
[2086] | 899 | BUS_INTERFACE BRAM_PORT = mb_low_ilmb_bram_PORT
|
---|
| 900 | BUS_INTERFACE SLMB = mb_low_ilmb
|
---|
| 901 | END
|
---|
| 902 |
|
---|
| 903 | BEGIN lmb_v10
|
---|
| 904 | PARAMETER INSTANCE = mb_low_ilmb
|
---|
| 905 | PARAMETER HW_VER = 2.00.b
|
---|
| 906 | PORT SYS_RST = sys_reset_BUS_STRUCT_RESET
|
---|
| 907 | PORT LMB_CLK = clk_160MHz
|
---|
| 908 | END
|
---|
| 909 |
|
---|
| 910 | BEGIN lmb_bram_if_cntlr
|
---|
| 911 | PARAMETER INSTANCE = mb_low_dlmb_bram_cntlr
|
---|
| 912 | PARAMETER HW_VER = 3.10.c
|
---|
| 913 | PARAMETER C_BASEADDR = 0x00000000
|
---|
[5856] | 914 | PARAMETER C_HIGHADDR = 0x0001ffff
|
---|
[2086] | 915 | BUS_INTERFACE BRAM_PORT = mb_low_dlmb_bram_PORT
|
---|
| 916 | BUS_INTERFACE SLMB = mb_low_dlmb
|
---|
| 917 | END
|
---|
| 918 |
|
---|
| 919 | BEGIN lmb_v10
|
---|
| 920 | PARAMETER INSTANCE = mb_low_dlmb
|
---|
| 921 | PARAMETER HW_VER = 2.00.b
|
---|
| 922 | PORT SYS_RST = sys_reset_BUS_STRUCT_RESET
|
---|
| 923 | PORT LMB_CLK = clk_160MHz
|
---|
| 924 | END
|
---|
| 925 |
|
---|
[4733] | 926 | # ##############################################################################
|
---|
| 927 | # Microblaze Low Standard Peripherals
|
---|
| 928 | # ##############################################################################
|
---|
[2086] | 929 | BEGIN axi_interconnect
|
---|
| 930 | PARAMETER INSTANCE = mb_low_axi_periph
|
---|
| 931 | PARAMETER HW_VER = 1.06.a
|
---|
| 932 | PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
|
---|
| 933 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 934 | PORT INTERCONNECT_ARESETN = sys_reset_Interconnect_aresetn
|
---|
| 935 | END
|
---|
| 936 |
|
---|
[4733] | 937 | BEGIN axi_uartlite
|
---|
| 938 | PARAMETER INSTANCE = mb_low_uart
|
---|
| 939 | PARAMETER HW_VER = 1.02.a
|
---|
| 940 | PARAMETER C_BAUDRATE = 115200
|
---|
| 941 | PARAMETER C_BASEADDR = 0x20000000
|
---|
| 942 | PARAMETER C_HIGHADDR = 0x2000FFFF
|
---|
| 943 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 944 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 945 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 946 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 947 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
| 948 | BUS_INTERFACE S_AXI = mb_low_axi_periph
|
---|
| 949 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 950 | # RX=input to uartartlite (PC -> FPGA)
|
---|
| 951 | # TX=output from uartlite (FPGA -> PC)
|
---|
| 952 | PORT RX = mb_low_uart_RX
|
---|
| 953 | PORT TX = mb_low_uart_TX
|
---|
| 954 | END
|
---|
| 955 |
|
---|
| 956 | # ##############################################################################
|
---|
| 957 | # Microblaze High
|
---|
| 958 | # ##############################################################################
|
---|
[2086] | 959 | BEGIN microblaze
|
---|
[4733] | 960 | PARAMETER INSTANCE = mb_high
|
---|
[2086] | 961 | PARAMETER HW_VER = 8.40.b
|
---|
| 962 | PARAMETER C_INTERCONNECT = 2
|
---|
| 963 | PARAMETER C_DEBUG_ENABLED = 1
|
---|
| 964 | PARAMETER C_USE_DCACHE = 1
|
---|
| 965 | PARAMETER C_USE_ICACHE = 0
|
---|
| 966 | # Little endian
|
---|
| 967 | PARAMETER C_ENDIANNESS = 1
|
---|
| 968 | # MMU Settings
|
---|
| 969 | PARAMETER C_USE_MMU = 0
|
---|
| 970 | PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1
|
---|
| 971 | PARAMETER C_ILL_OPCODE_EXCEPTION = 1
|
---|
| 972 | PARAMETER C_UNALIGNED_EXCEPTIONS = 1
|
---|
| 973 | PARAMETER C_OPCODE_0x0_ILLEGAL = 1
|
---|
| 974 | PARAMETER C_USE_BARREL = 1
|
---|
| 975 | PARAMETER C_PVR = 2
|
---|
[2405] | 976 | PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 7
|
---|
| 977 | PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 7
|
---|
[2086] | 978 | PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1
|
---|
| 979 | PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1
|
---|
[2405] | 980 | PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 7
|
---|
[2086] | 981 | PARAMETER C_NUMBER_OF_PC_BRK = 4
|
---|
| 982 | PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2
|
---|
| 983 | PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2
|
---|
| 984 | PARAMETER C_CACHE_BYTE_SIZE = 64
|
---|
| 985 | PARAMETER C_DCACHE_BYTE_SIZE = 64
|
---|
| 986 | PARAMETER C_DCACHE_BASEADDR = 0x80000000
|
---|
[2254] | 987 | PARAMETER C_DCACHE_HIGHADDR = 0xffffffff
|
---|
[4733] | 988 | PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 8
|
---|
| 989 | PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 8
|
---|
| 990 | PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 8
|
---|
| 991 | PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 8
|
---|
| 992 | PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 8
|
---|
[2086] | 993 | PARAMETER C_DCACHE_ALWAYS_USED = 1
|
---|
[3394] | 994 | PARAMETER C_USE_STACK_PROTECTION = 1
|
---|
[2086] | 995 | BUS_INTERFACE M_AXI_DC = mb_shared_axi
|
---|
[4733] | 996 | BUS_INTERFACE M_AXI_DP = mb_high_axi_periph
|
---|
| 997 | BUS_INTERFACE DEBUG = mb_high_debug
|
---|
| 998 | BUS_INTERFACE INTERRUPT = mb_high_interrupt
|
---|
| 999 | BUS_INTERFACE DLMB = mb_high_dlmb
|
---|
| 1000 | BUS_INTERFACE ILMB = mb_high_ilmb
|
---|
[2086] | 1001 | PORT MB_RESET = sys_reset_MB_Reset
|
---|
| 1002 | PORT CLK = clk_160MHz
|
---|
| 1003 | END
|
---|
| 1004 |
|
---|
[2405] | 1005 | BEGIN lmb_v10
|
---|
| 1006 | PARAMETER INSTANCE = mb_high_dlmb
|
---|
| 1007 | PARAMETER HW_VER = 2.00.b
|
---|
| 1008 | PORT SYS_RST = sys_reset_BUS_STRUCT_RESET
|
---|
| 1009 | PORT LMB_CLK = clk_160MHz
|
---|
[2086] | 1010 | END
|
---|
| 1011 |
|
---|
| 1012 | BEGIN lmb_v10
|
---|
[2405] | 1013 | PARAMETER INSTANCE = mb_high_ilmb
|
---|
[2086] | 1014 | PARAMETER HW_VER = 2.00.b
|
---|
| 1015 | PORT SYS_RST = sys_reset_BUS_STRUCT_RESET
|
---|
| 1016 | PORT LMB_CLK = clk_160MHz
|
---|
| 1017 | END
|
---|
| 1018 |
|
---|
[2405] | 1019 | BEGIN lmb_bram_if_cntlr
|
---|
| 1020 | PARAMETER INSTANCE = mb_high_dlmb_bram_cntlr_0
|
---|
| 1021 | PARAMETER HW_VER = 3.10.c
|
---|
| 1022 | PARAMETER C_BASEADDR = 0x00000000
|
---|
| 1023 | PARAMETER C_HIGHADDR = 0x0001FFFF
|
---|
| 1024 | BUS_INTERFACE SLMB = mb_high_dlmb
|
---|
| 1025 | BUS_INTERFACE BRAM_PORT = mb_high_dlmb_bram_cntlr_0_BRAM_PORT
|
---|
| 1026 | END
|
---|
| 1027 |
|
---|
| 1028 | BEGIN lmb_bram_if_cntlr
|
---|
| 1029 | PARAMETER INSTANCE = mb_high_ilmb_bram_cntlr_0
|
---|
| 1030 | PARAMETER HW_VER = 3.10.c
|
---|
| 1031 | PARAMETER C_BASEADDR = 0x00000000
|
---|
| 1032 | PARAMETER C_HIGHADDR = 0x0001FFFF
|
---|
| 1033 | BUS_INTERFACE SLMB = mb_high_ilmb
|
---|
| 1034 | BUS_INTERFACE BRAM_PORT = mb_high_ilmb_bram_cntlr_0_BRAM_PORT
|
---|
| 1035 | END
|
---|
| 1036 |
|
---|
| 1037 | BEGIN bram_block
|
---|
| 1038 | PARAMETER INSTANCE = mb_high_lmb_bram_0
|
---|
| 1039 | PARAMETER HW_VER = 1.00.a
|
---|
| 1040 | BUS_INTERFACE PORTB = mb_high_ilmb_bram_cntlr_0_BRAM_PORT
|
---|
| 1041 | BUS_INTERFACE PORTA = mb_high_dlmb_bram_cntlr_0_BRAM_PORT
|
---|
| 1042 | END
|
---|
| 1043 |
|
---|
| 1044 | BEGIN lmb_bram_if_cntlr
|
---|
| 1045 | PARAMETER INSTANCE = mb_high_dlmb_bram_cntlr_1
|
---|
| 1046 | PARAMETER HW_VER = 3.10.c
|
---|
| 1047 | PARAMETER C_BASEADDR = 0x00020000
|
---|
| 1048 | PARAMETER C_HIGHADDR = 0x0003FFFF
|
---|
| 1049 | BUS_INTERFACE SLMB = mb_high_dlmb
|
---|
| 1050 | BUS_INTERFACE BRAM_PORT = mb_high_dlmb_bram_cntlr_1_BRAM_PORT
|
---|
| 1051 | END
|
---|
| 1052 |
|
---|
| 1053 | BEGIN lmb_bram_if_cntlr
|
---|
| 1054 | PARAMETER INSTANCE = mb_high_ilmb_bram_cntlr_1
|
---|
| 1055 | PARAMETER HW_VER = 3.10.c
|
---|
| 1056 | PARAMETER C_BASEADDR = 0x00020000
|
---|
| 1057 | PARAMETER C_HIGHADDR = 0x0003FFFF
|
---|
| 1058 | BUS_INTERFACE SLMB = mb_high_ilmb
|
---|
| 1059 | BUS_INTERFACE BRAM_PORT = mb_high_ilmb_bram_cntlr_1_BRAM_PORT
|
---|
| 1060 | END
|
---|
| 1061 |
|
---|
| 1062 | BEGIN bram_block
|
---|
| 1063 | PARAMETER INSTANCE = mb_high_lmb_bram_1
|
---|
| 1064 | PARAMETER HW_VER = 1.00.a
|
---|
| 1065 | BUS_INTERFACE PORTA = mb_high_dlmb_bram_cntlr_1_BRAM_PORT
|
---|
| 1066 | BUS_INTERFACE PORTB = mb_high_ilmb_bram_cntlr_1_BRAM_PORT
|
---|
| 1067 | END
|
---|
| 1068 |
|
---|
[4733] | 1069 | # ##############################################################################
|
---|
| 1070 | # Microblaze High Standard Peripherals
|
---|
| 1071 | # ##############################################################################
|
---|
| 1072 | BEGIN axi_interconnect
|
---|
| 1073 | PARAMETER INSTANCE = mb_high_axi_periph
|
---|
| 1074 | PARAMETER HW_VER = 1.06.a
|
---|
| 1075 | PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
|
---|
| 1076 | PORT INTERCONNECT_ARESETN = sys_reset_Interconnect_aresetn
|
---|
| 1077 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 1078 | END
|
---|
| 1079 |
|
---|
| 1080 | BEGIN axi_uartlite
|
---|
| 1081 | PARAMETER INSTANCE = mb_high_uart
|
---|
| 1082 | PARAMETER HW_VER = 1.02.a
|
---|
| 1083 | PARAMETER C_BAUDRATE = 115200
|
---|
| 1084 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
|
---|
| 1085 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
|
---|
| 1086 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
|
---|
| 1087 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
|
---|
| 1088 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
|
---|
| 1089 | PARAMETER C_BASEADDR = 0x21000000
|
---|
| 1090 | PARAMETER C_HIGHADDR = 0x2100FFFF
|
---|
| 1091 | BUS_INTERFACE S_AXI = mb_high_axi_periph
|
---|
| 1092 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1093 | # RX=input to uartartlite (PC -> FPGA)
|
---|
| 1094 | # TX=output from uartlite (FPGA -> PC)
|
---|
| 1095 | PORT RX = mb_high_uart_RX
|
---|
| 1096 | PORT TX = mb_high_uart_TX
|
---|
| 1097 | PORT Interrupt = mb_high_uart_Interrupt
|
---|
| 1098 | END
|
---|
| 1099 |
|
---|
[6308] | 1100 | BEGIN sw_intr_util
|
---|
| 1101 | PARAMETER INSTANCE = high_sw_intr_util
|
---|
| 1102 | PARAMETER HW_VER = 1.00.a
|
---|
| 1103 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
|
---|
| 1104 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
|
---|
| 1105 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
|
---|
| 1106 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
|
---|
| 1107 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
|
---|
| 1108 | PARAMETER C_BASEADDR = 0x23010000
|
---|
| 1109 | PARAMETER C_HIGHADDR = 0x2301FFFF
|
---|
| 1110 | BUS_INTERFACE S_AXI = mb_high_axi_periph
|
---|
| 1111 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1112 | PORT intrA_out = SW_INTR_A
|
---|
| 1113 | PORT intrB_out = SW_INTR_B
|
---|
| 1114 | END
|
---|
| 1115 |
|
---|
[4733] | 1116 | BEGIN axi_timer
|
---|
| 1117 | PARAMETER INSTANCE = mb_high_timer
|
---|
| 1118 | PARAMETER HW_VER = 1.03.a
|
---|
| 1119 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
|
---|
| 1120 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
|
---|
| 1121 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
|
---|
| 1122 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
|
---|
| 1123 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
|
---|
| 1124 | PARAMETER C_BASEADDR = 0x23000000
|
---|
| 1125 | PARAMETER C_HIGHADDR = 0x2300FFFF
|
---|
| 1126 | BUS_INTERFACE S_AXI = mb_high_axi_periph
|
---|
| 1127 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1128 | PORT Interrupt = mb_high_timer_Interrupt
|
---|
| 1129 | END
|
---|
| 1130 |
|
---|
| 1131 | BEGIN axi_intc
|
---|
| 1132 | PARAMETER INSTANCE = mb_high_intc
|
---|
| 1133 | PARAMETER HW_VER = 1.03.a
|
---|
| 1134 | PARAMETER C_BASEADDR = 0x22000000
|
---|
| 1135 | PARAMETER C_HIGHADDR = 0x2200FFFF
|
---|
| 1136 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
|
---|
| 1137 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
|
---|
| 1138 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
|
---|
| 1139 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
|
---|
| 1140 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
|
---|
| 1141 | BUS_INTERFACE S_AXI = mb_high_axi_periph
|
---|
| 1142 | BUS_INTERFACE INTERRUPT = mb_high_interrupt
|
---|
[6308] | 1143 | PORT Intr = SW_INTR_B & ETH_A_MAC_INTERRUPT & ETH_B_MAC_INTERRUPT & mb_high_sw_gpio_IP2INTC_Irpt & mb_high_uart_Interrupt & ETH_A_DMA_mm2s_introut & ETH_A_DMA_s2mm_introut & ETH_B_DMA_mm2s_introut & ETH_B_DMA_s2mm_introut & SW_INTR_A & mb_high_timer_Interrupt & mb_mailbox_Interrupt_0
|
---|
[4733] | 1144 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1145 | END
|
---|
| 1146 |
|
---|
| 1147 | BEGIN axi_gpio
|
---|
| 1148 | PARAMETER INSTANCE = mb_high_sw_gpio
|
---|
| 1149 | PARAMETER HW_VER = 1.01.b
|
---|
| 1150 | PARAMETER C_BASEADDR = 0x20000000
|
---|
| 1151 | PARAMETER C_HIGHADDR = 0x2000FFFF
|
---|
| 1152 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
|
---|
| 1153 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
|
---|
| 1154 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
|
---|
| 1155 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
|
---|
| 1156 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
|
---|
[5545] | 1157 | PARAMETER C_IS_DUAL = 0
|
---|
| 1158 | PARAMETER C_GPIO_WIDTH = 9
|
---|
| 1159 | PARAMETER C_ALL_INPUTS = 1
|
---|
[4733] | 1160 | PARAMETER C_INTERRUPT_PRESENT = 1
|
---|
| 1161 | BUS_INTERFACE S_AXI = mb_high_axi_periph
|
---|
| 1162 | PORT S_AXI_ACLK = clk_160MHz
|
---|
[5545] | 1163 | PORT GPIO_IO_I = dram_init_done & 0b0 & userio_pb_u & userio_pb_m & userio_pb_d & userio_dipsw_b0 & userio_dipsw_b1 & userio_dipsw_b2 & userio_dipsw_b3
|
---|
[4733] | 1164 | PORT IP2INTC_Irpt = mb_high_sw_gpio_IP2INTC_Irpt
|
---|
| 1165 | END
|
---|
| 1166 |
|
---|
[2086] | 1167 | BEGIN axi_bram_ctrl
|
---|
[2405] | 1168 | PARAMETER INSTANCE = mb_high_aux_bram_ctrl
|
---|
[2086] | 1169 | PARAMETER HW_VER = 1.03.a
|
---|
| 1170 | PARAMETER C_S_AXI_DATA_WIDTH = 64
|
---|
[5743] | 1171 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = mb_high.M_AXI_DC & axi2axi_eth_a_dma.M_AXI & axi2axi_eth_b_dma.M_AXI
|
---|
[2405] | 1172 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 1173 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
[2086] | 1174 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1175 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
[2405] | 1176 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[4733] | 1177 | PARAMETER C_S_AXI_BASEADDR = 0xA0000000
|
---|
| 1178 | PARAMETER C_S_AXI_HIGHADDR = 0xA000FFFF
|
---|
[2405] | 1179 | BUS_INTERFACE BRAM_PORTA = MB_HIGH_AUX_BRAM_PORTA
|
---|
| 1180 | BUS_INTERFACE BRAM_PORTB = MB_HIGH_AUX_BRAM_PORTB
|
---|
[2086] | 1181 | BUS_INTERFACE S_AXI = mb_shared_axi
|
---|
| 1182 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1183 | END
|
---|
| 1184 |
|
---|
| 1185 | BEGIN bram_block
|
---|
[2405] | 1186 | PARAMETER INSTANCE = mb_high_aux_bram
|
---|
[2086] | 1187 | PARAMETER HW_VER = 1.00.a
|
---|
[2405] | 1188 | BUS_INTERFACE PORTA = MB_HIGH_AUX_BRAM_PORTA
|
---|
| 1189 | BUS_INTERFACE PORTB = MB_HIGH_AUX_BRAM_PORTB
|
---|
[2086] | 1190 | END
|
---|
| 1191 |
|
---|
| 1192 | BEGIN axi_cdma
|
---|
| 1193 | PARAMETER INSTANCE = axi_cdma_0
|
---|
| 1194 | PARAMETER HW_VER = 3.04.a
|
---|
| 1195 | PARAMETER C_M_AXI_DATA_WIDTH = 64
|
---|
| 1196 | PARAMETER C_M_AXI_MAX_BURST_LEN = 64
|
---|
| 1197 | PARAMETER C_INCLUDE_DRE = 1
|
---|
[2405] | 1198 | PARAMETER C_INTERCONNECT_M_AXI_AW_REGISTER = 7
|
---|
| 1199 | PARAMETER C_INTERCONNECT_M_AXI_AR_REGISTER = 7
|
---|
[2086] | 1200 | PARAMETER C_INTERCONNECT_M_AXI_W_REGISTER = 1
|
---|
| 1201 | PARAMETER C_INTERCONNECT_M_AXI_R_REGISTER = 1
|
---|
[2405] | 1202 | PARAMETER C_INTERCONNECT_M_AXI_B_REGISTER = 7
|
---|
[2086] | 1203 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 8
|
---|
| 1204 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 8
|
---|
| 1205 | PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 8
|
---|
| 1206 | PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 8
|
---|
| 1207 | PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 8
|
---|
[4733] | 1208 | PARAMETER C_BASEADDR = 0x48000000
|
---|
| 1209 | PARAMETER C_HIGHADDR = 0x4800FFFF
|
---|
[2086] | 1210 | BUS_INTERFACE S_AXI_LITE = mb_high_axi_periph
|
---|
| 1211 | BUS_INTERFACE M_AXI = mb_shared_axi
|
---|
| 1212 | PORT s_axi_lite_aclk = clk_160MHz
|
---|
| 1213 | PORT m_axi_aclk = clk_160MHz
|
---|
| 1214 | END
|
---|
| 1215 |
|
---|
[4733] | 1216 | # ##############################################################################
|
---|
| 1217 | # Ethernet
|
---|
| 1218 | # ##############################################################################
|
---|
| 1219 | BEGIN axi_interconnect
|
---|
| 1220 | PARAMETER INSTANCE = ethernet_axi
|
---|
| 1221 | PARAMETER HW_VER = 1.06.a
|
---|
| 1222 | PARAMETER C_INTERCONNECT_DATA_WIDTH = 64
|
---|
| 1223 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 1224 | PORT INTERCONNECT_ARESETN = sys_reset_Interconnect_aresetn
|
---|
[2086] | 1225 | END
|
---|
| 1226 |
|
---|
[4733] | 1227 | BEGIN axi2axi_connector
|
---|
[4853] | 1228 | PARAMETER INSTANCE = axi2axi_eth_a_dma
|
---|
[4733] | 1229 | PARAMETER HW_VER = 1.00.a
|
---|
| 1230 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ETH_A_DMA.M_AXI_SG & ETH_A_DMA.M_AXI_MM2S & ETH_A_DMA.M_AXI_S2MM
|
---|
[4867] | 1231 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0x00000000
|
---|
| 1232 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0xFFFFFFFF
|
---|
[4853] | 1233 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 1234 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
[4867] | 1235 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 1236 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
[4853] | 1237 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[4733] | 1238 | BUS_INTERFACE S_AXI = ethernet_axi
|
---|
| 1239 | BUS_INTERFACE M_AXI = mb_shared_axi
|
---|
| 1240 | END
|
---|
| 1241 |
|
---|
| 1242 | BEGIN axi2axi_connector
|
---|
[4853] | 1243 | PARAMETER INSTANCE = axi2axi_eth_b_dma
|
---|
[4733] | 1244 | PARAMETER HW_VER = 1.00.a
|
---|
| 1245 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ETH_B_DMA.M_AXI_SG & ETH_B_DMA.M_AXI_MM2S & ETH_B_DMA.M_AXI_S2MM
|
---|
[4867] | 1246 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0x00000000
|
---|
| 1247 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0xFFFFFFFF
|
---|
[4853] | 1248 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 1249 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
[4867] | 1250 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 1251 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
[4853] | 1252 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[4733] | 1253 | BUS_INTERFACE S_AXI = ethernet_axi
|
---|
| 1254 | BUS_INTERFACE M_AXI = mb_shared_axi
|
---|
| 1255 | END
|
---|
| 1256 |
|
---|
[2254] | 1257 | BEGIN axi_ethernet
|
---|
[2405] | 1258 | PARAMETER INSTANCE = ETH_A_MAC
|
---|
| 1259 | PARAMETER HW_VER = 3.01.a
|
---|
| 1260 | # ETH_A PHY Address = 6 on WARP v3 1.1
|
---|
| 1261 | PARAMETER C_PHYADDR = 0B00110
|
---|
| 1262 | PARAMETER C_INCLUDE_IO = 1
|
---|
| 1263 | PARAMETER C_TYPE = 2
|
---|
| 1264 | PARAMETER C_PHY_TYPE = 3
|
---|
| 1265 | PARAMETER C_HALFDUP = 0
|
---|
[5090] | 1266 | PARAMETER C_TXMEM = 16384
|
---|
| 1267 | PARAMETER C_RXMEM = 16384
|
---|
[2797] | 1268 | PARAMETER C_TXCSUM = 0
|
---|
| 1269 | PARAMETER C_RXCSUM = 0
|
---|
[2405] | 1270 | PARAMETER C_TXVLAN_TRAN = 0
|
---|
| 1271 | PARAMETER C_RXVLAN_TRAN = 0
|
---|
| 1272 | PARAMETER C_TXVLAN_TAG = 0
|
---|
| 1273 | PARAMETER C_RXVLAN_TAG = 0
|
---|
| 1274 | PARAMETER C_TXVLAN_STRP = 0
|
---|
| 1275 | PARAMETER C_RXVLAN_STRP = 0
|
---|
| 1276 | PARAMETER C_MCAST_EXTEND = 0
|
---|
| 1277 | PARAMETER C_STATS = 0
|
---|
| 1278 | PARAMETER C_AVB = 0
|
---|
| 1279 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
|
---|
| 1280 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
|
---|
| 1281 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
|
---|
| 1282 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
|
---|
| 1283 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
|
---|
[4733] | 1284 | PARAMETER C_BASEADDR = 0x40000000
|
---|
| 1285 | PARAMETER C_HIGHADDR = 0x4003FFFF
|
---|
[2405] | 1286 | BUS_INTERFACE S_AXI = mb_high_axi_periph
|
---|
| 1287 | BUS_INTERFACE AXI_STR_RXD = ETH_A_MAC_AXIS_RXD
|
---|
| 1288 | BUS_INTERFACE AXI_STR_RXS = ETH_A_MAC_AXIS_RXS
|
---|
| 1289 | BUS_INTERFACE AXI_STR_TXD = ETH_A_MAC_AXIS_TXD
|
---|
| 1290 | BUS_INTERFACE AXI_STR_TXC = ETH_A_MAC_AXIS_TXC
|
---|
| 1291 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1292 | PORT GTX_CLK = clk_125MHz
|
---|
| 1293 | PORT PHY_RST_N = ETH_A_PHY_RST_N
|
---|
| 1294 | PORT MDIO = ETH_A_MDIO
|
---|
| 1295 | PORT MDC = ETH_A_MDC
|
---|
| 1296 | PORT REF_CLK = clk_200MHz
|
---|
| 1297 | # AXI Stream connections (to FIFO or DMA)
|
---|
| 1298 | PORT AXI_STR_TXD_ACLK = clk_160MHz
|
---|
| 1299 | PORT AXI_STR_TXC_ACLK = clk_160MHz
|
---|
| 1300 | PORT AXI_STR_RXD_ACLK = clk_160MHz
|
---|
| 1301 | PORT AXI_STR_RXS_ACLK = clk_160MHz
|
---|
| 1302 | # RGMII connections (to Eth PHY IC on PCB)
|
---|
| 1303 | PORT RGMII_TXD = ETH_A_RGMII_TXD
|
---|
| 1304 | PORT RGMII_TX_CTL = ETH_A_RGMII_TX_CTL
|
---|
| 1305 | PORT RGMII_TXC = ETH_A_RGMII_TXC
|
---|
| 1306 | PORT RGMII_RXD = ETH_A_RGMII_RXD
|
---|
| 1307 | PORT RGMII_RX_CTL = ETH_A_RGMII_RX_CTL
|
---|
| 1308 | PORT RGMII_RXC = ETH_A_RGMII_RXC
|
---|
| 1309 | PORT INTERRUPT = ETH_A_MAC_INTERRUPT
|
---|
| 1310 | END
|
---|
| 1311 |
|
---|
[4733] | 1312 | BEGIN axi_dma
|
---|
| 1313 | PARAMETER INSTANCE = ETH_A_DMA
|
---|
| 1314 | PARAMETER HW_VER = 6.03.a
|
---|
| 1315 | PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
|
---|
| 1316 | PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
|
---|
| 1317 | PARAMETER C_INCLUDE_MM2S_DRE = 1
|
---|
| 1318 | PARAMETER C_M_AXI_S2MM_DATA_WIDTH = 64
|
---|
| 1319 | PARAMETER C_INCLUDE_S2MM_DRE = 1
|
---|
| 1320 | PARAMETER C_BASEADDR = 0x42000000
|
---|
| 1321 | PARAMETER C_HIGHADDR = 0x4200FFFF
|
---|
| 1322 | PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 7
|
---|
| 1323 | PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 7
|
---|
| 1324 | PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 1
|
---|
| 1325 | PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 1
|
---|
| 1326 | PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 7
|
---|
| 1327 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 7
|
---|
| 1328 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 7
|
---|
| 1329 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 1
|
---|
| 1330 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 1
|
---|
| 1331 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 7
|
---|
| 1332 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 7
|
---|
| 1333 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 7
|
---|
| 1334 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 1
|
---|
| 1335 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 1
|
---|
| 1336 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 7
|
---|
| 1337 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 8
|
---|
| 1338 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 8
|
---|
| 1339 | PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 8
|
---|
| 1340 | PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 8
|
---|
| 1341 | PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 8
|
---|
| 1342 | BUS_INTERFACE S_AXI_LITE = mb_high_axi_periph
|
---|
| 1343 | BUS_INTERFACE M_AXI_SG = ethernet_axi
|
---|
| 1344 | BUS_INTERFACE M_AXI_MM2S = ethernet_axi
|
---|
| 1345 | BUS_INTERFACE M_AXI_S2MM = ethernet_axi
|
---|
| 1346 | BUS_INTERFACE S_AXIS_S2MM = ETH_A_MAC_AXIS_RXD
|
---|
| 1347 | BUS_INTERFACE S_AXIS_S2MM_STS = ETH_A_MAC_AXIS_RXS
|
---|
| 1348 | BUS_INTERFACE M_AXIS_MM2S = ETH_A_MAC_AXIS_TXD
|
---|
| 1349 | BUS_INTERFACE M_AXIS_MM2S_CNTRL = ETH_A_MAC_AXIS_TXC
|
---|
| 1350 | PORT s_axi_lite_aclk = clk_160MHz
|
---|
| 1351 | PORT m_axi_sg_aclk = clk_160MHz
|
---|
| 1352 | PORT m_axi_mm2s_aclk = clk_160MHz
|
---|
| 1353 | PORT m_axi_s2mm_aclk = clk_160MHz
|
---|
| 1354 | PORT mm2s_introut = ETH_A_DMA_mm2s_introut
|
---|
| 1355 | PORT s2mm_introut = ETH_A_DMA_s2mm_introut
|
---|
| 1356 | PORT s_axis_s2mm_tuser = net_gnd
|
---|
| 1357 | PORT s_axis_s2mm_tid = net_gnd
|
---|
| 1358 | PORT s_axis_s2mm_tdest = net_gnd
|
---|
| 1359 | END
|
---|
| 1360 |
|
---|
[2405] | 1361 | BEGIN axi_ethernet
|
---|
[2254] | 1362 | PARAMETER INSTANCE = ETH_B_MAC
|
---|
| 1363 | PARAMETER HW_VER = 3.01.a
|
---|
| 1364 | # ETH_B PHY Address = 7 on WARP v3 1.1
|
---|
| 1365 | PARAMETER C_PHYADDR = 0B00111
|
---|
| 1366 | PARAMETER C_INCLUDE_IO = 1
|
---|
| 1367 | PARAMETER C_TYPE = 2
|
---|
| 1368 | PARAMETER C_PHY_TYPE = 3
|
---|
| 1369 | PARAMETER C_HALFDUP = 0
|
---|
[4733] | 1370 | PARAMETER C_TXMEM = 16384
|
---|
| 1371 | PARAMETER C_RXMEM = 16384
|
---|
[4853] | 1372 | PARAMETER C_TXCSUM = 0
|
---|
| 1373 | PARAMETER C_RXCSUM = 0
|
---|
[2254] | 1374 | PARAMETER C_TXVLAN_TRAN = 0
|
---|
| 1375 | PARAMETER C_RXVLAN_TRAN = 0
|
---|
| 1376 | PARAMETER C_TXVLAN_TAG = 0
|
---|
| 1377 | PARAMETER C_RXVLAN_TAG = 0
|
---|
| 1378 | PARAMETER C_TXVLAN_STRP = 0
|
---|
| 1379 | PARAMETER C_RXVLAN_STRP = 0
|
---|
| 1380 | PARAMETER C_MCAST_EXTEND = 0
|
---|
| 1381 | PARAMETER C_STATS = 0
|
---|
| 1382 | PARAMETER C_AVB = 0
|
---|
| 1383 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 8
|
---|
| 1384 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 8
|
---|
| 1385 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 8
|
---|
| 1386 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 8
|
---|
| 1387 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 8
|
---|
[4733] | 1388 | PARAMETER C_BASEADDR = 0x41000000
|
---|
| 1389 | PARAMETER C_HIGHADDR = 0x4103FFFF
|
---|
[2254] | 1390 | BUS_INTERFACE S_AXI = mb_high_axi_periph
|
---|
| 1391 | BUS_INTERFACE AXI_STR_RXD = ETH_B_MAC_AXIS_RXD
|
---|
[4733] | 1392 | BUS_INTERFACE AXI_STR_RXS = ETH_B_MAC_AXIS_RXS
|
---|
[2254] | 1393 | BUS_INTERFACE AXI_STR_TXD = ETH_B_MAC_AXIS_TXD
|
---|
| 1394 | BUS_INTERFACE AXI_STR_TXC = ETH_B_MAC_AXIS_TXC
|
---|
| 1395 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1396 | PORT GTX_CLK = clk_125MHz
|
---|
| 1397 | # PORT PHY_RST_N = ETH_B_PHY_RST_N
|
---|
| 1398 | PORT MDIO = ETH_B_MDIO
|
---|
| 1399 | PORT MDC = ETH_B_MDC
|
---|
| 1400 | PORT REF_CLK = clk_200MHz
|
---|
| 1401 | # AXI Stream connections (to FIFO or DMA)
|
---|
| 1402 | PORT AXI_STR_TXD_ACLK = clk_160MHz
|
---|
| 1403 | PORT AXI_STR_TXC_ACLK = clk_160MHz
|
---|
| 1404 | PORT AXI_STR_RXD_ACLK = clk_160MHz
|
---|
| 1405 | PORT AXI_STR_RXS_ACLK = clk_160MHz
|
---|
| 1406 | PORT AXI_STR_RXS_TREADY = net_vcc
|
---|
| 1407 | # RGMII connections (to Eth PHY IC on PCB)
|
---|
| 1408 | PORT RGMII_TXD = ETH_B_RGMII_TXD
|
---|
| 1409 | PORT RGMII_TX_CTL = ETH_B_RGMII_TX_CTL
|
---|
| 1410 | PORT RGMII_TXC = ETH_B_RGMII_TXC
|
---|
| 1411 | PORT RGMII_RXD = ETH_B_RGMII_RXD
|
---|
| 1412 | PORT RGMII_RX_CTL = ETH_B_RGMII_RX_CTL
|
---|
| 1413 | PORT RGMII_RXC = ETH_B_RGMII_RXC
|
---|
| 1414 | PORT INTERRUPT = ETH_B_MAC_INTERRUPT
|
---|
| 1415 | END
|
---|
| 1416 |
|
---|
[4733] | 1417 | BEGIN axi_dma
|
---|
| 1418 | PARAMETER INSTANCE = ETH_B_DMA
|
---|
| 1419 | PARAMETER HW_VER = 6.03.a
|
---|
| 1420 | PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
|
---|
| 1421 | PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
|
---|
| 1422 | PARAMETER C_INCLUDE_MM2S_DRE = 1
|
---|
| 1423 | PARAMETER C_M_AXI_S2MM_DATA_WIDTH = 64
|
---|
| 1424 | PARAMETER C_INCLUDE_S2MM_DRE = 1
|
---|
| 1425 | PARAMETER C_BASEADDR = 0x43000000
|
---|
| 1426 | PARAMETER C_HIGHADDR = 0x4300FFFF
|
---|
| 1427 | PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 7
|
---|
| 1428 | PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 7
|
---|
| 1429 | PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 1
|
---|
| 1430 | PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 1
|
---|
| 1431 | PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 7
|
---|
| 1432 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 7
|
---|
| 1433 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 7
|
---|
| 1434 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 1
|
---|
| 1435 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 1
|
---|
| 1436 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 7
|
---|
| 1437 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 7
|
---|
| 1438 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 7
|
---|
| 1439 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 1
|
---|
| 1440 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 1
|
---|
| 1441 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 7
|
---|
| 1442 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 8
|
---|
| 1443 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 8
|
---|
| 1444 | PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 8
|
---|
| 1445 | PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 8
|
---|
| 1446 | PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 8
|
---|
| 1447 | BUS_INTERFACE S_AXI_LITE = mb_high_axi_periph
|
---|
| 1448 | BUS_INTERFACE M_AXI_SG = ethernet_axi
|
---|
| 1449 | BUS_INTERFACE M_AXI_MM2S = ethernet_axi
|
---|
| 1450 | BUS_INTERFACE M_AXI_S2MM = ethernet_axi
|
---|
| 1451 | BUS_INTERFACE S_AXIS_S2MM = ETH_B_MAC_AXIS_RXD
|
---|
| 1452 | BUS_INTERFACE S_AXIS_S2MM_STS = ETH_B_MAC_AXIS_RXS
|
---|
| 1453 | BUS_INTERFACE M_AXIS_MM2S_CNTRL = ETH_B_MAC_AXIS_TXC
|
---|
| 1454 | BUS_INTERFACE M_AXIS_MM2S = ETH_B_MAC_AXIS_TXD
|
---|
| 1455 | PORT s_axi_lite_aclk = clk_160MHz
|
---|
| 1456 | PORT m_axi_sg_aclk = clk_160MHz
|
---|
| 1457 | PORT m_axi_mm2s_aclk = clk_160MHz
|
---|
| 1458 | PORT m_axi_s2mm_aclk = clk_160MHz
|
---|
| 1459 | PORT mm2s_introut = ETH_B_DMA_mm2s_introut
|
---|
| 1460 | PORT s2mm_introut = ETH_B_DMA_s2mm_introut
|
---|
| 1461 | PORT s_axis_s2mm_tuser = net_gnd
|
---|
| 1462 | PORT s_axis_s2mm_tid = net_gnd
|
---|
| 1463 | PORT s_axis_s2mm_tdest = net_gnd
|
---|
[2254] | 1464 | END
|
---|
| 1465 |
|
---|
[4733] | 1466 | # ##############################################################################
|
---|
| 1467 | # DDR
|
---|
| 1468 | # ##############################################################################
|
---|
[2254] | 1469 | BEGIN axi_v6_ddrx
|
---|
| 1470 | PARAMETER INSTANCE = DDR3_SODIMM
|
---|
| 1471 | PARAMETER HW_VER = 1.06.a
|
---|
| 1472 | PARAMETER C_MEM_PARTNO = MT8JSF25664HZ-1G4
|
---|
| 1473 | PARAMETER C_CK_WIDTH = 2
|
---|
| 1474 | PARAMETER C_ROW_WIDTH = 15
|
---|
| 1475 | PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y0
|
---|
| 1476 | # Manually entered params (extracted from MIG-ISE test design that worked in hardware)
|
---|
| 1477 | PARAMETER C_NDQS_COL0 = 5
|
---|
| 1478 | PARAMETER C_NDQS_COL1 = 3
|
---|
| 1479 | PARAMETER C_NDQS_COL2 = 0
|
---|
| 1480 | PARAMETER C_NDQS_COL3 = 0
|
---|
| 1481 | PARAMETER C_DQS_LOC_COL0 = 0x0403020100
|
---|
| 1482 | PARAMETER C_DQS_LOC_COL1 = 0x0000070605
|
---|
| 1483 | PARAMETER C_ECC = OFF
|
---|
| 1484 | # END Manually entered params
|
---|
| 1485 | PARAMETER C_TCK = 3125
|
---|
| 1486 | PARAMETER C_S_AXI_DATA_WIDTH = 64
|
---|
| 1487 | PARAMETER C_S_AXI_BASEADDR = 0xc0000000
|
---|
| 1488 | PARAMETER C_S_AXI_HIGHADDR = 0xffffffff
|
---|
[4853] | 1489 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_eth_a_dma.M_AXI & axi2axi_eth_b_dma.M_AXI & mb_high.M_AXI_DC & axi_cdma_0.M_AXI
|
---|
[2405] | 1490 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 1491 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
[2254] | 1492 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1493 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
[2405] | 1494 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
[2254] | 1495 | BUS_INTERFACE S_AXI = mb_shared_axi
|
---|
| 1496 | PORT clk = clk_160MHz
|
---|
[5490] | 1497 | PORT clk_mem = clk_dram_320MHz_clk_mem
|
---|
| 1498 | PORT clk_rd_base = clk_dram_320MHz_clk_rd_base
|
---|
[2254] | 1499 | PORT clk_ref = clk_200MHz
|
---|
| 1500 | PORT pd_PSEN = MMCM_PSEN
|
---|
| 1501 | PORT pd_PSINCDEC = MMCM_PSINCDEC
|
---|
| 1502 | PORT pd_PSDONE = MMCM_PSDONE
|
---|
| 1503 | PORT ddr_ck_p = ddr3_sodimm_ck_p
|
---|
| 1504 | PORT ddr_ck_n = ddr3_sodimm_ck_n
|
---|
| 1505 | PORT ddr_cke = ddr3_sodimm_cke
|
---|
| 1506 | PORT ddr_cs_n = ddr3_sodimm_cs_n
|
---|
| 1507 | PORT ddr_odt = ddr3_sodimm_odt
|
---|
| 1508 | PORT ddr_ras_n = ddr3_sodimm_ras_n
|
---|
| 1509 | PORT ddr_cas_n = ddr3_sodimm_cas_n
|
---|
| 1510 | PORT ddr_we_n = ddr3_sodimm_we_n
|
---|
| 1511 | PORT ddr_ba = ddr3_sodimm_ba
|
---|
| 1512 | PORT ddr_addr = ddr3_sodimm_addr
|
---|
| 1513 | PORT ddr_dq = ddr3_sodimm_dq
|
---|
| 1514 | PORT ddr_dm = ddr3_sodimm_dm
|
---|
| 1515 | PORT ddr_reset_n = ddr3_sodimm_reset_n
|
---|
| 1516 | PORT ddr_dqs_p = ddr3_sodimm_dqs_p
|
---|
| 1517 | PORT ddr_dqs_n = ddr3_sodimm_dqs_n
|
---|
| 1518 | PORT phy_init_done = dram_init_done
|
---|
[2086] | 1519 | END
|
---|
| 1520 |
|
---|
[4733] | 1521 | # ##############################################################################
|
---|
| 1522 | # Debug / Misc Logic
|
---|
| 1523 | # ##############################################################################
|
---|
| 1524 | BEGIN mdm
|
---|
| 1525 | PARAMETER INSTANCE = debug_module
|
---|
| 1526 | PARAMETER HW_VER = 2.10.a
|
---|
| 1527 | PARAMETER C_USE_UART = 0
|
---|
| 1528 | PARAMETER C_MB_DBG_PORTS = 2
|
---|
| 1529 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
|
---|
| 1530 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
|
---|
| 1531 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
|
---|
| 1532 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
|
---|
| 1533 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
|
---|
| 1534 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = mb_low.M_AXI_DC & mb_high.M_AXI_DC
|
---|
| 1535 | BUS_INTERFACE MBDEBUG_0 = mb_low_debug
|
---|
| 1536 | BUS_INTERFACE MBDEBUG_1 = mb_high_debug
|
---|
| 1537 | PORT Debug_SYS_Rst = sys_reset_debug_rst
|
---|
[2405] | 1538 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1539 | END
|
---|
| 1540 |
|
---|
[4733] | 1541 | BEGIN util_reduced_logic
|
---|
| 1542 | PARAMETER INSTANCE = clk_gen_locked_AND
|
---|
| 1543 | PARAMETER HW_VER = 1.00.a
|
---|
| 1544 | PARAMETER C_OPERATION = AND
|
---|
| 1545 | PARAMETER C_SIZE = 3
|
---|
[5490] | 1546 | PORT Op1 = clk_gen_proc_bus_clks_locked & clk_gen_async_clks_locked & clk_gen_dram_clks_locked
|
---|
[4733] | 1547 | PORT Res = clk_gen_all_locked
|
---|
[2797] | 1548 | END
|
---|
| 1549 |
|
---|
[4733] | 1550 | BEGIN uart_mux
|
---|
| 1551 | PARAMETER INSTANCE = usb_uart_mux
|
---|
| 1552 | PARAMETER HW_VER = 1.00.a
|
---|
| 1553 | PARAMETER MIRROR_UART_RX = 0
|
---|
| 1554 | PORT uart_sel = userio_dipsw_b3
|
---|
| 1555 | PORT uart_tx = mb_uart_mux_tx
|
---|
| 1556 | PORT uart_rx = usb_uart_rx
|
---|
| 1557 | PORT uart_0_tx = mb_low_uart_TX
|
---|
| 1558 | PORT uart_0_rx = mb_low_uart_RX
|
---|
| 1559 | PORT uart_1_tx = mb_high_uart_TX
|
---|
| 1560 | PORT uart_1_rx = mb_high_uart_RX
|
---|
| 1561 | END
|
---|
| 1562 |
|
---|
[4705] | 1563 | BEGIN w3_boot_io_mux
|
---|
| 1564 | PARAMETER INSTANCE = boot_io_mux
|
---|
| 1565 | PARAMETER HW_VER = 1.00.a
|
---|
| 1566 | # Mux Control
|
---|
| 1567 | PORT iic_sel_a = mmcm_inputs_invalid
|
---|
| 1568 | PORT uart_sel_a = mmcm_inputs_invalid
|
---|
| 1569 | # IOBs
|
---|
| 1570 | PORT iic_scl = iic_eeprom_onboard_scl
|
---|
| 1571 | PORT iic_sda = iic_eeprom_onboard_sda
|
---|
| 1572 | PORT uart_tx = usb_uart_tx
|
---|
| 1573 | # IIC Port A
|
---|
| 1574 | PORT iic_scl_I_a = clk_cfg_iic_eeprom_scl_I
|
---|
| 1575 | PORT iic_scl_O_a = clk_cfg_iic_eeprom_scl_O
|
---|
| 1576 | PORT iic_scl_T_a = clk_cfg_iic_eeprom_scl_T
|
---|
| 1577 | PORT iic_sda_I_a = clk_cfg_iic_eeprom_sda_I
|
---|
| 1578 | PORT iic_sda_O_a = clk_cfg_iic_eeprom_sda_O
|
---|
| 1579 | PORT iic_sda_T_a = clk_cfg_iic_eeprom_sda_T
|
---|
| 1580 | # IIC Port B
|
---|
| 1581 | PORT iic_scl_I_b = axi_iic_eeprom_scl_I
|
---|
| 1582 | PORT iic_scl_O_b = axi_iic_eeprom_scl_O
|
---|
| 1583 | PORT iic_scl_T_b = axi_iic_eeprom_scl_T
|
---|
| 1584 | PORT iic_sda_I_b = axi_iic_eeprom_sda_I
|
---|
| 1585 | PORT iic_sda_O_b = axi_iic_eeprom_sda_O
|
---|
| 1586 | PORT iic_sda_T_b = axi_iic_eeprom_sda_T
|
---|
| 1587 | # UART Ports
|
---|
| 1588 | PORT uart_tx_a = clk_cfg_uart_tx
|
---|
| 1589 | PORT uart_tx_b = mb_uart_mux_tx
|
---|
| 1590 | END
|
---|
| 1591 |
|
---|
[4853] | 1592 | BEGIN util_flipflop
|
---|
| 1593 | PARAMETER INSTANCE = dff_rssi_rfa
|
---|
| 1594 | PARAMETER HW_VER = 1.10.a
|
---|
| 1595 | PARAMETER C_SIZE = 10
|
---|
| 1596 | PARAMETER C_USE_RST = 0
|
---|
| 1597 | PARAMETER C_USE_SET = 0
|
---|
| 1598 | PARAMETER C_USE_CE = 0
|
---|
| 1599 | PARAMETER C_USE_ASYNCH = 0
|
---|
| 1600 | PORT CLK = clk_160MHz
|
---|
| 1601 | PORT D = RFA_RSSI_D
|
---|
| 1602 | PORT Q = RFA_RSSI_D_REG
|
---|
| 1603 | END
|
---|
| 1604 |
|
---|
| 1605 | BEGIN util_flipflop
|
---|
| 1606 | PARAMETER INSTANCE = dff_rssi_rfb
|
---|
| 1607 | PARAMETER HW_VER = 1.10.a
|
---|
| 1608 | PARAMETER C_SIZE = 10
|
---|
| 1609 | PARAMETER C_USE_RST = 0
|
---|
| 1610 | PARAMETER C_USE_SET = 0
|
---|
| 1611 | PARAMETER C_USE_CE = 0
|
---|
| 1612 | PARAMETER C_USE_ASYNCH = 0
|
---|
| 1613 | PORT CLK = clk_160MHz
|
---|
| 1614 | PORT D = RFB_RSSI_D
|
---|
| 1615 | PORT Q = RFB_RSSI_D_REG
|
---|
| 1616 | END
|
---|
| 1617 |
|
---|