1 | # ##############################################################################
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2 | # WARPLab Reference Design
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3 | # XPS Constraint Specification (system.ucf)
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4 | # Copyright 2013 Mango Communications
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5 | # Distributed under the WARP license (http://warpproject.org/license)
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6 | # WARPLab version: 7.6.0
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7 | # Family: virtex6
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8 | # Device: xc6vlx240t
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9 | # Package: ff1156
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10 | # Speed Grade: -1
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11 | # ##############################################################################
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12 |
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13 |
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14 | # ###################################################################
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15 | # Debug Header Ports
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16 | # ###################################################################
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17 |
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18 | NET "DEBUGHDR<0>" LOC = "AG27" | IOSTANDARD = "LVCMOS25"; # pin 0
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19 | NET "DEBUGHDR<1>" LOC = "AE26" | IOSTANDARD = "LVCMOS25"; # pin 1
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20 | NET "debug_sw_gpio<0>" LOC = "AF26" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 2
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21 | NET "debug_sw_gpio<1>" LOC = "AD25" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 3
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22 |
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23 | # NOTE: As of WARPLab 7.5.0, pins 4 - 7 are used as duplicate trigger_out[3:0] ports. To change
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24 | # them back to software GPIO pins, please uncomment the following lines and comment out the
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25 | # first set of trigger_out pins.
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26 | #
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27 | # NET "debug_sw_gpio<2>" LOC = "V24" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 4
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28 | # NET "debug_sw_gpio<3>" LOC = "AA23" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 5
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29 | # NET "debug_sw_gpio<4>" LOC = "AH30" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 6
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30 | # NET "debug_sw_gpio<5>" LOC = "AK31" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 7
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31 |
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32 | NET "trigger_1_out<0>" LOC = "V24" | IOSTANDARD = "LVCMOS25"; # pin 4
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33 | NET "trigger_1_out<1>" LOC = "AA23" | IOSTANDARD = "LVCMOS25"; # pin 5
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34 | NET "trigger_1_out<2>" LOC = "AH30" | IOSTANDARD = "LVCMOS25"; # pin 6
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35 | NET "trigger_1_out<3>" LOC = "AK31" | IOSTANDARD = "LVCMOS25"; # pin 7
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36 |
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37 | NET "trigger_0_out<0>" LOC = "AG28" | IOSTANDARD = "LVCMOS25"; # pin 8
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38 | NET "trigger_0_out<1>" LOC = "AE27" | IOSTANDARD = "LVCMOS25"; # pin 9
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39 | NET "trigger_0_out<2>" LOC = "AF28" | IOSTANDARD = "LVCMOS25"; # pin 10
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40 | NET "trigger_0_out<3>" LOC = "AJ29" | IOSTANDARD = "LVCMOS25"; # pin 11
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41 |
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42 | NET "trigger_in<0>" LOC = "AH29" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 12
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43 | NET "trigger_in<1>" LOC = "AL30" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 13
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44 | NET "trigger_in<2>" LOC = "AM31" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 14
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45 | NET "trigger_in<3>" LOC = "AP32" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # pin 15
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46 |
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47 |
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48 | # ###################################################################
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49 | # Clock & Reset Ports / Definitions
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50 | # ###################################################################
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51 |
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52 | # System clock (80MHz, from sampling clock buffer)
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53 | NET "samp_clk_n" LOC = "V23" | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
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54 | NET "samp_clk_p" LOC = "U23" | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
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55 |
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56 | NET "samp_clk_p" TNM_NET = "samp_clk";
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57 | TIMESPEC "TS_samp_clk" = PERIOD "samp_clk" 80000 kHz;
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58 |
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59 |
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60 | # System clock (200MHz, from LVDS oscillator)
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61 | NET "osc200_p" LOC = "A10" | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
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62 | NET "osc200_n" LOC = "B10" | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
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63 |
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64 | NET "osc200_p" TNM_NET = "osc200_p";
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65 | TIMESPEC "TS_osc200_p" = PERIOD "osc200_p" 200000 kHz;
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66 |
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67 | # System reset
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68 | NET "RESET" LOC = "AH13" | IOSTANDARD = "LVCMOS15" | TIG;
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69 |
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70 |
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71 | # ###################################################################
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72 | # Clock Module Header Ports
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73 | # ###################################################################
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74 |
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75 | # Trigger in/out via CM-PLL daisy chain headers - CM-PLL rev 1.1
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76 | NET "cm_pll_hdr_in_d<0>" LOC = "V28" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # CLKHDR_CTRL3 in W3 schematics
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77 | NET "cm_pll_hdr_in_d<1>" LOC = "V27" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # CLKHDR_CTRL2 in W3 schematics
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78 | NET "cm_pll_hdr_in_d<2>" LOC = "V33" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # CLKHDR_CTRL1 in W3 schematics
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79 | NET "cm_pll_hdr_in_d<3>" LOC = "V34" | IOSTANDARD = "LVCMOS25" | PULLDOWN; # CLKHDR_CTRL0 in W3 schematics
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80 |
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81 | NET "cm_pll_hdr_out_d<0>" LOC = "V32" | IOSTANDARD = "LVCMOS25"; # CLKHDR_CTRL4 in W3 schematics
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82 | NET "cm_pll_hdr_out_d<1>" LOC = "W34" | IOSTANDARD = "LVCMOS25"; # CLKHDR_CTRL5 in W3 schematics
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83 | NET "cm_pll_hdr_out_d<2>" LOC = "W30" | IOSTANDARD = "LVCMOS25"; # CLKHDR_CTRL6 in W3 schematics
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84 | NET "cm_pll_hdr_out_d<3>" LOC = "W29" | IOSTANDARD = "LVCMOS25"; # CLKHDR_CTRL7 in W3 schematics
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85 |
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86 | # SIP switch on clock module
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87 | NET "cm_switch<0>" LOC = "V30" | IOSTANDARD = "LVCMOS25" | PULLUP; # CLKHDR_CTRL12 in W3 schematics
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88 | NET "cm_switch<1>" LOC = "R34" | IOSTANDARD = "LVCMOS25" | PULLUP; # CLKHDR_CTRL13 in W3 schematics
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89 | NET "cm_switch<2>" LOC = "W26" | IOSTANDARD = "LVCMOS25" | PULLUP; # CLKHDR_CTRL14 in W3 schematics
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90 |
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91 | # SPI on clock module
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92 | NET "cm_spi_sclk" LOC = "Y34" | IOSTANDARD = "LVCMOS25"; # CLKHDR_CTRL8 in W3 schematics (CM hdr p25)
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93 | NET "cm_spi_mosi" LOC = "Y31" | IOSTANDARD = "LVCMOS25"; # CLKHDR_CTRL10 in W3 schematics (CM hdr p29)
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94 | NET "cm_spi_miso" LOC = "Y33" | IOSTANDARD = "LVCMOS25"; # CLKHDR_CTRL9 in W3 schematics (CM hdr p27)
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95 | NET "cm_spi_cs_n" LOC = "Y32" | IOSTANDARD = "LVCMOS25"; # CLKHDR_CTRL11 in W3 schematics (CM hdr p31)
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96 | NET "cm_pll_status" LOC = "V29" | IOSTANDARD = "LVCMOS25" | PULLUP; # CLKHDR_CTRL15 in W3 schematics (CM hdr p14)
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97 |
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98 | # FPGA CC pins connected to clock module header
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99 | # NOTE: CM-PLL drives these with copy of selected PLL reference clock
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100 | # NOTE: Constrained to 200MHz (overkill, but easy to meet given the simple logic)
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101 | NET "pll_refclk_p" LOC = "AD24" | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
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102 | NET "pll_refclk_n" LOC = "AE24" | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
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103 |
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104 | NET "pll_refclk_p" TNM_NET = "pll_refclk";
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105 | TIMESPEC "TS_pll_refclk" = PERIOD "pll_refclk" 200000 kHz;
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106 |
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107 |
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108 | # ###################################################################
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109 | # User IO Ports
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110 | # ###################################################################
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111 |
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112 | NET "userio_dipsw<0>" LOC = "AM22" | IOSTANDARD = "LVCMOS15";
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113 | NET "userio_dipsw<1>" LOC = "AL23" | IOSTANDARD = "LVCMOS15";
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114 | NET "userio_dipsw<2>" LOC = "AM23" | IOSTANDARD = "LVCMOS15";
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115 | NET "userio_dipsw<3>" LOC = "AN23" | IOSTANDARD = "LVCMOS15";
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116 |
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117 | NET "userio_leds_red<0>" LOC = "AN34" | IOSTANDARD = "LVCMOS25";
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118 | NET "userio_leds_red<1>" LOC = "AM33" | IOSTANDARD = "LVCMOS25";
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119 | NET "userio_leds_red<2>" LOC = "AN33" | IOSTANDARD = "LVCMOS25";
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120 | NET "userio_leds_red<3>" LOC = "AP33" | IOSTANDARD = "LVCMOS25";
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121 |
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122 | NET "userio_leds_green<0>" LOC = "AD22" | IOSTANDARD = "LVCMOS25";
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123 | NET "userio_leds_green<1>" LOC = "AE22" | IOSTANDARD = "LVCMOS25";
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124 | NET "userio_leds_green<2>" LOC = "AM32" | IOSTANDARD = "LVCMOS25";
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125 | NET "userio_leds_green<3>" LOC = "AN32" | IOSTANDARD = "LVCMOS25";
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126 |
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127 | NET "userio_pb_u" LOC = "AM21" | IOSTANDARD = "LVCMOS15";
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128 | NET "userio_pb_m" LOC = "AN22" | IOSTANDARD = "LVCMOS15";
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129 | NET "userio_pb_d" LOC = "AP22" | IOSTANDARD = "LVCMOS15";
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130 |
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131 | NET "userio_hexdisp_left<0>" LOC = "AL33" | IOSTANDARD = "LVCMOS25";
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132 | NET "userio_hexdisp_left<1>" LOC = "AK33" | IOSTANDARD = "LVCMOS25";
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133 | NET "userio_hexdisp_left<2>" LOC = "AH32" | IOSTANDARD = "LVCMOS25";
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134 | NET "userio_hexdisp_left<3>" LOC = "AF29" | IOSTANDARD = "LVCMOS25";
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135 | NET "userio_hexdisp_left<4>" LOC = "AE29" | IOSTANDARD = "LVCMOS25";
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136 | NET "userio_hexdisp_left<5>" LOC = "AK32" | IOSTANDARD = "LVCMOS25";
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137 | NET "userio_hexdisp_left<6>" LOC = "AF30" | IOSTANDARD = "LVCMOS25";
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138 | NET "userio_hexdisp_left_dp" LOC = "AG30" | IOSTANDARD = "LVCMOS25";
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139 |
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140 | NET "userio_hexdisp_right<0>" LOC = "AE28" | IOSTANDARD = "LVCMOS25";
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141 | NET "userio_hexdisp_right<1>" LOC = "AD26" | IOSTANDARD = "LVCMOS25";
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142 | NET "userio_hexdisp_right<2>" LOC = "AC24" | IOSTANDARD = "LVCMOS25";
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143 | NET "userio_hexdisp_right<3>" LOC = "AE23" | IOSTANDARD = "LVCMOS25";
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144 | NET "userio_hexdisp_right<4>" LOC = "AC22" | IOSTANDARD = "LVCMOS25";
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145 | NET "userio_hexdisp_right<5>" LOC = "AD27" | IOSTANDARD = "LVCMOS25";
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146 | NET "userio_hexdisp_right<6>" LOC = "AB23" | IOSTANDARD = "LVCMOS25";
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147 | NET "userio_hexdisp_right_dp" LOC = "AC23" | IOSTANDARD = "LVCMOS25";
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148 |
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149 | NET "userio_rfa_led_red" LOC = "AL34" | IOSTANDARD = "LVCMOS25";
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150 | NET "userio_rfa_led_green" LOC = "AK34" | IOSTANDARD = "LVCMOS25";
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151 | NET "userio_rfb_led_red" LOC = "AJ34" | IOSTANDARD = "LVCMOS25";
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152 | NET "userio_rfb_led_green" LOC = "AH34" | IOSTANDARD = "LVCMOS25";
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153 |
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154 |
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155 | # ###################################################################
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156 | # UART Ports
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157 | # ###################################################################
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158 |
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159 | NET "usb_uart_sin" LOC = "J9" | IOSTANDARD = "LVCMOS25";
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160 | NET "usb_uart_sout" LOC = "H9" | IOSTANDARD = "LVCMOS25";
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161 |
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162 |
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163 | # ###################################################################
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164 | # SPI Ports
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165 | # ###################################################################
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166 |
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167 | # RF reference clock SPI
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168 | NET "clk_rfref_spi_sclk" LOC = "V25" | IOSTANDARD = "LVCMOS25";
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169 | NET "clk_rfref_spi_mosi" LOC = "W25" | IOSTANDARD = "LVCMOS25";
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170 | NET "clk_rfref_spi_cs_n" LOC = "W27" | IOSTANDARD = "LVCMOS25";
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171 | NET "clk_rfref_spi_miso" LOC = "Y27" | IOSTANDARD = "LVCMOS25";
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172 | NET "clk_rfref_func" LOC = "L26" | IOSTANDARD = "LVCMOS25";
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173 |
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174 | # Sample clock SPI
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175 | NET "clk_samp_spi_sclk" LOC = "W32" | IOSTANDARD = "LVCMOS25";
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176 | NET "clk_samp_spi_mosi" LOC = "Y29" | IOSTANDARD = "LVCMOS25";
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177 | NET "clk_samp_spi_cs_n" LOC = "W31" | IOSTANDARD = "LVCMOS25";
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178 | NET "clk_samp_spi_miso" LOC = "Y28" | IOSTANDARD = "LVCMOS25";
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179 | NET "clk_samp_func" LOC = "R33" | IOSTANDARD = "LVCMOS25";
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180 |
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181 |
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182 | # ###################################################################
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183 | # I2C (IIC) Ports
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184 | # ###################################################################
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185 |
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186 | # IIC EEPROM
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187 | NET "IIC_EEPROM_iic_sda" LOC = "AG23" | IOSTANDARD = "LVCMOS25";
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188 | NET "IIC_EEPROM_iic_scl" LOC = "AF23" | IOSTANDARD = "LVCMOS25";
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189 |
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190 |
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191 | # ###################################################################
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192 | # Ethernet Ports / Definitions
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193 | # ###################################################################
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194 |
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195 | # Ethernet A Ports
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196 | # NOTE: Ports are for 88e1121R (pg 9 of W3 schematics)
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197 | NET "ETH_A_PD" LOC = "K9" | IOSTANDARD = "LVCMOS25" | TIG;
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198 | NET "ETH_A_RGMII_TXD<0>" LOC = "AF9" | IOSTANDARD = "LVCMOS25";
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199 | NET "ETH_A_RGMII_TXD<1>" LOC = "AF10" | IOSTANDARD = "LVCMOS25";
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200 | NET "ETH_A_RGMII_TXD<2>" LOC = "AD9" | IOSTANDARD = "LVCMOS25";
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201 | NET "ETH_A_RGMII_TXD<3>" LOC = "AD10" | IOSTANDARD = "LVCMOS25";
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202 | NET "ETH_A_RGMII_TX_CTL" LOC = "AG8" | IOSTANDARD = "LVCMOS25";
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203 | NET "ETH_A_RGMII_TXC" LOC = "AE9" | IOSTANDARD = "LVCMOS25";
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204 | NET "ETH_A_RGMII_RXD<0>" LOC = "AK9" | IOSTANDARD = "LVCMOS25";
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205 | NET "ETH_A_RGMII_RXD<1>" LOC = "AJ9" | IOSTANDARD = "LVCMOS25";
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206 | NET "ETH_A_RGMII_RXD<2>" LOC = "AH8" | IOSTANDARD = "LVCMOS25";
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207 | NET "ETH_A_RGMII_RXD<3>" LOC = "AH9" | IOSTANDARD = "LVCMOS25";
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208 | NET "ETH_A_RGMII_RX_CTL" LOC = "AL9" | IOSTANDARD = "LVCMOS25";
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209 | NET "ETH_A_RGMII_RXC" LOC = "AC10" | IOSTANDARD = "LVCMOS25";
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210 | NET "ETH_A_MDC" LOC = "AK8" | IOSTANDARD = "LVCMOS25";
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211 | NET "ETH_A_MDIO" LOC = "AP9" | IOSTANDARD = "LVCMOS25" | PULLUP;
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212 |
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213 | # Ethernet B Ports
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214 | NET "ETH_B_PD" LOC = "E8" | IOSTANDARD = "LVCMOS25" | TIG;
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215 | NET "ETH_B_RGMII_TXD<0>" LOC = "M10" | IOSTANDARD = "LVCMOS25";
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216 | NET "ETH_B_RGMII_TXD<1>" LOC = "B8" | IOSTANDARD = "LVCMOS25";
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217 | NET "ETH_B_RGMII_TXD<2>" LOC = "AC9" | IOSTANDARD = "LVCMOS25";
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218 | NET "ETH_B_RGMII_TXD<3>" LOC = "E9" | IOSTANDARD = "LVCMOS25";
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219 | NET "ETH_B_RGMII_TX_CTL" LOC = "D10" | IOSTANDARD = "LVCMOS25";
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220 | NET "ETH_B_RGMII_TXC" LOC = "AB10" | IOSTANDARD = "LVCMOS25";
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221 | NET "ETH_B_RGMII_RXD<0>" LOC = "A9" | IOSTANDARD = "LVCMOS25";
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222 | NET "ETH_B_RGMII_RXD<1>" LOC = "D9" | IOSTANDARD = "LVCMOS25";
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223 | NET "ETH_B_RGMII_RXD<2>" LOC = "C9" | IOSTANDARD = "LVCMOS25";
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224 | NET "ETH_B_RGMII_RXD<3>" LOC = "F10" | IOSTANDARD = "LVCMOS25";
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225 | NET "ETH_B_RGMII_RX_CTL" LOC = "A8" | IOSTANDARD = "LVCMOS25";
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226 | NET "ETH_B_RGMII_RXC" LOC = "L10" | IOSTANDARD = "LVCMOS25";
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227 | NET "ETH_B_MDC" LOC = "AN9" | IOSTANDARD = "LVCMOS25";
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228 | NET "ETH_B_MDIO" LOC = "AL8" | IOSTANDARD = "LVCMOS25" | PULLUP;
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229 |
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230 | # Common Ethernet Ports
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231 | # NOTE: 88e1121R has a single reset port for both PHYs, so let Ethernet A do it
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232 | NET "ETH_A_PHY_RST_N" LOC = "L9" | IOSTANDARD = "LVCMOS25" | TIG;
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233 | NET "ETH_COMA" LOC = "C8" | IOSTANDARD = "LVCMOS25" | TIG;
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234 |
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235 |
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236 | # ###############################################
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237 | # Ethernet A Timing
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238 | # ###############################################
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239 |
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240 | INST "*ETH_A*gmii_interface*rxdata_bus[0].delay_rgmii_rxd" IDELAY_VALUE = 13;
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241 | INST "*ETH_A*gmii_interface*rxdata_bus[1].delay_rgmii_rxd" IDELAY_VALUE = 13;
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242 | INST "*ETH_A*gmii_interface*rxdata_bus[2].delay_rgmii_rxd" IDELAY_VALUE = 13;
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243 | INST "*ETH_A*gmii_interface*rxdata_bus[3].delay_rgmii_rxd" IDELAY_VALUE = 13;
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244 |
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245 | INST "*ETH_A*gmii_interface*delay_rgmii_rx_ctl" IDELAY_VALUE = 13;
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246 |
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247 | INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk" ODELAY_VALUE = 6;
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248 | INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk" SIGNAL_PATTERN = CLOCK;
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249 |
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250 | # Group all IODELAY-related blocks to use a single IDELAYCTRL
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251 | INST "ETH_A*dlyctrl" IODELAY_GROUP = ETH_rgmii_iodelay;
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252 | INST "*ETH_A*gmii_interface*delay_rgmii_rx_ctl" IODELAY_GROUP = ETH_rgmii_iodelay;
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253 | INST "*ETH_A*gmii_interface*rxdata_bus[?].delay_rgmii_rxd" IODELAY_GROUP = ETH_rgmii_iodelay;
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254 | INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk" IODELAY_GROUP = ETH_rgmii_iodelay;
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255 |
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256 | # Specified Timings: 1.2ns setup time, 1.2ns hold time
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257 | # The internal PHY delays were not used to derive the OFFSET constraints
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258 | # This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock
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259 | # Therefore the offset in constraint must have less setup time than nominal
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260 | NET "ETH_A_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
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261 | NET "ETH_A_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
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262 |
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263 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock
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264 | # Therefore the offset in constraint must have more setup time than nominal
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265 | NET "ETH_A_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
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266 | NET "ETH_A_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
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267 |
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268 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock
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269 | # Therefore the offset in constraint must have more setup time than nominal
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270 | NET "ETH_A_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
|
---|
271 | NET "ETH_A_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
|
---|
272 |
|
---|
273 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock
|
---|
274 | # Therefore the offset in constraint must have more setup time than nominal
|
---|
275 | NET "ETH_A_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
|
---|
276 | NET "ETH_A_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
|
---|
277 |
|
---|
278 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock
|
---|
279 | # Therefore the offset in constraint must have more setup time than nominal
|
---|
280 | NET "ETH_A_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
|
---|
281 | NET "ETH_A_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
|
---|
282 |
|
---|
283 |
|
---|
284 | # ###############################################
|
---|
285 | # Ethernet B Timing
|
---|
286 | # ###############################################
|
---|
287 |
|
---|
288 | INST "*ETH_B*gmii_interface*rxdata_bus[0].delay_rgmii_rxd" IDELAY_VALUE = 13;
|
---|
289 | INST "*ETH_B*gmii_interface*rxdata_bus[1].delay_rgmii_rxd" IDELAY_VALUE = 13;
|
---|
290 | INST "*ETH_B*gmii_interface*rxdata_bus[2].delay_rgmii_rxd" IDELAY_VALUE = 13;
|
---|
291 | INST "*ETH_B*gmii_interface*rxdata_bus[3].delay_rgmii_rxd" IDELAY_VALUE = 13;
|
---|
292 |
|
---|
293 | INST "*ETH_B*gmii_interface*delay_rgmii_rx_ctl" IDELAY_VALUE = 13;
|
---|
294 |
|
---|
295 | INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk" ODELAY_VALUE = 6;
|
---|
296 | INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk" SIGNAL_PATTERN = CLOCK;
|
---|
297 |
|
---|
298 | # Group all IODELAY-related blocks to use a single IDELAYCTRL
|
---|
299 | # INST "ETH_B*dlyctrl" IODELAY_GROUP = ETH_rgmii_iodelay;
|
---|
300 | INST "*ETH_B*gmii_interface*delay_rgmii_rx_ctl" IODELAY_GROUP = ETH_rgmii_iodelay;
|
---|
301 | INST "*ETH_B*gmii_interface*rxdata_bus[?].delay_rgmii_rxd" IODELAY_GROUP = ETH_rgmii_iodelay;
|
---|
302 | INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk" IODELAY_GROUP = ETH_rgmii_iodelay;
|
---|
303 |
|
---|
304 | # Specified Timings: 1.2ns setup time, 1.2ns hold time
|
---|
305 | # The internal PHY delays were not used to derive the OFFSET constraints
|
---|
306 | # This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock
|
---|
307 | # Therefore the offset in constraint must have less setup time than nominal
|
---|
308 | NET "ETH_B_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
|
---|
309 | NET "ETH_B_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
|
---|
310 |
|
---|
311 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock
|
---|
312 | # Therefore the offset in constraint must have more setup time than nominal
|
---|
313 | NET "ETH_B_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
|
---|
314 | NET "ETH_B_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
|
---|
315 |
|
---|
316 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock
|
---|
317 | # Therefore the offset in constraint must have more setup time than nominal
|
---|
318 | NET "ETH_B_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
|
---|
319 | NET "ETH_B_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
|
---|
320 |
|
---|
321 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock
|
---|
322 | # Therefore the offset in constraint must have more setup time than nominal
|
---|
323 | NET "ETH_B_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
|
---|
324 | NET "ETH_B_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
|
---|
325 |
|
---|
326 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock
|
---|
327 | # Therefore the offset in constraint must have more setup time than nominal
|
---|
328 | NET "ETH_B_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
|
---|
329 | NET "ETH_B_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
|
---|
330 |
|
---|
331 |
|
---|
332 | # ###################################################################
|
---|
333 | # FPGA DNA Ports
|
---|
334 | # ###################################################################
|
---|
335 |
|
---|
336 | NET "*fpga_dna*" TIG;
|
---|
337 |
|
---|
338 |
|
---|
339 | # ###################################################################
|
---|
340 | # DDR Ports
|
---|
341 | # ###################################################################
|
---|
342 |
|
---|
343 | # NOTE: DDR3 SO-DIMM constraints are not specified here!
|
---|
344 | # These are pulled automatically from the MIG project during implementation
|
---|
345 |
|
---|
346 | # However, due to a bug in XPS, we need to add this constraint to LOC the IOB
|
---|
347 | NET "ddr_parity" LOC = "AL31" | IOSTANDARD = "LVCMOS25" | TIG; # Stray PAD MIG insists on including
|
---|
348 |
|
---|
349 |
|
---|
350 | # ###################################################################
|
---|
351 | # RFA Ports
|
---|
352 | # ###################################################################
|
---|
353 |
|
---|
354 | # AD9963 SPI
|
---|
355 | NET "RFA_AD_spi_sclk" LOC = "AB33" | IOSTANDARD = "LVCMOS25";
|
---|
356 | NET "RFA_AD_spi_sdio" LOC = "AC30" | IOSTANDARD = "LVCMOS25";
|
---|
357 | NET "RFA_AD_spi_cs_n" LOC = "AB31" | IOSTANDARD = "LVCMOS25";
|
---|
358 | NET "RFA_AD_reset_n" LOC = "AA34" | IOSTANDARD = "LVCMOS25";
|
---|
359 |
|
---|
360 | # AD9963
|
---|
361 | NET "RFA_AD_TRXD<0>" LOC = "AC25" | IOSTANDARD = "LVCMOS25";
|
---|
362 | NET "RFA_AD_TRXD<1>" LOC = "AB25" | IOSTANDARD = "LVCMOS25";
|
---|
363 | NET "RFA_AD_TRXD<2>" LOC = "AB32" | IOSTANDARD = "LVCMOS25";
|
---|
364 | NET "RFA_AD_TRXD<3>" LOC = "AC29" | IOSTANDARD = "LVCMOS25";
|
---|
365 | NET "RFA_AD_TRXD<4>" LOC = "AD29" | IOSTANDARD = "LVCMOS25";
|
---|
366 | NET "RFA_AD_TRXD<5>" LOC = "AC33" | IOSTANDARD = "LVCMOS25";
|
---|
367 | NET "RFA_AD_TRXD<6>" LOC = "AD34" | IOSTANDARD = "LVCMOS25";
|
---|
368 | NET "RFA_AD_TRXD<7>" LOC = "AC32" | IOSTANDARD = "LVCMOS25";
|
---|
369 | NET "RFA_AD_TRXD<8>" LOC = "AD31" | IOSTANDARD = "LVCMOS25";
|
---|
370 | NET "RFA_AD_TRXD<9>" LOC = "AD32" | IOSTANDARD = "LVCMOS25";
|
---|
371 | NET "RFA_AD_TRXD<10>" LOC = "AE31" | IOSTANDARD = "LVCMOS25";
|
---|
372 | NET "RFA_AD_TRXD<11>" LOC = "AE32" | IOSTANDARD = "LVCMOS25";
|
---|
373 |
|
---|
374 | NET "RFA_AD_TRXCLK" LOC = "AD30" | IOSTANDARD = "LVCMOS25";
|
---|
375 | NET "RFA_AD_TRXIQ" LOC = "AC34" | IOSTANDARD = "LVCMOS25";
|
---|
376 |
|
---|
377 | NET "RFA_AD_TXCLK" LOC = "AA31" | IOSTANDARD = "LVCMOS25";
|
---|
378 | NET "RFA_AD_TXIQ" LOC = "AA33" | IOSTANDARD = "LVCMOS25";
|
---|
379 |
|
---|
380 | NET "RFA_AD_TXD<0>" LOC = "AA25" | IOSTANDARD = "LVCMOS25";
|
---|
381 | NET "RFA_AD_TXD<1>" LOC = "AB26" | IOSTANDARD = "LVCMOS25";
|
---|
382 | NET "RFA_AD_TXD<2>" LOC = "Y26" | IOSTANDARD = "LVCMOS25";
|
---|
383 | NET "RFA_AD_TXD<3>" LOC = "AA26" | IOSTANDARD = "LVCMOS25";
|
---|
384 | NET "RFA_AD_TXD<4>" LOC = "AA28" | IOSTANDARD = "LVCMOS25";
|
---|
385 | NET "RFA_AD_TXD<5>" LOC = "AA29" | IOSTANDARD = "LVCMOS25";
|
---|
386 | NET "RFA_AD_TXD<6>" LOC = "AA30" | IOSTANDARD = "LVCMOS25";
|
---|
387 | NET "RFA_AD_TXD<7>" LOC = "AB30" | IOSTANDARD = "LVCMOS25";
|
---|
388 | NET "RFA_AD_TXD<8>" LOC = "AB28" | IOSTANDARD = "LVCMOS25";
|
---|
389 | NET "RFA_AD_TXD<9>" LOC = "AB27" | IOSTANDARD = "LVCMOS25";
|
---|
390 | NET "RFA_AD_TXD<10>" LOC = "AC28" | IOSTANDARD = "LVCMOS25";
|
---|
391 | NET "RFA_AD_TXD<11>" LOC = "AC27" | IOSTANDARD = "LVCMOS25";
|
---|
392 |
|
---|
393 |
|
---|
394 | # TRXCLK pins driven by AD9963's; assuming 80MHz worst case
|
---|
395 | NET "RFA_AD_TRXCLK" TNM_NET = "RFA_AD_TRXCLK";
|
---|
396 | TIMESPEC "TS_RFA_AD_TRXCLK" = PERIOD "RFA_AD_TRXCLK" 80 MHz;
|
---|
397 |
|
---|
398 |
|
---|
399 | # Define relationship of TRXD and TRXCLK, based on AD9963 specs
|
---|
400 | # Using worst-case output delay from AD9963 datasheet table 23
|
---|
401 | # TRXCLK leads TRXD transition by t_OD2; ad_bridge uses IDELAY to shift this to mid valid window
|
---|
402 | # VALID window below assumes DDR interleaved I/Q at 40MSps rate (12.5nsec / half sample)
|
---|
403 | INST "RFA_AD_TRXD<*>" TNM = "RFA_AD_TRXD_group";
|
---|
404 |
|
---|
405 | NET "RFA_AD_TRXCLK" TNM_NET = "RFA_AD_TRXCLK";
|
---|
406 | TIMEGRP "RFA_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 10 ns BEFORE "RFA_AD_TRXCLK" RISING;
|
---|
407 | TIMEGRP "RFA_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 10 ns BEFORE "RFA_AD_TRXCLK" FALLING;
|
---|
408 |
|
---|
409 |
|
---|
410 | # MAX2829 transceivers and RF front end
|
---|
411 | NET "RFA_SPI_SCLK" LOC = "T34" | IOSTANDARD = "LVCMOS25";
|
---|
412 | NET "RFA_SPI_MOSI" LOC = "T33" | IOSTANDARD = "LVCMOS25";
|
---|
413 | NET "RFA_SPI_CSn" LOC = "U32" | IOSTANDARD = "LVCMOS25";
|
---|
414 |
|
---|
415 | NET "RFA_SHDN" LOC = "U27" | IOSTANDARD = "LVCMOS25";
|
---|
416 | NET "RFA_TxEn" LOC = "T31" | IOSTANDARD = "LVCMOS25";
|
---|
417 | NET "RFA_RxEn" LOC = "U33" | IOSTANDARD = "LVCMOS25";
|
---|
418 | NET "RFA_RxHP" LOC = "AG32" | IOSTANDARD = "LVCMOS25";
|
---|
419 | NET "RFA_PAEn_24" LOC = "U25" | IOSTANDARD = "LVCMOS25";
|
---|
420 | NET "RFA_PAEn_5" LOC = "U28" | IOSTANDARD = "LVCMOS25";
|
---|
421 | NET "RFA_ANTSW<0>" LOC = "U31" | IOSTANDARD = "LVCMOS25";
|
---|
422 | NET "RFA_ANTSW<1>" LOC = "U30" | IOSTANDARD = "LVCMOS25";
|
---|
423 | NET "RFA_LD" LOC = "U26" | IOSTANDARD = "LVCMOS25";
|
---|
424 |
|
---|
425 | NET "RFA_B<0>" LOC = "AG33" | IOSTANDARD = "LVCMOS25";
|
---|
426 | NET "RFA_B<1>" LOC = "AF31" | IOSTANDARD = "LVCMOS25";
|
---|
427 | NET "RFA_B<2>" LOC = "AF33" | IOSTANDARD = "LVCMOS25";
|
---|
428 | NET "RFA_B<3>" LOC = "AG31" | IOSTANDARD = "LVCMOS25";
|
---|
429 | NET "RFA_B<4>" LOC = "AF34" | IOSTANDARD = "LVCMOS25";
|
---|
430 | NET "RFA_B<5>" LOC = "AE33" | IOSTANDARD = "LVCMOS25";
|
---|
431 | NET "RFA_B<6>" LOC = "AE34" | IOSTANDARD = "LVCMOS25";
|
---|
432 |
|
---|
433 |
|
---|
434 | # ###################################################################
|
---|
435 | # RFB Ports
|
---|
436 | # ###################################################################
|
---|
437 |
|
---|
438 | # AD9963 SPI
|
---|
439 | NET "RFB_AD_spi_sclk" LOC = "P32" | IOSTANDARD = "LVCMOS25";
|
---|
440 | NET "RFB_AD_spi_sdio" LOC = "P34" | IOSTANDARD = "LVCMOS25";
|
---|
441 | NET "RFB_AD_spi_cs_n" LOC = "N32" | IOSTANDARD = "LVCMOS25";
|
---|
442 | NET "RFB_AD_reset_n" LOC = "N34" | IOSTANDARD = "LVCMOS25";
|
---|
443 |
|
---|
444 | # AD9963
|
---|
445 | NET "RFB_AD_TRXD<0>" LOC = "N25" | IOSTANDARD = "LVCMOS25";
|
---|
446 | NET "RFB_AD_TRXD<1>" LOC = "M25" | IOSTANDARD = "LVCMOS25";
|
---|
447 | NET "RFB_AD_TRXD<2>" LOC = "N28" | IOSTANDARD = "LVCMOS25";
|
---|
448 | NET "RFB_AD_TRXD<3>" LOC = "N27" | IOSTANDARD = "LVCMOS25";
|
---|
449 | NET "RFB_AD_TRXD<4>" LOC = "P29" | IOSTANDARD = "LVCMOS25";
|
---|
450 | NET "RFB_AD_TRXD<5>" LOC = "M30" | IOSTANDARD = "LVCMOS25";
|
---|
451 | NET "RFB_AD_TRXD<6>" LOC = "N30" | IOSTANDARD = "LVCMOS25";
|
---|
452 | NET "RFB_AD_TRXD<7>" LOC = "N29" | IOSTANDARD = "LVCMOS25";
|
---|
453 | NET "RFB_AD_TRXD<8>" LOC = "P26" | IOSTANDARD = "LVCMOS25";
|
---|
454 | NET "RFB_AD_TRXD<9>" LOC = "P31" | IOSTANDARD = "LVCMOS25";
|
---|
455 | NET "RFB_AD_TRXD<10>" LOC = "P25" | IOSTANDARD = "LVCMOS25";
|
---|
456 | NET "RFB_AD_TRXD<11>" LOC = "P30" | IOSTANDARD = "LVCMOS25";
|
---|
457 |
|
---|
458 | NET "RFB_AD_TRXCLK" LOC = "N33" | IOSTANDARD = "LVCMOS25";
|
---|
459 | NET "RFB_AD_TRXIQ" LOC = "M33" | IOSTANDARD = "LVCMOS25";
|
---|
460 |
|
---|
461 | NET "RFB_AD_TXCLK" LOC = "L28" | IOSTANDARD = "LVCMOS25";
|
---|
462 | NET "RFB_AD_TXIQ" LOC = "L29" | IOSTANDARD = "LVCMOS25";
|
---|
463 |
|
---|
464 | NET "RFB_AD_TXD<0>" LOC = "K32" | IOSTANDARD = "LVCMOS25";
|
---|
465 | NET "RFB_AD_TXD<1>" LOC = "M26" | IOSTANDARD = "LVCMOS25";
|
---|
466 | NET "RFB_AD_TXD<2>" LOC = "M32" | IOSTANDARD = "LVCMOS25";
|
---|
467 | NET "RFB_AD_TXD<3>" LOC = "K34" | IOSTANDARD = "LVCMOS25";
|
---|
468 | NET "RFB_AD_TXD<4>" LOC = "M31" | IOSTANDARD = "LVCMOS25";
|
---|
469 | NET "RFB_AD_TXD<5>" LOC = "L30" | IOSTANDARD = "LVCMOS25";
|
---|
470 | NET "RFB_AD_TXD<6>" LOC = "L33" | IOSTANDARD = "LVCMOS25";
|
---|
471 | NET "RFB_AD_TXD<7>" LOC = "L31" | IOSTANDARD = "LVCMOS25";
|
---|
472 | NET "RFB_AD_TXD<8>" LOC = "M28" | IOSTANDARD = "LVCMOS25";
|
---|
473 | NET "RFB_AD_TXD<9>" LOC = "L34" | IOSTANDARD = "LVCMOS25";
|
---|
474 | NET "RFB_AD_TXD<10>" LOC = "M27" | IOSTANDARD = "LVCMOS25";
|
---|
475 | NET "RFB_AD_TXD<11>" LOC = "K31" | IOSTANDARD = "LVCMOS25";
|
---|
476 |
|
---|
477 |
|
---|
478 | # TRXCLK pins driven by AD9963's; assuming 80MHz worst case
|
---|
479 | NET "RFB_AD_TRXCLK" TNM_NET = "RFB_AD_TRXCLK";
|
---|
480 | TIMESPEC "TS_RFB_AD_TRXCLK" = PERIOD "RFB_AD_TRXCLK" 80 MHz;
|
---|
481 |
|
---|
482 |
|
---|
483 | # Define relationship of TRXD and TRXCLK, based on AD9963 specs
|
---|
484 | # Using worst-case output delay from AD9963 datasheet table 23
|
---|
485 | # TRXCLK leads TRXD transition by t_OD2; ad_bridge uses IDELAY to shift this to mid valid window
|
---|
486 | # VALID window below assumes DDR interleaved I/Q at 40MSps rate (12.5nsec / half sample)
|
---|
487 | INST "RFB_AD_TRXD<*>" TNM = "RFB_AD_TRXD_group";
|
---|
488 |
|
---|
489 | NET "RFB_AD_TRXCLK" TNM_NET = "RFB_AD_TRXCLK";
|
---|
490 | TIMEGRP "RFB_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 10 ns BEFORE "RFB_AD_TRXCLK" RISING;
|
---|
491 | TIMEGRP "RFB_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 10 ns BEFORE "RFB_AD_TRXCLK" FALLING;
|
---|
492 |
|
---|
493 |
|
---|
494 | # MAX2829 transceivers and RF front end
|
---|
495 | NET "RFB_SPI_SCLK" LOC = "H34" | IOSTANDARD = "LVCMOS25";
|
---|
496 | NET "RFB_SPI_MOSI" LOC = "H33" | IOSTANDARD = "LVCMOS25";
|
---|
497 | NET "RFB_SPI_CSn" LOC = "J32" | IOSTANDARD = "LVCMOS25";
|
---|
498 |
|
---|
499 | NET "RFB_SHDN" LOC = "J34" | IOSTANDARD = "LVCMOS25";
|
---|
500 | NET "RFB_TxEn" LOC = "H32" | IOSTANDARD = "LVCMOS25";
|
---|
501 | NET "RFB_RxEn" LOC = "J31" | IOSTANDARD = "LVCMOS25";
|
---|
502 | NET "RFB_RxHP" LOC = "R28" | IOSTANDARD = "LVCMOS25";
|
---|
503 | NET "RFB_PAEn_24" LOC = "T25" | IOSTANDARD = "LVCMOS25";
|
---|
504 | NET "RFB_PAEn_5" LOC = "T28" | IOSTANDARD = "LVCMOS25";
|
---|
505 | NET "RFB_ANTSW<0>" LOC = "T30" | IOSTANDARD = "LVCMOS25";
|
---|
506 | NET "RFB_ANTSW<1>" LOC = "T29" | IOSTANDARD = "LVCMOS25";
|
---|
507 | NET "RFB_LD" LOC = "K33" | IOSTANDARD = "LVCMOS25";
|
---|
508 |
|
---|
509 | NET "RFB_B<0>" LOC = "P27" | IOSTANDARD = "LVCMOS25";
|
---|
510 | NET "RFB_B<1>" LOC = "R27" | IOSTANDARD = "LVCMOS25";
|
---|
511 | NET "RFB_B<2>" LOC = "R29" | IOSTANDARD = "LVCMOS25";
|
---|
512 | NET "RFB_B<3>" LOC = "R26" | IOSTANDARD = "LVCMOS25";
|
---|
513 | NET "RFB_B<4>" LOC = "R32" | IOSTANDARD = "LVCMOS25";
|
---|
514 | NET "RFB_B<5>" LOC = "T26" | IOSTANDARD = "LVCMOS25";
|
---|
515 | NET "RFB_B<6>" LOC = "R31" | IOSTANDARD = "LVCMOS25";
|
---|
516 |
|
---|
517 |
|
---|
518 | # ###################################################################
|
---|
519 | # RFA / RFB RSSI Ports
|
---|
520 | # ###################################################################
|
---|
521 |
|
---|
522 | NET "RF_RSSI_CLK" LOC = "B32" | IOSTANDARD = "LVCMOS25";
|
---|
523 | NET "RF_RSSI_PD" LOC = "B34" | IOSTANDARD = "LVCMOS25";
|
---|
524 |
|
---|
525 | NET "RFA_RSSI_D<0>" LOC = "E32" | IOSTANDARD = "LVCMOS25";
|
---|
526 | NET "RFA_RSSI_D<1>" LOC = "E33" | IOSTANDARD = "LVCMOS25";
|
---|
527 | NET "RFA_RSSI_D<2>" LOC = "E34" | IOSTANDARD = "LVCMOS25";
|
---|
528 | NET "RFA_RSSI_D<3>" LOC = "F30" | IOSTANDARD = "LVCMOS25";
|
---|
529 | NET "RFA_RSSI_D<4>" LOC = "F31" | IOSTANDARD = "LVCMOS25";
|
---|
530 | NET "RFA_RSSI_D<5>" LOC = "F34" | IOSTANDARD = "LVCMOS25";
|
---|
531 | NET "RFA_RSSI_D<6>" LOC = "F33" | IOSTANDARD = "LVCMOS25";
|
---|
532 | NET "RFA_RSSI_D<7>" LOC = "G31" | IOSTANDARD = "LVCMOS25";
|
---|
533 | NET "RFA_RSSI_D<8>" LOC = "G33" | IOSTANDARD = "LVCMOS25";
|
---|
534 | NET "RFA_RSSI_D<9>" LOC = "G32" | IOSTANDARD = "LVCMOS25";
|
---|
535 |
|
---|
536 | NET "RFB_RSSI_D<0>" LOC = "A33" | IOSTANDARD = "LVCMOS25";
|
---|
537 | NET "RFB_RSSI_D<1>" LOC = "B33" | IOSTANDARD = "LVCMOS25";
|
---|
538 | NET "RFB_RSSI_D<2>" LOC = "C33" | IOSTANDARD = "LVCMOS25";
|
---|
539 | NET "RFB_RSSI_D<3>" LOC = "C34" | IOSTANDARD = "LVCMOS25";
|
---|
540 | NET "RFB_RSSI_D<4>" LOC = "C32" | IOSTANDARD = "LVCMOS25";
|
---|
541 | NET "RFB_RSSI_D<5>" LOC = "D31" | IOSTANDARD = "LVCMOS25";
|
---|
542 | NET "RFB_RSSI_D<6>" LOC = "G30" | IOSTANDARD = "LVCMOS25";
|
---|
543 | NET "RFB_RSSI_D<7>" LOC = "E31" | IOSTANDARD = "LVCMOS25";
|
---|
544 | NET "RFB_RSSI_D<8>" LOC = "D32" | IOSTANDARD = "LVCMOS25";
|
---|
545 | NET "RFB_RSSI_D<9>" LOC = "D34" | IOSTANDARD = "LVCMOS25";
|
---|
546 |
|
---|
547 |
|
---|
548 | # ###################################################################
|
---|
549 | # Floor planning Information
|
---|
550 | # ###################################################################
|
---|
551 |
|
---|
552 | INST "microblaze_0_ilmb" AREA_GROUP = "MB_Subsystem";
|
---|
553 | INST "microblaze_0_dlmb" AREA_GROUP = "MB_Subsystem";
|
---|
554 | INST "microblaze_0" AREA_GROUP = "MB_Subsystem";
|
---|
555 | INST "microblaze_0_i_bram_ctrl" AREA_GROUP = "MB_Subsystem";
|
---|
556 | INST "microblaze_0_d_bram_ctrl" AREA_GROUP = "MB_Subsystem";
|
---|
557 | INST "microblaze_0_bram_block" AREA_GROUP = "MB_Subsystem";
|
---|
558 | AREA_GROUP "MB_Subsystem" RANGE = SLICE_X84Y140:SLICE_X147Y198;
|
---|
559 |
|
---|
560 | INST "rfa_iq_rx_buffer_ctrl" AREA_GROUP = "IQ_Buffers_AB";
|
---|
561 | INST "rfa_iq_rx_buffer" AREA_GROUP = "IQ_Buffers_AB";
|
---|
562 | INST "rfa_iq_tx_buffer_ctrl" AREA_GROUP = "IQ_Buffers_AB";
|
---|
563 | INST "rfa_iq_tx_buffer" AREA_GROUP = "IQ_Buffers_AB";
|
---|
564 | INST "rfb_iq_rx_buffer_ctrl" AREA_GROUP = "IQ_Buffers_AB";
|
---|
565 | INST "rfb_iq_rx_buffer" AREA_GROUP = "IQ_Buffers_AB";
|
---|
566 | INST "rfb_iq_tx_buffer_ctrl" AREA_GROUP = "IQ_Buffers_AB";
|
---|
567 | INST "rfb_iq_tx_buffer" AREA_GROUP = "IQ_Buffers_AB";
|
---|
568 | INST "axi_interconnect_buffers" AREA_GROUP = "IQ_Buffers_AB";
|
---|
569 |
|
---|
570 | INST "axi_interconnect_core" AREA_GROUP = "Interconnect_core";
|
---|
571 |
|
---|
572 | INST "axi_interconnect_dma" AREA_GROUP = "ETH_Subsystem";
|
---|
573 | INST "ETH_A_MAC" AREA_GROUP = "ETH_Subsystem";
|
---|
574 | INST "ETH_A_DMA" AREA_GROUP = "ETH_Subsystem";
|
---|
575 | INST "ETH_B_MAC" AREA_GROUP = "ETH_Subsystem";
|
---|
576 | INST "ETH_B_DMA" AREA_GROUP = "ETH_Subsystem";
|
---|
577 |
|
---|
578 | INST "axi_cdma_0" AREA_GROUP = "CDMA";
|
---|
579 |
|
---|
580 | INST "warplab_buffers" AREA_GROUP = "WL_BUFFERS";
|
---|
581 |
|
---|
582 | INST "warplab_agc" AREA_GROUP = "WL_AGC";
|
---|
583 |
|
---|
584 | INST "warplab_trigger_proc" AREA_GROUP = "WL_TRIGGER_PROC";
|
---|
585 |
|
---|
586 | INST "w3_clock_controller_0" AREA_GROUP = "CLK_CONTROLLER";
|
---|
587 | AREA_GROUP "CLK_CONTROLLER" RANGE = RAMB36_X0Y17:RAMB36_X3Y23;
|
---|
588 |
|
---|
589 | INST "DDR3_SODIMM" AREA_GROUP = "DDR3_SODIMM";
|
---|
590 | AREA_GROUP "DDR3_SODIMM" RANGE = SLICE_X52Y40:SLICE_X103Y80, SLICE_X0Y0:SLICE_X143Y39;
|
---|
591 |
|
---|