| 1 | //Register write macros |
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| 2 | //4x4 |
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| 3 | #define warplab_mimo_WriteReg_TxDelay(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXDELAY, data) |
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| 4 | #define warplab_mimo_WriteReg_RADIO1RXBUFF_RXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO1RXBUFF_RXEN, data) |
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| 5 | #define warplab_mimo_WriteReg_RADIO1TXBUFF_TXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO1TXBUFF_TXEN, data) |
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| 6 | #define warplab_mimo_WriteReg_RADIO2RXBUFF_RXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO2RXBUFF_RXEN, data) |
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| 7 | #define warplab_mimo_WriteReg_RADIO2TXBUFF_TXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO2TXBUFF_TXEN, data) |
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| 8 | #define warplab_mimo_WriteReg_RADIO3RXBUFF_RXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO3RXBUFF_RXEN, data) |
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| 9 | #define warplab_mimo_WriteReg_RADIO3TXBUFF_TXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO3TXBUFF_TXEN, data) |
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| 10 | #define warplab_mimo_WriteReg_RADIO4RXBUFF_RXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO4RXBUFF_RXEN, data) |
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| 11 | #define warplab_mimo_WriteReg_RADIO4TXBUFF_TXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO4TXBUFF_TXEN, data) |
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| 12 | #define warplab_mimo_WriteReg_StartCapture(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_STARTCAPTURE, data) |
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| 13 | #define warplab_mimo_WriteReg_StartTx(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_STARTTX, data) |
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| 14 | #define warplab_mimo_WriteReg_StopTx(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_STOPTX, data) |
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| 15 | #define warplab_mimo_WriteReg_StartTxRx(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_STARTTXRX, data) |
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| 16 | #define warplab_mimo_WriteReg_TransMode(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TRANSMODE, data) |
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| 17 | #define warplab_mimo_WriteReg_TxLength(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXLENGTH, data) |
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| 18 | #define warplab_mimo_WriteReg_DebugRx1Buffers(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX1BUFFERS, data) |
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| 19 | #define warplab_mimo_WriteReg_DebugRx2Buffers(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX2BUFFERS, data) |
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| 20 | #define warplab_mimo_WriteReg_DebugRx3Buffers(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX3BUFFERS, data) |
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| 21 | #define warplab_mimo_WriteReg_DebugRx4Buffers(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX4BUFFERS, data) |
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| 22 | #define warplab_mimo_WriteReg_MGC_AGC_SEL(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_MGC_AGC_SEL, data) |
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| 23 | #define warplab_mimo_WriteReg_DCO_EN_SEL(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DCO_EN_SEL, data) |
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| 25 | //4x4AGC |
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| 26 | #define warplab_AGC_WriteReg_SRESET_IN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_SRESET_IN, data) |
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| 27 | #define warplab_AGC_WriteReg_MRESET_IN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_MRESET_IN, data) |
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| 28 | #define warplab_AGC_WriteReg_PACKET_IN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_PACKET_IN, data) |
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| 29 | #define warplab_AGC_WriteReg_T_dB(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_T_DB, data) |
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| 30 | #define warplab_AGC_WriteReg_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_AGC_EN, data) |
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| 31 | #define warplab_AGC_WriteReg_AVG_LEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_AVG_LEN, data) |
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| 32 | #define warplab_AGC_WriteReg_Timing(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_TIMING, data) |
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| 33 | #define warplab_AGC_WriteReg_Thresholds(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_THRESHOLDS, data) |
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| 34 | #define warplab_AGC_WriteReg_ADJ(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_ADJ, data) |
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| 35 | #define warplab_AGC_WriteReg_GBB_init(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_INIT, data) |
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| 36 | #define warplab_AGC_WriteReg_RADIO1_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_RADIO1_AGC_EN, data) |
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| 37 | #define warplab_AGC_WriteReg_RADIO2_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_RADIO2_AGC_EN, data) |
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| 38 | #define warplab_AGC_WriteReg_RADIO3_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_RADIO3_AGC_EN, data) |
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| 39 | #define warplab_AGC_WriteReg_RADIO4_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_RADIO4_AGC_EN, data) |
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| 40 | #define warplab_AGC_WriteReg_AGC_TRIGGER_DELAY(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_AGC_TRIGGER_DELAY, data); |
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| 41 | #define warplab_AGC_WriteReg_DCO_Timing(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_DCO_TIMING, data); |
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| 42 | #define warplab_AGC_WriteReg_Bits(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_BITS, data); |
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| 43 | |
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| 44 | |
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| 45 | //Register read macros |
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| 46 | //4x4 |
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| 47 | #define warplab_mimo_ReadReg_TxDelay(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXDELAY) |
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| 48 | #define warplab_mimo_ReadReg_CaptOffset(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_CAPTOFFSET) |
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| 49 | #define warplab_mimo_ReadReg_CaptureDone(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_CAPTUREDONE) |
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| 50 | #define warplab_mimo_ReadReg_TransMode(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TRANSMODE) |
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| 51 | #define warplab_mimo_ReadReg_TxLength(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXLENGTH) |
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| 52 | #define warplab_mimo_ReadReg_DebugRx1Buffers(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX1BUFFERS) |
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| 53 | #define warplab_mimo_ReadReg_DebugRx2Buffers(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX2BUFFERS) |
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| 54 | #define warplab_mimo_ReadReg_DebugRx3Buffers(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX3BUFFERS) |
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| 55 | #define warplab_mimo_ReadReg_DebugRx4Buffers(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX4BUFFERS) |
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| 56 | #define warplab_mimo_ReadReg_MGC_AGC_SEL(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_MGC_AGC_SEL) |
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| 57 | #define warplab_mimo_ReadReg_DCO_EN_SEL(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DCO_EN_SEL) |
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| 58 | #define warplab_mimo_ReadReg_AGCDoneAddr(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_AGCDONEADDR) |
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| 59 | #define warplab_mimo_ReadReg_Radio1AGCDoneRSSI(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO1AGCDONERSSI) |
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| 60 | #define warplab_mimo_ReadReg_Radio2AGCDoneRSSI(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO2AGCDONERSSI) |
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| 61 | #define warplab_mimo_ReadReg_Radio3AGCDoneRSSI(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO3AGCDONERSSI) |
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| 62 | #define warplab_mimo_ReadReg_Radio4AGCDoneRSSI(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO4AGCDONERSSI) |
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| 64 | |
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| 65 | //4x4 AGC |
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| 66 | #define warplab_AGC_ReadReg_GBB_A(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_A) |
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| 67 | #define warplab_AGC_ReadReg_GBB_B(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_B) |
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| 68 | #define warplab_AGC_ReadReg_GBB_C(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_C) |
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| 69 | #define warplab_AGC_ReadReg_GBB_D(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_D) |
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| 70 | #define warplab_AGC_ReadReg_GRF_A(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GRF_A) |
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| 71 | #define warplab_AGC_ReadReg_GRF_B(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GRF_B) |
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| 72 | #define warplab_AGC_ReadReg_GRF_C(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GRF_C) |
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| 73 | #define warplab_AGC_ReadReg_GRF_D(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GRF_D) |
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| 74 | #define warplab_AGC_ReadReg_Thresholds(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_THRESHOLDS) |
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| 75 | #define warplab_AGC_ReadReg_Bits(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_BITS) |
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