source: ResearchApps/PHY/WARPLAB/WARPLab_v05_2/EDK_Files_MIMO_2x2_FPGAv2/system.ucf

############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=AN20;
Net sys_clk_pin IOSTANDARD = LVTTL;
Net sys_rst_pin LOC=M21;
Net sys_rst_pin IOSTANDARD = LVCMOS25;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 ps;
Net sys_rst_pin TIG;
NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;

## IO Devices constraints
#Debug header LOC constraints (manually entered)
NET "debug<0>" LOC = "L20" | IOSTANDARD = LVTTL; #pin 0
NET "debug<1>" LOC = "J21" | IOSTANDARD = LVTTL; #pin 1
NET "debug<2>" LOC = "G20" | IOSTANDARD = LVTTL; #pin 2
NET "debug<3>" LOC = "J20" | IOSTANDARD = LVTTL; #pin 3
NET "debug<4>" LOC = "K21" | IOSTANDARD = LVTTL; #pin 4
NET "debug<5>" LOC = "F20" | IOSTANDARD = LVTTL; #pin 5
NET "debug<6>" LOC = "H20" | IOSTANDARD = LVTTL; #pin 6
NET "debug<7>" LOC = "L21" | IOSTANDARD = LVTTL; #pin 7
NET "debug<8>" LOC = "H18" | IOSTANDARD = LVTTL; #pin 8
NET "debug<9>" LOC = "H19" | IOSTANDARD = LVTTL; #pin 9
NET "debug<10>" LOC = "K19" | IOSTANDARD = LVTTL; #pin 10
NET "debug<11>" LOC = "G18" | IOSTANDARD = LVTTL; #pin 11
NET "debug<12>" LOC = "F19" | IOSTANDARD = LVTTL; #pin 12
NET "debug<13>" LOC = "L19" | IOSTANDARD = LVTTL; #pin 13
NET "debug<14>" LOC = "J19" | IOSTANDARD = LVTTL; #pin 14
NET "debug<15>" LOC = "F18" | IOSTANDARD = LVTTL; #pin 15

#### Module Ethernet_MAC constraints

Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=H24;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=G17;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=C17;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=G15;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=K17;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=E17;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=D17;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=C18;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=G22;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=F23;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=J22;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=H23;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=K23;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=E21;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=E22;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=H22;

Net fpga_0_Ethernet_MAC_PHY_rst_n_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVCMOS25;

#### Module warp_v4_userio_all constraints

Net fpga_0_warp_v4_userio_all_LEDs_out_pin<0> LOC=N24;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<1> LOC=N20;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<2> LOC=L18;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<3> LOC=N18;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<4> LOC=M18;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<5> LOC=M25;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<5> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<6> LOC=N19;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<6> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<7> LOC=P19;
Net fpga_0_warp_v4_userio_all_LEDs_out_pin<7> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<0> LOC=M17;
Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<1> LOC=R18;
Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<2> LOC=P17;
Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<3> LOC=M16;
Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_PB_in_pin<0> LOC=N23;
Net fpga_0_warp_v4_userio_all_PB_in_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_PB_in_pin<1> LOC=N22;
Net fpga_0_warp_v4_userio_all_PB_in_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_PB_in_pin<2> LOC=M23;
Net fpga_0_warp_v4_userio_all_PB_in_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_PB_in_pin<3> LOC=L23;
Net fpga_0_warp_v4_userio_all_PB_in_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_warp_v4_userio_all_IOEx_SCL_pin LOC=AK17;
Net fpga_0_warp_v4_userio_all_IOEx_SCL_pin IOSTANDARD = LVTTL;
Net fpga_0_warp_v4_userio_all_IOEx_SDA_pin LOC=AL18;
Net fpga_0_warp_v4_userio_all_IOEx_SDA_pin IOSTANDARD = LVTTL;

#### Module rs232_db9 constraints

Net fpga_0_rs232_db9_RX_pin LOC=L24;
Net fpga_0_rs232_db9_RX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_rs232_db9_TX_pin LOC=K24;
Net fpga_0_rs232_db9_TX_pin IOSTANDARD = LVCMOS25;

#### Module clk_board_config constraints

Net fpga_0_clk_board_config_sys_clk_pin LOC=AM21;
Net fpga_0_clk_board_config_sys_clk_pin IOSTANDARD = LVTTL;
Net fpga_0_clk_board_config_cfg_radio_dat_out_pin LOC=AN19;
Net fpga_0_clk_board_config_cfg_radio_dat_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_radio_dat_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_csb_out_pin LOC=AP19;
Net fpga_0_clk_board_config_cfg_radio_csb_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_radio_csb_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_en_out_pin LOC=AR19;
Net fpga_0_clk_board_config_cfg_radio_en_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_radio_en_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_clk_out_pin LOC=AM20;
Net fpga_0_clk_board_config_cfg_radio_clk_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_radio_clk_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_dat_out_pin LOC=AR21;
Net fpga_0_clk_board_config_cfg_logic_dat_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_logic_dat_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_csb_out_pin LOC=AL21;
Net fpga_0_clk_board_config_cfg_logic_csb_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_logic_csb_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_en_out_pin LOC=AK21;
Net fpga_0_clk_board_config_cfg_logic_en_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_logic_en_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_clk_out_pin LOC=AN22;
Net fpga_0_clk_board_config_cfg_logic_clk_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_logic_clk_out_pin SLEW = SLOW;

#### Module radio_controller_0 constraints



#### Module radio_bridge_slot_2 constraints

Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin LOC=AD5;
Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> LOC=AA4;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> LOC=AH5;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> LOC=Y4;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> LOC=V17;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> LOC=AC3;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> LOC=Y6;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> LOC=AH4;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> LOC=V14;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> LOC=U15;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> LOC=W6;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> LOC=AG18;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> LOC=V15;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> LOC=V5;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> LOC=AA10;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> LOC=Y11;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> LOC=AA9;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> LOC=V7;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> LOC=U6;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> LOC=AB11;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> LOC=W4;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> LOC=V12;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> LOC=AB7;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> LOC=AE7;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> LOC=AC7;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> LOC=AC5;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> LOC=AE4;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> LOC=AD4;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> LOC=AD7;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> LOC=AD6;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> LOC=W14;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> LOC=U5;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> LOC=W5;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> LOC=AA11;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> LOC=W9;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> LOC=Y12;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> LOC=AP4;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> LOC=AR3;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> LOC=AT4;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> LOC=AR4;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> LOC=AT5;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> LOC=AN3;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> LOC=AT3;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> LOC=AU5;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> LOC=AM7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> LOC=AU6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> LOC=AP5;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> LOC=AN5;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> LOC=AT6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> LOC=AM6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> LOC=AL6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> LOC=AL8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> LOC=AF8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> LOC=AF9;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> LOC=AH8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> LOC=AG7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> LOC=AJ6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> LOC=AN4;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> LOC=AG8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> LOC=AM5;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> LOC=AJ5;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> LOC=AK6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> LOC=AH7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> LOC=AJ4;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> LOC=AL4;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> LOC=AB15;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> LOC=AC14;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> LOC=AK4;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin LOC=AC9;
Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin LOC=AK8;
Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin LOC=AK7;
Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin LOC=AB12;
Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin LOC=AG3;
Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin LOC=AE8;
Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin LOC=AB3;
Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin LOC=W16;
Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin LOC=AB10;
Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin LOC=AC4;
Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_24PA_pin LOC=W7;
Net fpga_0_radio_bridge_slot_2_radio_24PA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_5PA_pin LOC=AC8;
Net fpga_0_radio_bridge_slot_2_radio_5PA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> LOC=U3;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> LOC=Y7;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> LOC=AA8;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> LOC=W10;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> LOC=V4;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin LOC=AA5;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin LOC=AF4;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin LOC=Y8;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin LOC=AA14;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> LOC=Y13;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> LOC=AH3;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> LOC=W15;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> LOC=AA13;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin LOC=AF5;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin LOC=AB13;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin LOC=AK3;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin LOC=AH9;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> LOC=AD10;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> LOC=AD11;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> LOC=AE3;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> LOC=AC13;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> LOC=AF3;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> LOC=AM3;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> LOC=AG10;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> LOC=AF10;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> LOC=AL5;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> LOC=AM8;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_LD_pin LOC=AD9;
Net fpga_0_radio_bridge_slot_2_radio_LD_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin LOC=V13;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin LOC=Y9;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin LOC=AC12;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin LOC=AL3;
Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin LOC=AC10;
Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO LOC=AE6;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO DRIVE = 8;

#### Module radio_bridge_slot_3 constraints

Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin LOC=AC29;
Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> LOC=AG28;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> LOC=AC24;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> LOC=AD31;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> LOC=AA24;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> LOC=AG30;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> LOC=AB23;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> LOC=AH29;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> LOC=AM33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> LOC=AF33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> LOC=AG31;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> LOC=AM22;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> LOC=AH30;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> LOC=AG32;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> LOC=AF31;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> LOC=AH34;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> LOC=AK32;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> LOC=AF34;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> LOC=AN34;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> LOC=AJ36;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> LOC=AN33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> LOC=AH35;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> LOC=AA26;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> LOC=AE29;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> LOC=AA29;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> LOC=AD29;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> LOC=AB26;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> LOC=AB27;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> LOC=AA28;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> LOC=AC28;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> LOC=AL34;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> LOC=AJ34;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> LOC=AK33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> LOC=AK34;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> LOC=AJ35;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> LOC=AG33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> LOC=AB35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> LOC=AC34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> LOC=AA30;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> LOC=Y27;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> LOC=AB31;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> LOC=N37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> LOC=AA31;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> LOC=R34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> LOC=AC32;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> LOC=Y32;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> LOC=AD35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> LOC=Y34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> LOC=P37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> LOC=R36;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> LOC=T35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> LOC=Y33;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> LOC=V34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> LOC=AC35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> LOC=V33;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> LOC=Y36;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> LOC=U37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> LOC=AB36;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> LOC=U35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> LOC=Y37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> LOC=W37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> LOC=AA34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> LOC=W36;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> LOC=AA35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> LOC=W30;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> LOC=W32;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> LOC=V35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> LOC=W34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin LOC=T36;
Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin LOC=W35;
Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin LOC=AA36;
Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin LOC=AC37;
Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin LOC=AD37;
Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin LOC=AF36;
Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin LOC=AD27;
Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin LOC=AE37;
Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin LOC=Y26;
Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin LOC=AC25;
Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_24PA_pin LOC=AM36;
Net fpga_0_radio_bridge_slot_3_radio_24PA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_5PA_pin LOC=AN35;
Net fpga_0_radio_bridge_slot_3_radio_5PA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> LOC=AN37;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> LOC=AJ37;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> LOC=AL35;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> LOC=AE33;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> LOC=AM35;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin LOC=AF28;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin LOC=AD34;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin LOC=AK36;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin LOC=AE28;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> LOC=AG36;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> LOC=AG37;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> LOC=T34;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> LOC=AH37;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin LOC=AD32;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin LOC=K36;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin LOC=W29;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin LOC=K37;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> LOC=P35;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> LOC=AB28;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> LOC=M36;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> LOC=AF35;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> LOC=L36;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> LOC=M37;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> LOC=R37;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> LOC=P36;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> LOC=AE34;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> LOC=Y31;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_LD_pin LOC=AB37;
Net fpga_0_radio_bridge_slot_3_radio_LD_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin LOC=AM37;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin LOC=AL36;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin LOC=U36;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin LOC=AG35;
Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin LOC=AE36;
Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO LOC=AE32;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO DRIVE = 8;

#### Module eeprom_controller constraints

Net fpga_0_eeprom_controller_DQ0_pin LOC=AH22;
Net fpga_0_eeprom_controller_DQ0_pin IOSTANDARD = LVTTL;
Net fpga_0_eeprom_controller_DQ0_pin SLEW = SLOW;
Net fpga_0_eeprom_controller_DQ0_pin DRIVE = 8;

Net mgt_null_controller_0_rxn_mgt01_pin<0> LOC = A22;
Net mgt_null_controller_0_rxp_mgt01_pin<0> LOC = A21;
Net mgt_null_controller_0_txn_mgt01_pin<0> LOC = A25;
Net mgt_null_controller_0_txp_mgt01_pin<0> LOC = A24;
INST *mgt01*INST_A* LOC = GT11_X0Y9;

Net mgt_null_controller_0_rxn_mgt01_pin<1> LOC = A30;
Net mgt_null_controller_0_rxp_mgt01_pin<1> LOC = A29;
Net mgt_null_controller_0_txn_mgt01_pin<1> LOC = A27;
Net mgt_null_controller_0_txp_mgt01_pin<1> LOC = A26;
INST *mgt01*INST_B* LOC = GT11_X0Y8;

Net mgt_null_controller_0_rxn_mgt02_pin<0> LOC = A32;
Net mgt_null_controller_0_rxp_mgt02_pin<0> LOC = A31;
Net mgt_null_controller_0_txn_mgt02_pin<0> LOC = A35;
Net mgt_null_controller_0_txp_mgt02_pin<0> LOC = A34;
INST *mgt02*INST_A* LOC = GT11_X0Y7;

Net mgt_null_controller_0_rxn_mgt02_pin<1> LOC = D39;
Net mgt_null_controller_0_rxp_mgt02_pin<1> LOC = C39;
Net mgt_null_controller_0_txn_mgt02_pin<1> LOC = A37;
Net mgt_null_controller_0_txp_mgt02_pin<1> LOC = A36;
INST *mgt02*INST_B* LOC = GT11_X0Y6;

Net mgt_null_controller_0_rxn_mgt03_pin<0> LOC = K39;
Net mgt_null_controller_0_rxp_mgt03_pin<0> LOC = J39;
Net mgt_null_controller_0_txn_mgt03_pin<0> LOC = N39;
Net mgt_null_controller_0_txp_mgt03_pin<0> LOC = M39;
INST *mgt03*INST_A* LOC = GT11_X0Y5;

Net mgt_null_controller_0_rxn_mgt03_pin<1> LOC = V39;
Net mgt_null_controller_0_rxp_mgt03_pin<1> LOC = U39;
Net mgt_null_controller_0_txn_mgt03_pin<1> LOC = R39;
Net mgt_null_controller_0_txp_mgt03_pin<1> LOC = P39;
INST *mgt03*INST_B* LOC = GT11_X0Y4;

Net mgt_null_controller_0_rxn_mgt05_pin<0> LOC = AM39;
Net mgt_null_controller_0_rxp_mgt05_pin<0> LOC = AL39;
Net mgt_null_controller_0_txn_mgt05_pin<0> LOC = AR39;
Net mgt_null_controller_0_txp_mgt05_pin<0> LOC = AP39;
INST *mgt05*INST_A* LOC = GT11_X0Y3;

Net mgt_null_controller_0_rxn_mgt05_pin<1> LOC = AW36;
Net mgt_null_controller_0_rxp_mgt05_pin<1> LOC = AW37;
Net mgt_null_controller_0_txn_mgt05_pin<1> LOC = AU39;
Net mgt_null_controller_0_txp_mgt05_pin<1> LOC = AT39;
INST *mgt05*INST_B* LOC = GT11_X0Y2;

Net mgt_null_controller_0_rxn_mgt06_pin<0> LOC = AW30;
Net mgt_null_controller_0_rxp_mgt06_pin<0> LOC = AW31;
Net mgt_null_controller_0_txn_mgt06_pin<0> LOC = AW27;
Net mgt_null_controller_0_txp_mgt06_pin<0> LOC = AW28;
INST *mgt06*INST_A* LOC = GT11_X0Y1;

Net mgt_null_controller_0_rxn_mgt06_pin<1> LOC = AW21;
Net mgt_null_controller_0_rxp_mgt06_pin<1> LOC = AW22;
Net mgt_null_controller_0_txn_mgt06_pin<1> LOC = AW24;
Net mgt_null_controller_0_txp_mgt06_pin<1> LOC = AW25;
INST *mgt06*INST_B* LOC = GT11_X0Y0;

Net mgt_null_controller_0_rxn_mgt09_pin<0> LOC = AW10;
Net mgt_null_controller_0_rxp_mgt09_pin<0> LOC = AW9;
Net mgt_null_controller_0_txn_mgt09_pin<0> LOC = AW13;
Net mgt_null_controller_0_txp_mgt09_pin<0> LOC = AW12;
INST *mgt09*INST_A* LOC = GT11_X1Y1;

Net mgt_null_controller_0_rxn_mgt09_pin<1> LOC = AW19;
Net mgt_null_controller_0_rxp_mgt09_pin<1> LOC = AW18;
Net mgt_null_controller_0_txn_mgt09_pin<1> LOC = AW16;
Net mgt_null_controller_0_txp_mgt09_pin<1> LOC = AW15;
INST *mgt09*INST_B* LOC = GT11_X1Y0;

Net mgt_null_controller_0_rxn_mgt10_pin<0> LOC = AM1;
Net mgt_null_controller_0_rxp_mgt10_pin<0> LOC = AL1;
Net mgt_null_controller_0_txn_mgt10_pin<0> LOC = AR1;
Net mgt_null_controller_0_txp_mgt10_pin<0> LOC = AP1;
INST *mgt10*INST_A* LOC = GT11_X1Y3;

Net mgt_null_controller_0_rxn_mgt10_pin<1> LOC = AW4;
Net mgt_null_controller_0_rxp_mgt10_pin<1> LOC = AW3;
Net mgt_null_controller_0_txn_mgt10_pin<1> LOC = AU1;
Net mgt_null_controller_0_txp_mgt10_pin<1> LOC = AT1;
INST *mgt10*INST_B* LOC = GT11_X1Y2;

Net mgt_null_controller_0_rxn_mgt12_pin<0> LOC = K1;
Net mgt_null_controller_0_rxp_mgt12_pin<0> LOC = J1;
Net mgt_null_controller_0_txn_mgt12_pin<0> LOC = N1;
Net mgt_null_controller_0_txp_mgt12_pin<0> LOC = M1;
INST *mgt12*INST_A* LOC = GT11_X1Y5;

Net mgt_null_controller_0_rxn_mgt12_pin<1> LOC = V1;
Net mgt_null_controller_0_rxp_mgt12_pin<1> LOC = U1;
Net mgt_null_controller_0_txn_mgt12_pin<1> LOC = R1;
Net mgt_null_controller_0_txp_mgt12_pin<1> LOC = P1;
INST *mgt12*INST_B* LOC = GT11_X1Y4;

Net mgt_null_controller_0_rxn_mgt13_pin<0> LOC = A8;
Net mgt_null_controller_0_rxp_mgt13_pin<0> LOC = A9;
Net mgt_null_controller_0_txn_mgt13_pin<0> LOC = A5;
Net mgt_null_controller_0_txp_mgt13_pin<0> LOC = A6;
INST *mgt13*INST_A* LOC = GT11_X1Y7;

Net mgt_null_controller_0_rxn_mgt13_pin<1> LOC = D1;
Net mgt_null_controller_0_rxp_mgt13_pin<1> LOC = C1;
Net mgt_null_controller_0_txn_mgt13_pin<1> LOC = A3;
Net mgt_null_controller_0_txp_mgt13_pin<1> LOC = A4;
INST *mgt13*INST_B* LOC = GT11_X1Y6;

Net mgt_null_controller_0_rxn_mgt14_pin<0> LOC = A18;
Net mgt_null_controller_0_rxp_mgt14_pin<0> LOC = A19;
Net mgt_null_controller_0_txn_mgt14_pin<0> LOC = A15;
Net mgt_null_controller_0_txp_mgt14_pin<0> LOC = A16;
INST *mgt14*INST_A* LOC = GT11_X1Y9;

Net mgt_null_controller_0_rxn_mgt14_pin<1> LOC = A10;
Net mgt_null_controller_0_rxp_mgt14_pin<1> LOC = A11;
Net mgt_null_controller_0_txn_mgt14_pin<1> LOC = A13;
Net mgt_null_controller_0_txp_mgt14_pin<1> LOC = A14;
INST *mgt14*INST_B* LOC = GT11_X1Y8;