Creating the Model

Open MATLAB 2007a.

Open the Simulink Library browser by typing 'simulink' on the MATLAB Command Window.

This should open a browser that looks like the above picture. Notice that there is a WARP Blockset. If you do not see this in your library, re-visit the instructions on installing the WARP user repository at http://warp.rice.edu/trac.

Open a new model by clicking New -> Model in the Simulink Library Browser. This should open a blank canvas where the new design will be built.

Expand the Xilinx Blockset by clicking the plus (+) sign next to it. These are the blocks that we will use to create the custom peripherals as they can be generated into HDL code. Only blocks with a white X are valid for generation.

Drag in a System Generator block. This is required at the top-level in every Sysgen design. It has the system parameters such as simulation sampling period and corresponding clock frequency. This also has the options to generate HDL.

Save the model as ddsexample.mdl in a folder that does not contain spaces. For example, 'C:\Documents and Settings\User\Desktop' is not a valid location while 'C:\WARP_Tutorial\Peripherals' is valid.

Drag in an Accumulator Block. This will increment a phase value to feed to the LUT.

Double-click the block to open the options window. Set it up as shown above. The synchronous reset port will not be needed and choose 32 bits for the data to maintain high-precision.

Drag in a Slice block. We are going to use a LUT to store the sine and cosine waves, but they will only be 2^12 deep. So we need to slice off the top 12 bits of the Accumulator to feed into the address port of the LUT.

In the options for the Slice, set the width to be 12 and MSB input. This will slice 12 bits from the top of the word.

Drag in 2 ROM blocks. These will serve as the LUT that store the sine and cosine waves. Rename the blocks as SIN and COS to diambiguate them.

In the options for the SIN block, the depth should be set as 2^12 as thats the number of sample we want to store. The Initial Value Vector must be set one complete sine wave.

In the Output Type tab, make sure to set the output for Signed with 16 bits and binary point at 15. This should give us sufficient precision for the waves.

Similarly for the COS, the Initial Value vector must the cosine wave. Remember to set the precision as well just like the sine wave.

In order to drive the Accumulator, we need a constant phase increment input. This will be done using the From Register Block. The idea is that given a constant phase increment, the accumulator will loop through the values stored in the ROM at that rate. If the phase increment value is high, the sine and cosine wave outputs will have a higher frequency, while if the value is low, the output freqency will be low as well.

Setup the From Register by giving it the name phaseInc. Set the Initial Value to 1. Set the register to be Locally owned and initialized.

Also for the Output type, we can take an input up to 32 bits as that is the width of the Accumulator. However, this time we want it to be Unsigned as we will like only positive increment values.

The output of the ROM blocks varies between 1 and -1. That is the extent that the DAC can output. To avoid hitting the rails, the output must be scaled. Use a Scale block on the output of the ROMs.

Set the block to scale by 2^-1. Now the output should vary between -0.5 and 0.5.

Before passing the sine and cosine values to the DAC, lets add a Register so we can reset the output if needed.

Check the synchronous reset port box that can be asserted using a register.

Add a From Register block and a Convert block to connect to the reset ports of the registers. The From Register can only output Unsigned or Signed, but the reset requires a Boolean input. This will be done by the Convert block.

Name the From Register outputReset. Make sure the initial value is 0 so the system is not in reset by default.

Change the output type of the From Register to Unsigned with 1 bit.

For the Convert block, change the output type to Boolean.

The last step is to add DACs. Two pairs of DACs will connect to both outputs; one forwarding the data to the Analog Board and the other to the Radio Board.

To add the DAC blocks, expand the WARP Blockset.

Drag in Analog 4 DAC 1A and Analog 4 DAC 1B. The 4 is because the Analog Daughtercard is normally in slot 4, while 1A and 1B correspond to the DAC outputs on the daughtercard.

Connect the output of your system to Radio blocks as well. Thus this model can be connected to the Analog Board or Radio Board. Drag in Radio 2 DAC I and Radio 2 DAC Q. Remember to connect the sine to the Q channel and the cosine to I channel.

Finally, drag in Bus Creator and Scope blocks and connect the Analog Board outputs to them. This well help in simulation.

At this time, the model itself is complete. Next we will test and simulate model before generating the HDL corresponding to it.