Exporting as Peripheral Core

Before generating the HDL core, set the intial value of the phaseInc register back to 1 embedding this value into the hardware design. The From Registers will get memory-mapped in the process of generation and we will be able to change their values by reading and writing certain address locations.

In order to create memory map, drag in the EDK Processor block from the Xilinx Library.

Double-clicking it will reveal the options window. Click Add to create the register map. This will populate the map with the list of registers found in the system. The registers can be expanded to see their address locations. Click Apply to save.

Move to the Implementation tab of the EDK Processor block. Here check Register Read-Back as shown above. Click Ok or Apply to save.

Open the System Generator block. It will reveals a whole set of options to create the design. As the model is going to be part of a Xilinx Platform Studio project, choose EDK Export Tool to the Compilation. This will create all the supporting files so it can be recognized by the Embedded Development Kit (EDK) that Xilinx provides.

The WARP Boards are Virtex-II Pro FPGA-based so select the Virtex2P -> xc2vp70 -> -6 -> ff1517. This selects the correct target as each FPGA has a different architecture inside.

Finally, click Generate to start the compilation.

The above window will pop-up once the generation is complete. At this point there is an XPS-compatible peripheral core available in the ./netlist/pcores folder. This includes the HDL for the core and associated data files that identifies the type of core, the memory-mapped locations etc.