Functions
int	ad_init (u32 baseaddr, u8 clkdiv)

u32	ad_spi_read (u32 baseaddr, u32 csMask, u8 regAddr)

void	ad_spi_write (u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte)

int	ad_set_TxDCO (u32 baseaddr, u32 csMask, u8 iqSel, u16 dco)

int	ad_set_TxGain1 (u32 baseaddr, u32 csMask, u8 iqSel, u8 gain)

int	ad_set_TxGain2 (u32 baseaddr, u32 csMask, u8 iqSel, u8 gain)

int	ad_config_filters (u32 baseaddr, u32 csMask, u8 interpRate, u8 decimationRate)

int	ad_config_clocks (u32 baseaddr, u32 csMask, u8 DAC_clkSrc, u8 ADC_clkSrc, u8 ADC_clkDiv, u8 ADC_DCS)

int	ad_config_DLL (u32 baseaddr, u32 csMask, u8 DLL_En, u8 DLL_M, u8 DLL_N, u8 DLL_DIV)

int	ad_config_power (u32 baseaddr, u32 csMask, u8 pwrState)

Detailed Description

Example:

//Assumes user code sets AD_BASEADDR to base address of w3_ad_controller core, as set in xparameters.h
//Initialize the AD9963s
ad_init(AD_CONTROLLER, 3);

Function Documentation

int ad_init	(	u32	baseaddr,
		u8	clkdiv
	)

Initializes the AD controller. This function must be called once at boot before any AD or RF operations will work.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
clkdiv	Clock divider for SPI serial clock (set to 3 for 160MHz bus)

u32 ad_spi_read	(	u32	baseaddr,
		u32	csMask,
		u8	regAddr
	)

Reads the specified register from both AD9963s.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
regAddr	Address of register to read, in [0x00, 0x82]

Returns: Returns concatenation of current values of the specified register for both AD9963s; RFA is LSB

void ad_spi_write	(	u32	baseaddr,
		u32	csMask,
		u8	regAddr,
		u8	txByte
	)

Writes the specified register in selected AD9963s. Multiple AD9963s can be selected for simultaneous writes.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
regAddr	Address of register to write, in [0x00, 0xFF]
txByte	Byte value to write

int ad_set_TxDCO	(	u32	baseaddr,
		u32	csMask,
		u8	iqSel,
		u16	dco
	)

Sets the DC offset for the selected path (I or Q) in the selected AD9963s.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
iqSel	Select I or Q path; must be AD_CHAN_I or AD_CHAN_Q
dco	DC offset to apply, in [0,1024]

int ad_set_TxGain1	(	u32	baseaddr,
		u32	csMask,
		u8	iqSel,
		u8	gain
	)

Sets the GAIN1 value (linear-in-dB adjustment +/- 6dB) for the selected path (I or Q) in the selected AD9963s. Changing this gain value also changes the common mode voltage and DC offset of the selected path. We recommend leaving this gain setting unchanged for optimal performance.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
iqSel	Select I or Q path; must be AD_CHAN_I or AD_CHAN_Q
gain	6-bit gain value; [0:25] = [0:+6dB], [41,63] = [-6dB:0dB]

int ad_set_TxGain2	(	u32	baseaddr,
		u32	csMask,
		u8	iqSel,
		u8	gain
	)

Sets the GAIN2 value (linear adjustment +/- 2.5%) for the selected path (I or Q) in the selected AD9963s Changing this gain value also changes the common mode voltage and DC offset of the selected path. We recommend leaving this gain setting unchanged for optimal performance.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
iqSel	Select I or Q path; must be AD_CHAN_I or AD_CHAN_Q
gain	6-bit gain value; [0:25] = [0:+2.5%], [41,63] = [-2.5%:0]

int ad_config_filters	(	u32	baseaddr,
		u32	csMask,
		u8	interpRate,
		u8	decimationRate
	)

Configures the digital rate-change filters in the AD9963. Changing filter settings affects the require data rate at the TXD and TRXD ports. You must ensure all related paramters (AD9963 filters, I/Q rate in FPGA, AD9512 dividers) are consistent.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
interpRate	Desired interpolation rate in AD9963; must be one of [1, 2, 4, 8]
decimationRate	Desired decimation rate in AD9963; must be one of [1, 2]

Returns: Returns 0 on success, -1 for invalid paramters

int ad_config_clocks	(	u32	baseaddr,
		u32	csMask,
		u8	DAC_clkSrc,
		u8	ADC_clkSrc,
		u8	ADC_clkDiv,
		u8	ADC_DCS
	)

Configures the ADC and DAC clock sources in the AD9963. Refer to the WARP v3 user guide and AD9963 for details on various clocking modes.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
DAC_clkSrc	DAC clock source; must be AD_DACCLKSRC_DLL (use DLL clock) or AD_DACCLKSRC_EXT (use external reference clock)
ADC_clkSrc	ADC clock source; must be AD_ADCCLKSRC_DLL (use DLL clock) or AD_ADCCLKSRC_EXT (use external reference clock)
ADC_clkDiv	ADC clock divider; must be one of [AD_ADCCLKDIV_1, AD_ADCCLKDIV_2, AD_ADCCLKDIV_4] for divide-by of [1, 2, 4]
ADC_DCS	ADC duty cycle stabilizer; must be AD_DCS_ON or AD_DCS_OFF. AD9963 datasheet recommends DCS be enabled only for ADC rates above 75MHz.

Returns: Returns 0 on success, -1 for invalid paramters

int ad_config_DLL	(	u32	baseaddr,
		u32	csMask,
		u8	DLL_En,
		u8	DLL_M,
		u8	DLL_N,
		u8	DLL_DIV
	)

Configures the AD9963 DLL block. DLL output clock is REFCLK*M/(N*DLL_DIV). REFCLK*M must be in [100,310]MHz. See the AD9963 for more details.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
DLL_En	DLL Enable (1=DLL enabled, 0=DLL disabled). Other arguments are ignored when DLL_En=0
DLL_M	DLL multiplication (M) parameter; must be in [0,1,...,31] for multiplications of [1,2,...,32], constrained by M*REFCLK in [100, 310]MHz
DLL_N	DLL division (N) parameter; must be one of [1,2,3,4,5,6,8]
DLL_DIV	Secondary DLL divider; must be one of [1,2,4]

Returns: Returns 0 on success, -1 for invalid paramters, -2 if DLLs fail to lock with new settings

int ad_config_power	(	u32	baseaddr,
		u32	csMask,
		u8	pwrState
	)

Shuts down or enables the selected AD9963. Starting up from shutdown is not instantaneous, so this function should only be used to disable an AD9963 that will be unsed for a while. If you shutdown a AD9963, you should also shutdown the corresponding MAX2829 with radio_controller_setMode_shutdown(). Note: this function will always leave the AD9963 DLL shutdown. You must call ad_config_DLL() again to re-configure and re-enable the DLL if your design uses the DLL clock for ADCs or DACs.

Parameters

baseaddr	Base memory address of w3_ad_controller pcore
csMask	OR'd combination of RFA_AD_CS and RFB_AD_CS
pwrState	Desired AD9963 power state; must be one of [AD_PWR_ALLOFF, AD_PWR_ALLON]

Returns: Returns 0 on success, -1 for invalid paramters

Functions

Detailed Description

Function Documentation