Functions

Functions
int	clk_init (u32 baseaddr, u8 clkDiv)
int	clk_config_outputs (u32 baseaddr, u8 clkOutMode, u32 clkOutSel)
int	clk_config_dividers (u32 baseaddr, u8 clkDiv, u32 clkOutSel)
u32	clk_spi_read (u32 baseaddr, u32 csMask, u8 regAddr)
void	clk_spi_write (u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte)

Detailed Description

Example:

//Assumes user code sets CLK_BASEADDR to base address of w3_clock_controller core, as set in xparameters.h

//Initialize the AD9512 clock buffers
ad_init(CLK_BASEADDR, 3);

//Enable clock outputs to FMC slot
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC | CLK_RFREF_OUTSEL_FMC));

//Disable clock outputs to clock module header
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));

//Set clock to AD chips to 40MHz (80MHz source divided by 2)
clk_config_dividers(CLK_BASEADDR, 2, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));

Function Documentation

int clk_init	(	u32	baseaddr,
		u8	clkDiv
	)

Initializes the clock controller. This function must be called once at boot before any AD or RF operations will work. Default config is:

• On board 80MHz TCXO used as source for sampling and RF ref clock buffers
• 80MHz clock driven to FPGA, RF A and RF B ADC/DACs
• 40MHz clock driven to RF A and B transceivers
• FMC and clock module header clocks disabled

  Parameters

  baseaddr	Base memory address of w3_clock_controller pcore
  clkDiv	Clock divider for SPI serial clock (set to 3 for 160MHz bus)

int clk_config_outputs	(	u32	baseaddr,
		u8	clkOutMode,
		u32	clkOutSel
	)

Configures which outputs are en/disabled in both AD9512 clock buffers.

Parameters

baseaddr	Base memory address of w3_clock_controller pcore
clkOutMode	New mode for selected clock outputs; must be CLK_OUTPUT_ON or CLK_OUTPUT_OFF
clkOutSel	Masks to select which clock outputs to affect; must be OR'd combination of: Mask Selected Output CLK_SAMP_OUTSEL_FMC Sampling clock buffer to FMC slot CLK_SAMP_OUTSEL_CLKMODHDR Sampling clock buffer to clock module header CLK_SAMP_OUTSEL_FPGA Sampling clock buffer to FPGA CLK_SAMP_OUTSEL_AD_RFA Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) CLK_SAMP_OUTSEL_AD_RFB Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) CLK_RFREF_OUTSEL_FMC RF ref clock buffer to FMC CLK_RFREF_OUTSEL_CLKMODHDR RF ref clock buffer to clock module header CLK_RFREF_OUTSEL_RFAB RF ref clock buffer to RF A and B transceivers

Returns

Returns 0 on success, -1 for invalid parameters

int clk_config_dividers	(	u32	baseaddr,
		u8	clkDiv,
		u32	clkOutSel
	)

Configures output dividers in both AD9512 clock buffers.

Parameters

baseaddr	Base memory address of w3_clock_controller pcore
clkDiv	Divider value to set; must be 1 or even integer in [2,32]
clkOutSel	Masks to select which clock outputs to affect; must be OR'd combination of: Mask Selected Output CLK_SAMP_OUTSEL_FMC Sampling clock buffer to FMC slot CLK_SAMP_OUTSEL_CLKMODHDR Sampling clock buffer to clock module header CLK_SAMP_OUTSEL_FPGA Sampling clock buffer to FPGA CLK_SAMP_OUTSEL_AD_RFA Sampling clock buffer to RF A AD9963 (ADC/DAC ref clock) CLK_SAMP_OUTSEL_AD_RFB Sampling clock buffer to RF B AD9963 (ADC/DAC ref clock) CLK_RFREF_OUTSEL_FMC RF ref clock buffer to FMC CLK_RFREF_OUTSEL_CLKMODHDR RF ref clock buffer to clock module header CLK_RFREF_OUTSEL_RFAB RF ref clock buffer to RF A and B transceivers

Returns

Returns 0 on success, -1 for invalid parameters

u32 clk_spi_read	(	u32	baseaddr,
		u32	csMask,
		u8	regAddr
	)

Reads the specified register from both AD9963s.

Parameters

baseaddr	Base memory address of w3_clock_controller pcore
csMask	OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS
regAddr	Address of register to read, in [0x00, 0x5A]

Returns

Returns concatenation of current values of the specified register for both AD9512s (if selected); samp clock buffer is LSB

void clk_spi_write	(	u32	baseaddr,
		u32	csMask,
		u8	regAddr,
		u8	txByte
	)

Writes the specified register value to the selected AD9512 clock buffers.

Parameters

baseaddr	Base memory address of w3_clock_controller pcore
csMask	OR'd combination of CLK_SAMP_CS and CLK_RFREF_CS
regAddr	Address of register to write, in [0x00, 0x5A]
txByte	8-bit value to write