Control registers

Macros
#define	userio_read_control(baseaddr)   Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET)
#define	userio_write_control(baseaddr, x)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, x)
#define	userio_set_ctrlSrc_sw(baseaddr, ioMask)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) & ~(ioMask)))
#define	userio_set_ctrlSrc_hw(baseaddr, ioMask)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) | (ioMask)))
#define	userio_set_hw_ctrl_mode_pwm(baseaddr, ioMask)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG10_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) | (ioMask)))
#define	userio_set_hw_ctrl_mode_port(baseaddr, ioMask)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG10_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) & (~ioMask)))
#define	userio_set_pwm_period(baseaddr, p)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG7_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG7_OFFSET) & 0x0000FFFF) | (((p) & 0xFFFF)<<16))
#define	userio_set_pwm_thresh(baseaddr, t)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG7_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG7_OFFSET) & 0xFFFF0000) | ((t) & 0xFFFF))
#define	userio_set_pwm_ramp_en(baseaddr, d)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, ( (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0x7FFFFFFF) | ((d&0x1)<<31)))
#define	userio_set_pwm_ramp_max(baseaddr, m)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0xFFFF0000) | ((m) & 0xFFFF))
#define	userio_set_pwm_ramp_min(baseaddr, m)   Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0x8000FFFF) | (((m) & 0x7FFF)<<16))
#define	W3_USERIO_HEXDISP_L_MAPMODE   0x20000000
#define	W3_USERIO_HEXDISP_R_MAPMODE   0x10000000
#define	W3_USERIO_CTRLSRC_LED_RFB_RED   0x08000000
#define	W3_USERIO_CTRLSRC_LED_RFB_GREEN   0x04000000
#define	W3_USERIO_CTRLSRC_LED_RFA_RED   0x02000000
#define	W3_USERIO_CTRLSRC_LED_RFA_GREEN   0x01000000
#define	W3_USERIO_CTRLSRC_LEDS_RED   0x000F0000
#define	W3_USERIO_CTRLSRC_LEDS_GREEN   0x00F00000
#define	W3_USERIO_CTRLSRC_HEXDISP_R   0x0000FF00
#define	W3_USERIO_CTRLSRC_HEXDISP_L   0x000000FF
#define	W3_USERIO_CTRLSRC_HEXDISP_DP_R   0x00008000
#define	W3_USERIO_CTRLSRC_HEXDISP_DP_L   0x00000080
#define	W3_USERIO_CTRLSRC_LEDS_RFA   (W3_USERIO_CTRLSRC_LED_RFA_RED | W3_USERIO_CTRLSRC_LED_RFA_GREEN)
#define	W3_USERIO_CTRLSRC_LEDS_RFB   (W3_USERIO_CTRLSRC_LED_RFB_RED | W3_USERIO_CTRLSRC_LED_RFB_GREEN)
#define	W3_USERIO_CTRLSRC_LEDS_RF   (W3_USERIO_CTRLSRC_LEDS_RFA | W3_USERIO_CTRLSRC_LEDS_RFB)
#define	W3_USERIO_CTRLSRC_LEDS   (W3_USERIO_CTRLSRC_LEDS_RED | W3_USERIO_CTRLSRC_LEDS_GREEN)
#define	W3_USERIO_CTRLSRC_HEXDISPS   (W3_USERIO_CTRLSRC_HEXDISP_L | W3_USERIO_CTRLSRC_HEXDISP_R)
#define	W3_USERIO_CTRLSRC_ALL_OUTPUTS   (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS | W3_USERIO_CTRLSRC_HEXDISPS)

Detailed Description

Hardware vs. software control: Every LED and hex display segment can be controlled either via software or hardware:

• Software: user code sets LED state by writing a 1 to the corresponding register bit
• Hardware: Two modes:
  • Port mode: LED state is controlled by corresponding usr_* port
  • PWM mode: LED state is controlled by internal PWM waveform generator

The WARP reference designs use hardware/port control for the RF LEDs (to indicate real-time Tx/Rx state of each RF interface) and software control for all other LED/hex display outputs.

The control source (hw or sw) for each output bit is set by the control register described below.

Examples:

//Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h

//------------------------------------------------------------------------------
// Set both hex dipslays to map 4-bit to 7-segment values automatically
userio_write_control(USERIO_BASEADDR, (W3_USERIO_HEXDISP_L_MAPMODE | W3_USERIO_HEXDISP_R_MAPMODE));

//------------------------------------------------------------------------------
// Select software control of all outputs
userio_set_ctrlSrc_sw(USERIO_BASEADDR, (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS | W3_USERIO_CTRLSRC_HEXDISPS));

//------------------------------------------------------------------------------
// Select hardware/port control of RF LEDs
userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RF);

//------------------------------------------------------------------------------
// Enable hardware control of green user LEDs, software control of red user LEDs
userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_GREEN);
userio_set_ctrlSrc_sw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);

//------------------------------------------------------------------------------
// Use the PWM generator to slowly blink the green LEDs
userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_GREEN);
userio_set_hw_ctrl_mode_pwm(USERIO_BASEADDR, (W3_USERIO_CTRLSRC_LEDS_GREEN);
userio_set_pwm_ramp_en(USERIO_BASEADDR, 0);
userio_set_pwm_period(USERIO_BASEADDR, 65530);
userio_set_pwm_thresh(USERIO_BASEADDR, 65530/2);

//------------------------------------------------------------------------------
// Use the PWM generator to show a "sleep" pattern on red LEDs
userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);
userio_set_hw_ctrl_mode_pwm(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);

//Use fast period so blinking is not visable
// (fast blink with low duty cycle looks like a dim constant brightness)
userio_set_pwm_period(USERIO_BASEADDR, 500);

//Ramp must be disabled when changing ramp params
userio_set_pwm_ramp_en(USERIO_BASEADDR, 0);
userio_set_pwm_ramp_min(USERIO_BASEADDR, 2);
userio_set_pwm_ramp_max(USERIO_BASEADDR, 250);
userio_set_pwm_ramp_en(USERIO_BASEADDR, 1);

Macro Definition Documentation

#define userio_read_control

(

baseaddr

)

Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET)

Returns the value of the control register.

#define userio_write_control	(		baseaddr,
			x
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, x)

Sets the control register to x.

#define userio_set_ctrlSrc_sw	(		baseaddr,
			ioMask
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) & ~(ioMask)))

Sets selected outputs to software control (register writes)

#define userio_set_ctrlSrc_hw	(		baseaddr,
			ioMask
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) | (ioMask)))

Sets selected outputs to hardware control (usr_ ports)

#define userio_set_hw_ctrl_mode_pwm	(		baseaddr,
			ioMask
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG10_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) | (ioMask)))

Sets selected outputs to use PWM generator for hardware/PWM control.

#define userio_set_hw_ctrl_mode_port	(		baseaddr,
			ioMask
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG10_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) & (~ioMask)))

Sets selected outputs to use PWM generator for hardware/port control.

#define userio_set_pwm_period	(		baseaddr,
			p
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG7_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG7_OFFSET) & 0x0000FFFF) | (((p) & 0xFFFF)<<16))

Sets the PWM period; larger periods result in slower blinking.

#define userio_set_pwm_thresh	(		baseaddr,
			t
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG7_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG7_OFFSET) & 0xFFFF0000) | ((t) & 0xFFFF))

Sets the PWM duty cycle threshold; threshold be greater than 1 and less than the PWM period. This threshold is ignored when the threshold ramp is enabled.

#define userio_set_pwm_ramp_en	(		baseaddr,
			d
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, ( (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0x7FFFFFFF) | ((d&0x1)<<31)))

Enables and disables the PWM threshold ramp logic. Ramp must be disabled when changing ramp min/max params.

#define userio_set_pwm_ramp_max	(		baseaddr,
			m
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0xFFFF0000) | ((m) & 0xFFFF))

Sets the max value of the ramped PWM threshold; must be greater than the ramp min value and less than the PWM period.

#define userio_set_pwm_ramp_min	(		baseaddr,
			m
	)		Xil_Out32(baseaddr+W3_USERIO_SLV_REG9_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG9_OFFSET) & 0x8000FFFF) | (((m) & 0x7FFF)<<16))

Sets the min value of the ramped PWM threshold; must be greater than 1 and less than the ramp max value.

#define W3_USERIO_HEXDISP_L_MAPMODE   0x20000000

Enables 4-bit to 7-segment mapping for left hex display.

#define W3_USERIO_HEXDISP_R_MAPMODE   0x10000000

Enables 4-bit to 7-segment mapping for right hex display.

#define W3_USERIO_CTRLSRC_LED_RFB_RED   0x08000000

Control source selection mask for red LED near RF B.

#define W3_USERIO_CTRLSRC_LED_RFB_GREEN   0x04000000

Control source selection mask for green LED near RF B.

#define W3_USERIO_CTRLSRC_LED_RFA_RED   0x02000000

Control source selection mask for red LED near RF A.

#define W3_USERIO_CTRLSRC_LED_RFA_GREEN   0x01000000

Control source selection mask for green LED near RF A.

#define W3_USERIO_CTRLSRC_LEDS_RED   0x000F0000

Control source selection mask for the red user LEDs.

#define W3_USERIO_CTRLSRC_LEDS_GREEN   0x00F00000

Control source selection mask for the green user LEDs.

#define W3_USERIO_CTRLSRC_HEXDISP_R   0x0000FF00

Control source selection mask for the left hex display (includes decimal point)

#define W3_USERIO_CTRLSRC_HEXDISP_L   0x000000FF

Control source selection mask for the right hex display (includes decimal point)

#define W3_USERIO_CTRLSRC_HEXDISP_DP_R   0x00008000

Control source selection mask for the left hex display decimal point.

#define W3_USERIO_CTRLSRC_HEXDISP_DP_L   0x00000080

Control source selection mask for the right hex display decimal point.

#define W3_USERIO_CTRLSRC_LEDS_RFA   (W3_USERIO_CTRLSRC_LED_RFA_RED | W3_USERIO_CTRLSRC_LED_RFA_GREEN)

Control source selection masks for both LEDs near RF A.

#define W3_USERIO_CTRLSRC_LEDS_RFB   (W3_USERIO_CTRLSRC_LED_RFB_RED | W3_USERIO_CTRLSRC_LED_RFB_GREEN)

Control source selection masks for both LEDs near RF B.

#define W3_USERIO_CTRLSRC_LEDS_RF   (W3_USERIO_CTRLSRC_LEDS_RFA | W3_USERIO_CTRLSRC_LEDS_RFB)

Control source selection masks for all RF LEDs.

#define W3_USERIO_CTRLSRC_LEDS   (W3_USERIO_CTRLSRC_LEDS_RED | W3_USERIO_CTRLSRC_LEDS_GREEN)

Control source selection masks for all user LEDs.

#define W3_USERIO_CTRLSRC_HEXDISPS   (W3_USERIO_CTRLSRC_HEXDISP_L | W3_USERIO_CTRLSRC_HEXDISP_R)

Control source selection masks for both hex displays.

#define W3_USERIO_CTRLSRC_ALL_OUTPUTS   (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS | W3_USERIO_CTRLSRC_HEXDISPS)

Control source selection masks for all outputs.