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Changes between Version 8 and Version 9 of 802.11/Architecture

v8	v9
19	19	* '''MAC DCF Core (wlan_mac_dcf_hw):''' an FPGA core implemented in System Generator which acts as the interface between the MAC software design and the Tx/Rx PHY cores. This core implements the timers required for the DCF (timeout, backoff, DIFS, SIFS, etc.) and the various carrier sensing mechanisms. The MAC DCF core monitors the Tx and Rx PHY cores and sequences Tx and Rx events per the configuration provided by the MAC software.
20	20
21		* '''PHY Tx/Rx''': These peripheral cores implement the OFDM physical layer transceiver specified in Section 18 of the 802.11-2012 standard. Details are available in the [wiki:./PHY PHY page]. The PHY cores are clocked at 160MHz (8x the I/Q sample rate).
	21	* '''PHY Tx/Rx''': These peripheral cores implement the OFDM physical layer transceiver specified in Section 18 of the 802.11-2012 standard. Details are available in the [wiki:../PHY PHY page]. The PHY cores are clocked at 160MHz (8x the I/Q sample rate).
22	22
23	23	* '''Hardware Support''': These cores are drawn from the standard platform support cores for WARP v3 ([wiki:cores/w3_ad_controller w3_ad_controller], [wiki:cores/radio_controller radio_controller], etc.) and enable control of the various peripheral interfaces on WARP v3 from the code in CPU Low.