Changes between Version 20 and Version 21 of 802.11/PHY
- Timestamp:
- Jun 9, 2016, 4:07:25 PM (8 years ago)
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802.11/PHY
v20 v21 19 19 [[Image(wiki:802.11/files:wlan_phy_cores_arch.png,nolink)]] 20 20 21 At one end the PHY cores interface directly to the ADCs and DACs on the WARP v3 hardware via the w3_ad_bridge core. These interfaces are complex sample streams running at 20MHz. At the other end the cores connect to the Tx and Rx packet buffers. The packet buffers are implemented as dual-port RAMs, each with one port dedicated to PHY access and the other port tied to the AXI interconnect for access by the CPUs.21 At one end the PHY cores interface directly to the ADCs and DACs on the WARP v3 hardware via the w3_ad_bridge core. These interfaces are complex sample streams running at 10, 20 or 40MHz. At the other end the cores connect to the Tx and Rx packet buffers. The packet buffers are implemented as dual-port RAMs, each with one port dedicated to PHY access and the other port tied to the AXI interconnect for access by the CPUs. 22 22 23 23 == PHY Specs == … … 25 25 '''Clock frequency:''' 160MHz 26 26 27 '''Bandwidth:''' 20MHz max27 '''Bandwidth:''' 10, 20 or 40MHz 28 28 29 29 '''OFDM format:''' 64 subcarriers (48 data, 4 pilots), 16-sample cyclic prefix … … 83 83 * '''Descrambling''': the de-coded bits are finally descrambled using the LFSR specified in the standard 84 84 85 All logic in the 802.11 receiver FPGA core is clocked at 160MHz and supports a maximum bandwidth of 20MHz (clock rate = 8x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the Rx pipeline.85 All logic in the 802.11 receiver FPGA core is clocked at 160MHz and supports a maximum bandwidth of 40MHz (clock rate = 4x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the Rx pipeline. 86 86 87 87 === DSSS === … … 115 115 * '''Antenna Selection''': the complete waveform is finally transmitted via the selected RF interface 116 116 117 All logic in the 802.11 transmitter FPGA core is clocked at 160MHz and supports a maximum bandwidth of 20MHz (clock rate = 8x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the sample FIFO at the RF interface ports.117 All logic in the 802.11 transmitter FPGA core is clocked at 160MHz and supports a maximum bandwidth of 40MHz (clock rate = 4x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the sample FIFO at the RF interface ports.
