802.11 Reference Design: PHY
The Mango 802.11 Reference Design implements a complete, real-time PHY transceiver in FPGA fabric. Our physical layer implementation is based on the OFDM PHY specified in sections 18 and 20 of of the 802.11-2012 standard. This PHY is commonly referred to as "802.11a/n" (at 5GHz) and "802.11g/n" (at 2.4GHz). The PHY adopts the 11a/g/n standard as defaults for its many parameters (subcarrier allocations, preamble structure, etc.). Many of these parameters can be customized with minor changes to the PHY core initialization scripts.
The PHY FPGA cores are implemented as Xilinx System Generator models. The source models are available in the repository: /ReferenceDesigns/w3_802.11/sysgen.
The 802.11 Reference Design physical layer implementation is divided across three FPGA cores:
- wlan_phy_tx_pmd: OFDM transmitter
- wlan_phy_rx_pmd: OFDM and DSSS receiver
- wlan_phy_agc: Automatic gain control (AGC)
At one end the PHY cores interface directly to the ADCs and DACs on the WARP v3 hardware via the w3_ad_bridge core. These interfaces are complex sample streams running at 10, 20 or 40MHz. At the other end the cores connect to the Tx and Rx packet buffers. The packet buffers are implemented as dual-port RAMs, each with one port dedicated to PHY access and the other port tied to the AXI interconnect for access by the CPUs.
Clock frequency: 160MHz
Bandwidth: 10, 20 or 40MHz
- 10MHz and 20MHz bandwidths are compliant to 802.11
- 40MHz implemented as double-clocked 20MHz, not compliant to 802.11 HT40 waveform
OFDM format: 64 subcarriers, 16-sample cyclic prefix
- NONHT waveform (11ag): 48 data subcarriers, 4 pilot tones
- HTMF waveform (11n): 52 data subcarriers, 4 pilot tones
Frame Format: As specified in sections 18 and 20 of 802.11-2012:
- Preamble (10 repetitions of 16-sample short training symbol, 2.5 repetitions of 64-sample long training symbol)
- SIGNAL field as first OFDM symbol (3 bytes as BSPK, rate 1/2 code)
- HT-SIG, HT-STF and HT-LTF for HTMF waveforms
- Remaining OFDM symbols filled with SERVICE field (2 bytes) and payload (up to 2048 bytes) at one of the rates listed below
Rates: The following OFDM data rates are implemented. Each data rate is realized by a combination of modulation and coding rates.
Multi-antenna Support: The current PHY Tx/Rx pipelines are SISO, supporting the modulation/coding rates specified in sections 18 and 20 of the standard. The PHY antenna interfaces implement selection diversity across the two RF interfaces on WARP v3 hardware. The antenna selection is made per packet. For transmissions the antenna selection is always controlled by C code in CPU Low. For receptions the PHY can automatically select the higher-SNR antenna based on the AGC gain selections. Alternatively the C code in CPU Low can force the receive antenna selection.
The architecture of the 802.11 receiver FPGA core is illustrated below. The source model is in the repository: ReferenceDesigns/w3_802.11/sysgen/wlan_phy_rx_pmd.
- Packet Detection: implements two packet detection schemes: simple energy detection based on RSSI and auto-correlation of the I/Q samples searching for the preamble STS, based on the well-known Schmidl-Cox algorithm. When selection diversity is enabled parallel packet detectors are enabled so that either antenna can trigger a detection.
- Antenna Selection: automatic selection of which I/Q stream feeds the rest of the PHY pipeline, using AGC gain selections as an indicator of received SNR.
- LTS Correlation: cross correlator searching for the 64-sample LTS in the preamble. The two LTS correlation peaks establish timing for the rest of the reception, marking the boundary of each OFDM symbol fed into the FFT.
- Synchronization: a dual-port circular sample buffer records all incoming samples. Once the LTS correlator establishes sample-level timing the buffer begins reading samples into the FFT using the correlation timing to set the boundary of each OFDM symbol.
- CFO Correction: the carrier frequency offset (CFO) is estimated before the FFT by comparing the phases of identical samples in the two LTS. The CFO is estimated by averaging the 64 phase comparisons, then removed by multiplying the I/Q samples by the output of a DDS.
- FFT: translates the time domain received samples into the frequency domain. Each FFT consumes 64 time domain samples and produces 64 frequency domain samples. The boundary of each FFT is established by the synchronization blocks above. The cyclic prefix of each OFDM symbol is removed by advancing the boundary of each FFT 16 samples per transform.
- Channel Estimation: a complex channel coefficient is calculated for each non-zero subcarrier by averaging the estimates from the two LTS.
- Phase Error Estimation: the pilot tones embedded in each OFDM symbol are used to calculate a phase error estimate per OFDM symbol. Every subcarrier in the OFDM symbol is then de-rotated by the estimated phase error.
- Equalization: the channel estimates and phase-corrected data symbols are fed into the equalizer to remove amplitude and phase errors incurred by propagation through the wireless channel. The current implementation uses a simple zero-forcing equalizer, dividing each subcarrier by the corresponding channel coefficient and using the same channel coefficients for the full packet.
- Soft Demod: each data symbol is then demodulated to a soft value per coded bit
- De-Interleaving: the coded bits, represented as soft 4-bit confidence values, are de-interleaved along OFDM symbol boundaries using the interleaving pattern specified in the standard
- Decoding: the de-interleaved soft values are decoded using a standard Viterbi decoder
- Descrambling: the de-coded bits are finally descrambled using the LFSR specified in the standard
All logic in the 802.11 receiver FPGA core is clocked at 160MHz and supports a maximum bandwidth of 40MHz (clock rate = 4x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the Rx pipeline.
The PHY receiver also implements the 1Mbps DSSS rate specified in the original 802.11 standard (section 16.2 of the 802.11-2012 standard). This receiver allows reception of management frames transmitted by 802.11 devices at 1Mbps. These transmissions are common in deployments of 802.11 hardware at 2.4GHz. For example, Beacon and Probe Request frames are frequently transmitted at 1Mbps by commercial devices. The basic STA/AP association handshake requires reception of these frames. The 802.11 Reference Design does not implement a DSSS transmitter, as modern 802.11 devices are able to receive management frames at higher rates (including 6Mbps, the lowest OFDM rate, which is commonly used for management frames at 5GHz).
The architecture of the 802.11 transmitter FPGA core is illustrated below. The source model is in the repository: ReferenceDesigns/w3_802.11/sysgen/wlan_phy_tx_pmd.
- Rate/Length Decode: the length and modulation/coding rates are stored in the first 3 bytes of the packet, part of the 802.11 SIGNAl field. The Tx core uses these values to configure the relevant blocks per packet.
- Scrambling: payload bits are scrambled to avoid long runs of constant values
- Encoding: payload bits are encoded by a standard 1/2 rate convolutional encoder and optionally punctured to rates 2/3 or 3/4, depending on the selected coding rate
- Interleaving: coded bits are interleaved in blocks along OFDM symbol boundaries
- Modulation: the coded bits are mapped on to complex values using the selected modulation scheme. The modulated symbols are then mapped on to the data-bearing subcarriers
- Pilot Insertion: four pilot tones, represented by BPSK symbols with scrambled signs, are mapped onto the dedicated subcarriers in each OFDM symbol
- IFFT: the IFFT translates 64 frequency domain samples into 64 time domain samples. A 16-sample cyclic prefix is added by repeating the last 16 IFFT output samples for each OFDM symbol
- Preamble Insertion: the standard 320-sample preamble is prepended to the IFFT output
- Antenna Selection: the complete waveform is finally transmitted via the selected RF interface
All logic in the 802.11 transmitter FPGA core is clocked at 160MHz and supports a maximum bandwidth of 40MHz (clock rate = 4x max sample rate). Smaller bandwidths are supported by reducing the duty cycle of the sample_valid signal at the input to the sample FIFO at the RF interface ports.