Changes between Version 18 and Version 19 of 802.11/ResourceUsage
- Timestamp:
- Jan 14, 2015, 3:01:53 PM (9 years ago)
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802.11/ResourceUsage
v18 v19 5 5 [[TracNav(802.11/TOC)]] 6 6 7 = 802.11 Reference Design v1. 0: Resource Usage =7 = 802.11 Reference Design v1.2: Resource Usage = 8 8 9 9 The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. … … 13 13 14 14 ||= Resource =||= Used =|| 15 || Slice Registers || 6 6,702out of 301,440 (22%) ||16 || LUTs || 61, 499out of 150,720 (40%) ||15 || Slice Registers || 67,081 out of 301,440 (22%) || 16 || LUTs || 61,791 out of 150,720 (40%) || 17 17 || Block RAMs (see note 1) || 228 of 416 (59%) || 18 18 || DSP48 (multipliers) || 155 of 768 (20%) || … … 42 42 Target Speed : -2 43 43 Mapper Version : virtex6 -- $Revision: 1.55 $ 44 Mapped Date : Tue Jan 13 10:31:48 2015 44 45 45 46 Design Summary … … 48 49 Number of warnings: 305 49 50 Slice Logic Utilization: 50 Number of Slice Registers: 6 6,702out of 301,440 22%51 Number used as Flip Flops: 66, 54551 Number of Slice Registers: 67,081 out of 301,440 22% 52 Number used as Flip Flops: 66,924 52 53 Number used as Latches: 4 53 54 Number used as Latch-thrus: 0 54 55 Number used as AND/OR logics: 153 55 Number of Slice LUTs: 61, 499out of 150,720 40%56 Number used as logic: 51, 449out of 150,720 34%57 Number using O6 output only: 40,0 2258 Number using O5 output only: 1,2 5459 Number using O5 and O6: 10,1 7356 Number of Slice LUTs: 61,791 out of 150,720 40% 57 Number used as logic: 51,531 out of 150,720 34% 58 Number using O6 output only: 40,055 59 Number using O5 output only: 1,278 60 Number using O5 and O6: 10,198 60 61 Number used as ROM: 0 61 62 Number used as Memory: 6,926 out of 58,400 11% … … 69 70 Number using O5 and O6: 4 70 71 Number used as Shift Register: 4,543 71 Number using O6 output only: 4,34 572 Number using O5 output only: 1 972 Number using O6 output only: 4,346 73 Number using O5 output only: 18 73 74 Number using O5 and O6: 179 74 Number used exclusively as route-thrus: 3, 12475 Number with same-slice register load: 2,87676 Number with same-slice carry load: 23 075 Number used exclusively as route-thrus: 3,334 76 Number with same-slice register load: 3,079 77 Number with same-slice carry load: 237 77 78 Number with other load: 18 78 79 79 80 Slice Logic Distribution: 80 Number of occupied Slices: 25, 805 out of 37,680 68%81 Number of LUT Flip Flop pairs used: 79, 88782 Number with an unused Flip Flop: 2 1,011 out of 79,887 26%83 Number with an unused LUT: 1 8,388 out of 79,887 23%84 Number of fully used LUT-FF pairs: 4 0,488 out of 79,887 50%85 Number of unique control sets: 2,4 0281 Number of occupied Slices: 25,376 out of 37,680 67% 82 Number of LUT Flip Flop pairs used: 79,591 83 Number with an unused Flip Flop: 20,623 out of 79,591 25% 84 Number with an unused LUT: 17,800 out of 79,591 22% 85 Number of fully used LUT-FF pairs: 41,168 out of 79,591 51% 86 Number of unique control sets: 2,461 86 87 Number of slice register sites lost 87 to control set restrictions: 9, 073out of 301,440 3%88 to control set restrictions: 9,222 out of 301,440 3% 88 89 89 90 A LUT Flip Flop pair for this architecture represents one LUT paired with
