802.11 Reference Design v1.7.8: Resource Usage
The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below.
FPGA Resources
The table below summarizes the FPGA resource usage for the current version of the 802.11 Reference Design.
| Resource | Used |
|---|---|
| Slice Registers | 80,472 out of 301,440 (26%) |
| LUTs | 71,243 out of 150,720 (47%) |
| Block RAMs (see note 1) | 216 of 416 (52%) |
| DSP48 (multipliers) | 194 of 768 (23%) |
| MMCM_ADV | 3 of 12 (25%) |
| Ethernet MAC | 2 of 4 (50%) |
| IOBs (see note 2) | 354 of 600 (58%) |
- Note 1: the ISE MAP reports utilization of RAMB36E1 and RAMB18E1 separately, even though these represent overlapping resources in the FPGA (each RAMB36E1 can be used as 2 RAMB18E1). The block RAM usage above lists the total number of RAMB36E1 primitives in the FPGA and num(RAMB36E1) + ceil(num(RAMB18E1)/2) as the number used. See the MAP report below for more details.
- Note 2: the IOB count includes all IOBs used by the design, not just the RF interfaces. Many of these pins are used for the DDR3 memory interface, Ethernet interfaces, user I/O, etc.
MAP Report
The resource usage section of the MAP report of the 802.11 Reference Design is copied below.
You can find the full MAP report in the implementation/system_map.mrp file in your local copy of the 802.11 Reference Design XPS project.
Release 14.4 Map P.49d (nt64)
Xilinx Mapping Report File for Design 'system'
Design Information
------------------
Command Line : map -mt 2 -o system_map.ncd -w -pr b -ol high -t 13 -register_duplication on -logic_opt on -timing
-detail system.ngd system.pcf
Target Device : xc6vlx240t
Target Package : ff1156
Target Speed : -2
Mapper Version : virtex6 -- $Revision: 1.55 $
Design Summary
--------------
Number of errors: 0
Number of warnings: 352
Slice Logic Utilization:
Number of Slice Registers: 80,472 out of 301,440 26%
Number used as Flip Flops: 80,311
Number used as Latches: 3
Number used as Latch-thrus: 0
Number used as AND/OR logics: 158
Number of Slice LUTs: 71,243 out of 150,720 47%
Number used as logic: 58,208 out of 150,720 38%
Number using O6 output only: 44,095
Number using O5 output only: 1,483
Number using O5 and O6: 12,630
Number used as ROM: 0
Number used as Memory: 8,176 out of 58,400 14%
Number used as Dual Port RAM: 2,522
Number using O6 output only: 1,546
Number using O5 output only: 27
Number using O5 and O6: 949
Number used as Single Port RAM: 31
Number using O6 output only: 19
Number using O5 output only: 0
Number using O5 and O6: 12
Number used as Shift Register: 5,623
Number using O6 output only: 4,910
Number using O5 output only: 18
Number using O5 and O6: 695
Number used exclusively as route-thrus: 4,859
Number with same-slice register load: 3,889
Number with same-slice carry load: 495
Number with other load: 475
Slice Logic Distribution:
Number of occupied Slices: 28,639 out of 37,680 76%
Number of LUT Flip Flop pairs used: 91,784
Number with an unused Flip Flop: 22,037 out of 91,784 24%
Number with an unused LUT: 20,541 out of 91,784 22%
Number of fully used LUT-FF pairs: 49,206 out of 91,784 53%
Number of unique control sets: 2,787
Number of slice register sites lost
to control set restrictions: 10,366 out of 301,440 3%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 354 out of 600 59%
Number of LOCed IOBs: 354 out of 354 100%
IOB Flip Flops: 105
IOB Master Pads: 10
IOB Slave Pads: 10
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 199 out of 416 47%
Number using RAMB36E1 only: 199
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 34 out of 832 4%
Number using RAMB18E1 only: 34
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 8 out of 32 25%
Number used as BUFGs: 8
Number used as BUFGCTRLs: 0
Number of ILOGICE1/ISERDESE1s: 108 out of 720 15%
Number used as ILOGICE1s: 43
Number used as ISERDESE1s: 65
Number of OLOGICE1/OSERDESE1s: 187 out of 720 25%
Number used as OLOGICE1s: 62
Number used as OSERDESE1s: 125
Number of BSCANs: 1 out of 4 25%
Number of BUFHCEs: 0 out of 144 0%
Number of BUFIODQSs: 10 out of 72 13%
Number of BUFRs: 5 out of 36 13%
Number of LOCed BUFRs: 2 out of 5 40%
Number of CAPTUREs: 0 out of 1 0%
Number of DSP48E1s: 194 out of 768 25%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of GTXE1s: 0 out of 20 0%
Number of IBUFDS_GTXE1s: 0 out of 12 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 5 out of 18 27%
Number of IODELAYE1s: 112 out of 720 15%
Number of LOCed IODELAYE1s: 10 out of 112 8%
Number of MMCM_ADVs: 3 out of 12 25%
Number of PCIE_2_0s: 0 out of 2 0%
Number of STARTUPs: 1 out of 1 100%
Number of SYSMONs: 1 out of 1 100%
Number of TEMAC_SINGLEs: 2 out of 4 50%
Number of RPM macros: 5
Average Fanout of Non-Clock Nets: 3.49
CPU RAM Resources
The following gives the amount of space used by each SDK Software project when compiled in SDK 14.4. After a project is compiled, these values can be found in the <Project Name>.elf.size file in the SDK_Workspace folder.
| Project | gcc Options | Instructions .text bytes | Data .data + .bss bytes | Total Size bytes |
|---|---|---|---|---|
| AP | -O3 -g | 225028 | 67996 | 293024 |
| STA | -O3 -g | 217820 | 68076 | 285896 |
| IBSS | -O3 -g | 216160 | 67992 | 284152 |
| DCF | -O3 -g | 78997 | 3496 | 82493 |
| NOMAC | -O3 -g | 51445 | 3216 | 54661 |
Last modified 6 years ago
Last modified on Nov 30, 2018, 9:57:15 AM
