Changes between Version 25 and Version 26 of 802.11/ResourceUsage


Ignore:
Timestamp:
Jul 1, 2016, 2:37:44 PM (8 years ago)
Author:
murphpo
Comment:

--

Legend:

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  • 802.11/ResourceUsage

    v25 v26  
    1313
    1414||=  Resource  =||=  Used  =||
    15 || Slice Registers  || 77,280 out of 301,440 (25%) ||
    16 || LUTs  || 70,086 out of 150,720 (46%) ||
    17 || Block RAMs (see note 1)  || 258 of 416 (62%) ||
    18 || DSP48 (multipliers)  || 170 of 768 (22%) ||
     15|| Slice Registers  || 79,221 out of 301,440 (26%) ||
     16|| LUTs  || 71,193 out of 150,720 (47%) ||
     17|| Block RAMs (see note 1)  || 261 of 416 (63%) ||
     18|| DSP48 (multipliers)  || 182 of 768 (23%) ||
    1919|| MMCM_ADV  || 3 of 12 (25%) ||
    2020|| Ethernet MAC  || 2 of 4 (50%) ||
     
    3737------------------
    3838Command Line   : map -mt 4 -o system_map.ncd -w -pr b -ol high -t 13 -register_duplication on -timing -detail system.ngd
    39 
    4039system.pcf
    4140Target Device  : xc6vlx240t
     
    4342Target Speed   : -2
    4443Mapper Version : virtex6 -- $Revision: 1.55 $
    45 Mapped Date    : Sun Mar 06 16:30:27 2016
    4644
    4745Design Summary
    4846--------------
    4947Number of errors:      0
    50 Number of warnings:  344
     48Number of warnings:  352
    5149Slice Logic Utilization:
    52   Number of Slice Registers:                77,280 out of 301,440   25%
    53     Number used as Flip Flops:              77,112
     50  Number of Slice Registers:                79,221 out of 301,440   26%
     51    Number used as Flip Flops:              79,059
    5452    Number used as Latches:                      4
    5553    Number used as Latch-thrus:                  0
    56     Number used as AND/OR logics:              164
    57   Number of Slice LUTs:                     70,086 out of 150,720   46%
    58     Number used as logic:                   57,505 out of 150,720   38%
    59       Number using O6 output only:          43,946
    60       Number using O5 output only:           1,464
    61       Number using O5 and O6:               12,095
     54    Number used as AND/OR logics:              158
     55  Number of Slice LUTs:                     71,193 out of 150,720   47%
     56    Number used as logic:                   58,524 out of 150,720   38%
     57      Number using O6 output only:          44,685
     58      Number using O5 output only:           1,486
     59      Number using O5 and O6:               12,353
    6260      Number used as ROM:                        0
    63     Number used as Memory:                   7,590 out of  58,400   12%
     61    Number used as Memory:                   7,870 out of  58,400   13%
    6462      Number used as Dual Port RAM:          2,522
    6563        Number using O6 output only:         1,546
     
    7068        Number using O5 output only:             0
    7169        Number using O5 and O6:                 12
    72       Number used as Shift Register:         5,037
    73         Number using O6 output only:         4,776
    74         Number using O5 output only:            17
    75         Number using O5 and O6:                244
    76     Number used exclusively as route-thrus:  4,991
    77       Number with same-slice register load:  4,210
    78       Number with same-slice carry load:       316
    79       Number with other load:                  465
     70      Number used as Shift Register:         5,317
     71        Number using O6 output only:         4,877
     72        Number using O5 output only:            18
     73        Number using O5 and O6:                422
     74    Number used exclusively as route-thrus:  4,799
     75      Number with same-slice register load:  3,832
     76      Number with same-slice carry load:       497
     77      Number with other load:                  470
    8078
    8179Slice Logic Distribution:
    82   Number of occupied Slices:                28,289 out of  37,680   75%
    83   Number of LUT Flip Flop pairs used:       89,396
    84     Number with an unused Flip Flop:        22,638 out of  89,396   25%
    85     Number with an unused LUT:              19,310 out of  89,396   21%
    86     Number of fully used LUT-FF pairs:      47,448 out of  89,396   53%
    87     Number of unique control sets:           2,850
     80  Number of occupied Slices:                28,957 out of  37,680   76%
     81  Number of LUT Flip Flop pairs used:       91,640
     82    Number with an unused Flip Flop:        22,592 out of  91,640   24%
     83    Number with an unused LUT:              20,447 out of  91,640   22%
     84    Number of fully used LUT-FF pairs:      48,601 out of  91,640   53%
     85    Number of unique control sets:           2,849
    8886    Number of slice register sites lost
    89       to control set restrictions:          10,633 out of 301,440    3%
     87      to control set restrictions:          10,676 out of 301,440    3%
    9088
    9189  A LUT Flip Flop pair for this architecture represents one LUT paired with
     
    105103
    106104Specific Feature Utilization:
    107   Number of RAMB36E1/FIFO36E1s:                240 out of     416   57%
    108     Number using RAMB36E1 only:                240
     105  Number of RAMB36E1/FIFO36E1s:                243 out of     416   58%
     106    Number using RAMB36E1 only:                243
    109107    Number using FIFO36E1 only:                  0
    110   Number of RAMB18E1/FIFO18E1s:                 35 out of     832    4%
    111     Number using RAMB18E1 only:                 35
     108  Number of RAMB18E1/FIFO18E1s:                 36 out of     832    4%
     109    Number using RAMB18E1 only:                 36
    112110    Number using FIFO18E1 only:                  0
    113111  Number of BUFG/BUFGCTRLs:                      9 out of      32   28%
     
    126124    Number of LOCed BUFRs:                       2 out of       5   40%
    127125  Number of CAPTUREs:                            0 out of       1    0%
    128   Number of DSP48E1s:                          170 out of     768   22%
     126  Number of DSP48E1s:                          182 out of     768   23%
    129127  Number of EFUSE_USRs:                          0 out of       1    0%
    130128  Number of FRAME_ECCs:                          0 out of       1    0%
     
    142140
    143141  Number of RPM macros:           15
    144 Average Fanout of Non-Clock Nets:                3.58
     142Average Fanout of Non-Clock Nets:                3.55
    145143}}}
    146144