Changes between Version 31 and Version 32 of 802.11/ResourceUsage
- Timestamp:
- Jan 13, 2017, 12:48:11 PM (7 years ago)
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802.11/ResourceUsage
v31 v32 5 5 [[TracNav(802.11/TOC)]] 6 6 7 = 802.11 Reference Design v1. 5.3: Resource Usage =7 = 802.11 Reference Design v1.6.0: Resource Usage = 8 8 9 9 The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. … … 13 13 14 14 ||= Resource =||= Used =|| 15 || Slice Registers || 79, 340out of 301,440 (26%) ||16 || LUTs || 71, 142 out of 150,720 (47%) ||17 || Block RAMs (see note 1) || 2 61 of 416 (63%) ||15 || Slice Registers || 79,819 out of 301,440 (26%) || 16 || LUTs || 71,422 out of 150,720 (47%) || 17 || Block RAMs (see note 1) || 253 of 416 (60%) || 18 18 || DSP48 (multipliers) || 182 of 768 (23%) || 19 19 || MMCM_ADV || 3 of 12 (25%) || … … 48 48 Number of warnings: 352 49 49 Slice Logic Utilization: 50 Number of Slice Registers: 79, 340out of 301,440 26%51 Number used as Flip Flops: 79, 17850 Number of Slice Registers: 79,819 out of 301,440 26% 51 Number used as Flip Flops: 79,657 52 52 Number used as Latches: 4 53 53 Number used as Latch-thrus: 0 54 54 Number used as AND/OR logics: 158 55 Number of Slice LUTs: 71, 142 out of 150,720 47%56 Number used as logic: 58, 464out of 150,720 38%57 Number using O6 output only: 44, 53358 Number using O5 output only: 1,4 8259 Number using O5 and O6: 12, 44955 Number of Slice LUTs: 71,422 out of 150,720 47% 56 Number used as logic: 58,148 out of 150,720 38% 57 Number using O6 output only: 44,295 58 Number using O5 output only: 1,473 59 Number using O5 and O6: 12,380 60 60 Number used as ROM: 0 61 Number used as Memory: 7, 913out of 58,400 13%61 Number used as Memory: 7,890 out of 58,400 13% 62 62 Number used as Dual Port RAM: 2,522 63 63 Number using O6 output only: 1,546 … … 68 68 Number using O5 output only: 0 69 69 Number using O5 and O6: 12 70 Number used as Shift Register: 5,3 6071 Number using O6 output only: 4, 92070 Number used as Shift Register: 5,337 71 Number using O6 output only: 4,897 72 72 Number using O5 output only: 17 73 73 Number using O5 and O6: 423 74 Number used exclusively as route-thrus: 4,76575 Number with same-slice register load: 3,79276 Number with same-slice carry load: 50777 Number with other load: 4 6674 Number used exclusively as route-thrus: 5,384 75 Number with same-slice register load: 4,418 76 Number with same-slice carry load: 493 77 Number with other load: 473 78 78 79 79 Slice Logic Distribution: 80 Number of occupied Slices: 28, 829 out of 37,680 76%81 Number of LUT Flip Flop pairs used: 91, 27682 Number with an unused Flip Flop: 22, 148 out of 91,27624%83 Number with an unused LUT: 20,134 out of 91,276 22%84 Number of fully used LUT-FF pairs: 4 8,994 out of 91,27653%85 Number of unique control sets: 2,8 5180 Number of occupied Slices: 28,620 out of 37,680 75% 81 Number of LUT Flip Flop pairs used: 91,113 82 Number with an unused Flip Flop: 22,231 out of 91,113 24% 83 Number with an unused LUT: 19,691 out of 91,113 21% 84 Number of fully used LUT-FF pairs: 49,191 out of 91,113 53% 85 Number of unique control sets: 2,828 86 86 Number of slice register sites lost 87 to control set restrictions: 10, 681out of 301,440 3%87 to control set restrictions: 10,593 out of 301,440 3% 88 88 89 89 A LUT Flip Flop pair for this architecture represents one LUT paired with … … 103 103 104 104 Specific Feature Utilization: 105 Number of RAMB36E1/FIFO36E1s: 2 43 out of 416 58%106 Number using RAMB36E1 only: 2 43105 Number of RAMB36E1/FIFO36E1s: 235 out of 416 56% 106 Number using RAMB36E1 only: 235 107 107 Number using FIFO36E1 only: 0 108 108 Number of RAMB18E1/FIFO18E1s: 36 out of 832 4% … … 140 140 141 141 Number of RPM macros: 15 142 Average Fanout of Non-Clock Nets: 3.5 5142 Average Fanout of Non-Clock Nets: 3.53 143 143 }}} 144 144
