Changes between Version 40 and Version 41 of 802.11/ResourceUsage
- Timestamp:
- Dec 6, 2017, 3:45:15 PM (6 years ago)
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802.11/ResourceUsage
v40 v41 5 5 [[TracNav(802.11/TOC)]] 6 6 7 = 802.11 Reference Design v1.7. 2: Resource Usage =7 = 802.11 Reference Design v1.7.4: Resource Usage = 8 8 9 9 The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. … … 13 13 14 14 ||= Resource =||= Used =|| 15 || Slice Registers || 79,910 out of 301,440 (26%) ||16 || LUTs || 71, 180out of 150,720 (47%) ||17 || Block RAMs (see note 1) || 2 69of 416 (65%) ||18 || DSP48 (multipliers) || 1 82of 768 (23%) ||15 || Slice Registers || 80,560 out of 301,440 (26%) || 16 || LUTs || 71,036 out of 150,720 (47%) || 17 || Block RAMs (see note 1) || 272 of 416 (65%) || 18 || DSP48 (multipliers) || 194 of 768 (23%) || 19 19 || MMCM_ADV || 3 of 12 (25%) || 20 20 || Ethernet MAC || 2 of 4 (50%) || … … 31 31 32 32 {{{ 33 ap P.49d (nt64)33 Release 14.4 Map P.49d (nt64) 34 34 Xilinx Mapping Report File for Design 'system' 35 35 … … 48 48 Number of warnings: 354 49 49 Slice Logic Utilization: 50 Number of Slice Registers: 79,910 out of 301,440 26%51 Number used as Flip Flops: 79,74850 Number of Slice Registers: 80,560 out of 301,440 26% 51 Number used as Flip Flops: 80,398 52 52 Number used as Latches: 4 53 53 Number used as Latch-thrus: 0 54 54 Number used as AND/OR logics: 158 55 Number of Slice LUTs: 71, 180out of 150,720 47%56 Number used as logic: 5 8,158out of 150,720 38%57 Number using O6 output only: 4 4,28558 Number using O5 output only: 1, 48059 Number using O5 and O6: 12, 39355 Number of Slice LUTs: 71,036 out of 150,720 47% 56 Number used as logic: 57,520 out of 150,720 38% 57 Number using O6 output only: 43,462 58 Number using O5 output only: 1,544 59 Number using O5 and O6: 12,514 60 60 Number used as ROM: 0 61 Number used as Memory: 7,931 out of 58,400 13%61 Number used as Memory: 8,349 out of 58,400 14% 62 62 Number used as Dual Port RAM: 2,522 63 63 Number using O6 output only: 1,546 … … 68 68 Number using O5 output only: 0 69 69 Number using O5 and O6: 12 70 Number used as Shift Register: 5, 37871 Number using O6 output only: 4,93672 Number using O5 output only: 1 973 Number using O5 and O6: 42374 Number used exclusively as route-thrus: 5, 09175 Number with same-slice register load: 4, 14076 Number with same-slice carry load: 4 7777 Number with other load: 47 470 Number used as Shift Register: 5,796 71 Number using O6 output only: 5,084 72 Number using O5 output only: 17 73 Number using O5 and O6: 695 74 Number used exclusively as route-thrus: 5,167 75 Number with same-slice register load: 4,205 76 Number with same-slice carry load: 489 77 Number with other load: 473 78 78 79 79 Slice Logic Distribution: 80 Number of occupied Slices: 28,6 70 out of 37,680 76%81 Number of LUT Flip Flop pairs used: 91, 24082 Number with an unused Flip Flop: 21, 979 out of 91,240 24%83 Number with an unused LUT: 20, 060 out of 91,240 21%84 Number of fully used LUT-FF pairs: 49, 201 out of 91,24053%85 Number of unique control sets: 2,8 1680 Number of occupied Slices: 28,613 out of 37,680 75% 81 Number of LUT Flip Flop pairs used: 91,549 82 Number with an unused Flip Flop: 21,879 out of 91,549 23% 83 Number with an unused LUT: 20,513 out of 91,549 22% 84 Number of fully used LUT-FF pairs: 49,157 out of 91,549 53% 85 Number of unique control sets: 2,830 86 86 Number of slice register sites lost 87 to control set restrictions: 10,5 65out of 301,440 3%87 to control set restrictions: 10,577 out of 301,440 3% 88 88 89 89 A LUT Flip Flop pair for this architecture represents one LUT paired with … … 103 103 104 104 Specific Feature Utilization: 105 Number of RAMB36E1/FIFO36E1s: 25 1 out of 416 60%106 Number using RAMB36E1 only: 25 1105 Number of RAMB36E1/FIFO36E1s: 254 out of 416 61% 106 Number using RAMB36E1 only: 254 107 107 Number using FIFO36E1 only: 0 108 Number of RAMB18E1/FIFO18E1s: 3 6out of 832 4%109 Number using RAMB18E1 only: 3 6108 Number of RAMB18E1/FIFO18E1s: 35 out of 832 4% 109 Number using RAMB18E1 only: 35 110 110 Number using FIFO18E1 only: 0 111 111 Number of BUFG/BUFGCTRLs: 9 out of 32 28% … … 124 124 Number of LOCed BUFRs: 2 out of 5 40% 125 125 Number of CAPTUREs: 0 out of 1 0% 126 Number of DSP48E1s: 1 82 out of 768 23%126 Number of DSP48E1s: 194 out of 768 25% 127 127 Number of EFUSE_USRs: 0 out of 1 0% 128 128 Number of FRAME_ECCs: 0 out of 1 0% … … 140 140 141 141 Number of RPM macros: 15 142 Average Fanout of Non-Clock Nets: 3.5 4142 Average Fanout of Non-Clock Nets: 3.50 143 143 }}} 144 144
