Changes between Version 45 and Version 46 of 802.11/ResourceUsage
- Timestamp:
- Nov 30, 2018, 9:57:15 AM (5 years ago)
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802.11/ResourceUsage
v45 v46 1 {{{#!comment2 [[Include(wiki:802.11/beta-note)]]3 }}}4 5 1 [[TracNav(802.11/TOC)]] 6 2 7 = 802.11 Reference Design v1.7. 7: Resource Usage =3 = 802.11 Reference Design v1.7.8: Resource Usage = 8 4 9 5 The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. … … 13 9 14 10 ||= Resource =||= Used =|| 15 || Slice Registers || 80, 597out of 301,440 (26%) ||16 || LUTs || 71, 768out of 150,720 (47%) ||17 || Block RAMs (see note 1) || 2 72 of 416 (65%) ||11 || Slice Registers || 80,472 out of 301,440 (26%) || 12 || LUTs || 71,243 out of 150,720 (47%) || 13 || Block RAMs (see note 1) || 216 of 416 (52%) || 18 14 || DSP48 (multipliers) || 194 of 768 (23%) || 19 15 || MMCM_ADV || 3 of 12 (25%) || … … 36 32 Design Information 37 33 ------------------ 38 Command Line : map -mt 4 -o system_map.ncd -w -pr b -ol high -t 13 -register_duplication on -timing -detail system.ngd39 system.pcf34 Command Line : map -mt 2 -o system_map.ncd -w -pr b -ol high -t 13 -register_duplication on -logic_opt on -timing 35 -detail system.ngd system.pcf 40 36 Target Device : xc6vlx240t 41 37 Target Package : ff1156 … … 46 42 -------------- 47 43 Number of errors: 0 48 Number of warnings: 35 444 Number of warnings: 352 49 45 Slice Logic Utilization: 50 Number of Slice Registers: 80, 597out of 301,440 26%51 Number used as Flip Flops: 80, 43552 Number used as Latches: 446 Number of Slice Registers: 80,472 out of 301,440 26% 47 Number used as Flip Flops: 80,311 48 Number used as Latches: 3 53 49 Number used as Latch-thrus: 0 54 50 Number used as AND/OR logics: 158 55 Number of Slice LUTs: 71, 768out of 150,720 47%56 Number used as logic: 5 7,549out of 150,720 38%57 Number using O6 output only: 4 3,48958 Number using O5 output only: 1, 54459 Number using O5 and O6: 12, 51651 Number of Slice LUTs: 71,243 out of 150,720 47% 52 Number used as logic: 58,208 out of 150,720 38% 53 Number using O6 output only: 44,095 54 Number using O5 output only: 1,483 55 Number using O5 and O6: 12,630 60 56 Number used as ROM: 0 61 Number used as Memory: 8, 350out of 58,400 14%57 Number used as Memory: 8,176 out of 58,400 14% 62 58 Number used as Dual Port RAM: 2,522 63 59 Number using O6 output only: 1,546 … … 68 64 Number using O5 output only: 0 69 65 Number using O5 and O6: 12 70 Number used as Shift Register: 5, 79771 Number using O6 output only: 5,08572 Number using O5 output only: 1 766 Number used as Shift Register: 5,623 67 Number using O6 output only: 4,910 68 Number using O5 output only: 18 73 69 Number using O5 and O6: 695 74 Number used exclusively as route-thrus: 5,86975 Number with same-slice register load: 4,88776 Number with same-slice carry load: 50477 Number with other load: 47 870 Number used exclusively as route-thrus: 4,859 71 Number with same-slice register load: 3,889 72 Number with same-slice carry load: 495 73 Number with other load: 475 78 74 79 75 Slice Logic Distribution: 80 Number of occupied Slices: 28, 383 out of 37,680 75%81 Number of LUT Flip Flop pairs used: 9 0,84282 Number with an unused Flip Flop: 22,0 64 out of 90,84224%83 Number with an unused LUT: 19,074 out of 90,842 20%84 Number of fully used LUT-FF pairs: 49, 704 out of 90,842 54%85 Number of unique control sets: 2, 86176 Number of occupied Slices: 28,639 out of 37,680 76% 77 Number of LUT Flip Flop pairs used: 91,784 78 Number with an unused Flip Flop: 22,037 out of 91,784 24% 79 Number with an unused LUT: 20,541 out of 91,784 22% 80 Number of fully used LUT-FF pairs: 49,206 out of 91,784 53% 81 Number of unique control sets: 2,787 86 82 Number of slice register sites lost 87 to control set restrictions: 10, 651out of 301,440 3%83 to control set restrictions: 10,366 out of 301,440 3% 88 84 89 85 A LUT Flip Flop pair for this architecture represents one LUT paired with … … 103 99 104 100 Specific Feature Utilization: 105 Number of RAMB36E1/FIFO36E1s: 254 out of 416 61%106 Number using RAMB36E1 only: 254101 Number of RAMB36E1/FIFO36E1s: 199 out of 416 47% 102 Number using RAMB36E1 only: 199 107 103 Number using FIFO36E1 only: 0 108 Number of RAMB18E1/FIFO18E1s: 3 5out of 832 4%109 Number using RAMB18E1 only: 3 5104 Number of RAMB18E1/FIFO18E1s: 34 out of 832 4% 105 Number using RAMB18E1 only: 34 110 106 Number using FIFO18E1 only: 0 111 Number of BUFG/BUFGCTRLs: 9 out of 32 28%112 Number used as BUFGs: 9107 Number of BUFG/BUFGCTRLs: 8 out of 32 25% 108 Number used as BUFGs: 8 113 109 Number used as BUFGCTRLs: 0 114 110 Number of ILOGICE1/ISERDESE1s: 108 out of 720 15% … … 118 114 Number used as OLOGICE1s: 62 119 115 Number used as OSERDESE1s: 125 120 Number of BSCANs: 2 out of 4 50%116 Number of BSCANs: 1 out of 4 25% 121 117 Number of BUFHCEs: 0 out of 144 0% 122 118 Number of BUFIODQSs: 10 out of 72 13% … … 139 135 Number of TEMAC_SINGLEs: 2 out of 4 50% 140 136 141 Number of RPM macros: 15137 Number of RPM macros: 5 142 138 Average Fanout of Non-Clock Nets: 3.49 143 139 }}}
