Changes between Version 45 and Version 46 of 802.11/ResourceUsage


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Timestamp:
Nov 30, 2018, 9:57:15 AM (15 months ago)
Author:
murphpo
Comment:

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  • 802.11/ResourceUsage

    v45 v46  
    1 {{{#!comment
    2 [[Include(wiki:802.11/beta-note)]]
    3 }}}
    4 
    51[[TracNav(802.11/TOC)]]
    62
    7 = 802.11 Reference Design v1.7.7: Resource Usage =
     3= 802.11 Reference Design v1.7.8: Resource Usage =
    84
    95The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below.
     
    139
    1410||=  Resource  =||=  Used  =||
    15 || Slice Registers  || 80,597 out of 301,440 (26%) ||
    16 || LUTs  || 71,768 out of 150,720 (47%) ||
    17 || Block RAMs (see note 1)  || 272 of 416 (65%) ||
     11|| Slice Registers  || 80,472 out of 301,440 (26%) ||
     12|| LUTs  || 71,243 out of 150,720 (47%) ||
     13|| Block RAMs (see note 1)  || 216 of 416 (52%) ||
    1814|| DSP48 (multipliers)  || 194 of 768 (23%) ||
    1915|| MMCM_ADV  || 3 of 12 (25%) ||
     
    3632Design Information
    3733------------------
    38 Command Line   : map -mt 4 -o system_map.ncd -w -pr b -ol high -t 13 -register_duplication on -timing -detail system.ngd
    39 system.pcf
     34Command Line   : map -mt 2 -o system_map.ncd -w -pr b -ol high -t 13 -register_duplication on -logic_opt on -timing
     35-detail system.ngd system.pcf
    4036Target Device  : xc6vlx240t
    4137Target Package : ff1156
     
    4642--------------
    4743Number of errors:      0
    48 Number of warnings:  354
     44Number of warnings:  352
    4945Slice Logic Utilization:
    50   Number of Slice Registers:                80,597 out of 301,440   26%
    51     Number used as Flip Flops:              80,435
    52     Number used as Latches:                      4
     46  Number of Slice Registers:                80,472 out of 301,440   26%
     47    Number used as Flip Flops:              80,311
     48    Number used as Latches:                      3
    5349    Number used as Latch-thrus:                  0
    5450    Number used as AND/OR logics:              158
    55   Number of Slice LUTs:                     71,768 out of 150,720   47%
    56     Number used as logic:                   57,549 out of 150,720   38%
    57       Number using O6 output only:          43,489
    58       Number using O5 output only:           1,544
    59       Number using O5 and O6:               12,516
     51  Number of Slice LUTs:                     71,243 out of 150,720   47%
     52    Number used as logic:                   58,208 out of 150,720   38%
     53      Number using O6 output only:          44,095
     54      Number using O5 output only:           1,483
     55      Number using O5 and O6:               12,630
    6056      Number used as ROM:                        0
    61     Number used as Memory:                   8,350 out of  58,400   14%
     57    Number used as Memory:                   8,176 out of  58,400   14%
    6258      Number used as Dual Port RAM:          2,522
    6359        Number using O6 output only:         1,546
     
    6864        Number using O5 output only:             0
    6965        Number using O5 and O6:                 12
    70       Number used as Shift Register:         5,797
    71         Number using O6 output only:         5,085
    72         Number using O5 output only:            17
     66      Number used as Shift Register:         5,623
     67        Number using O6 output only:         4,910
     68        Number using O5 output only:            18
    7369        Number using O5 and O6:                695
    74     Number used exclusively as route-thrus:  5,869
    75       Number with same-slice register load:  4,887
    76       Number with same-slice carry load:       504
    77       Number with other load:                  478
     70    Number used exclusively as route-thrus:  4,859
     71      Number with same-slice register load:  3,889
     72      Number with same-slice carry load:       495
     73      Number with other load:                  475
    7874
    7975Slice Logic Distribution:
    80   Number of occupied Slices:                28,383 out of  37,680   75%
    81   Number of LUT Flip Flop pairs used:       90,842
    82     Number with an unused Flip Flop:        22,064 out of  90,842   24%
    83     Number with an unused LUT:              19,074 out of  90,842   20%
    84     Number of fully used LUT-FF pairs:      49,704 out of  90,842   54%
    85     Number of unique control sets:           2,861
     76  Number of occupied Slices:                28,639 out of  37,680   76%
     77  Number of LUT Flip Flop pairs used:       91,784
     78    Number with an unused Flip Flop:        22,037 out of  91,784   24%
     79    Number with an unused LUT:              20,541 out of  91,784   22%
     80    Number of fully used LUT-FF pairs:      49,206 out of  91,784   53%
     81    Number of unique control sets:           2,787
    8682    Number of slice register sites lost
    87       to control set restrictions:          10,651 out of 301,440    3%
     83      to control set restrictions:          10,366 out of 301,440    3%
    8884
    8985  A LUT Flip Flop pair for this architecture represents one LUT paired with
     
    10399
    104100Specific Feature Utilization:
    105   Number of RAMB36E1/FIFO36E1s:                254 out of     416   61%
    106     Number using RAMB36E1 only:                254
     101  Number of RAMB36E1/FIFO36E1s:                199 out of     416   47%
     102    Number using RAMB36E1 only:                199
    107103    Number using FIFO36E1 only:                  0
    108   Number of RAMB18E1/FIFO18E1s:                 35 out of     832    4%
    109     Number using RAMB18E1 only:                 35
     104  Number of RAMB18E1/FIFO18E1s:                 34 out of     832    4%
     105    Number using RAMB18E1 only:                 34
    110106    Number using FIFO18E1 only:                  0
    111   Number of BUFG/BUFGCTRLs:                      9 out of      32   28%
    112     Number used as BUFGs:                        9
     107  Number of BUFG/BUFGCTRLs:                      8 out of      32   25%
     108    Number used as BUFGs:                        8
    113109    Number used as BUFGCTRLs:                    0
    114110  Number of ILOGICE1/ISERDESE1s:               108 out of     720   15%
     
    118114    Number used as OLOGICE1s:                   62
    119115    Number used as OSERDESE1s:                 125
    120   Number of BSCANs:                              2 out of       4   50%
     116  Number of BSCANs:                              1 out of       4   25%
    121117  Number of BUFHCEs:                             0 out of     144    0%
    122118  Number of BUFIODQSs:                          10 out of      72   13%
     
    139135  Number of TEMAC_SINGLEs:                       2 out of       4   50%
    140136
    141   Number of RPM macros:           15
     137  Number of RPM macros:            5
    142138Average Fanout of Non-Clock Nets:                3.49
    143139}}}