| 50 | When the SDK has successfully compiled the software projects for CPU High and CPU Low, you can use the updated design in hardware. |
| 51 | |
| 52 | The output of the XPS hardware implementation flow is a bitstream named {{{system.bit}}}. This bitstream contains the full hardware design. In this design the initial values of the memory blocks used for instruction/data are all zero. |
| 53 | |
| 54 | The SDK's Program FPGA tool (under the Xilinx Tools menu) implements the process of updating the memory blocks in {{{system.bit}}} with the software binary (the .elf file) generated by the SDK compiler/linker. The output of this flow is a new bistream named {{{download.bit}}}, ready to download to the FPGA. |
| 55 | |
| 56 | The Program FPGA tool requires selection of one software binary per processor in the design. You must select a valid .elf file per CPU. If you select the default bootloop, the corresponding processor will be configured with a "do nothing forever" application, leading to a boot failure of the 802.11 design. |
| 57 | |
| 58 | The image below shows the .elf selections to use the IBSS application in CPU High and DCF MAC in CPU Low: |
| 59 | [[Image(wiki:802.11/files:sdk_program_fpga_elf_selection.png)]] |
| 60 | |
| 61 | After selecting valid .elf files click Program. This will generate the file {{{download.bit}}} in {{{<SDK_Workspace>/Mango_802.11_RefDes_vXXX_hw_platform/}}}. If you have a JTAG cable attached to your PC the tool will also attempt configuring your FPGA with the updated design. If no JTAG cable or FPGA is found, the tool will report "Program FPGA Failed". The {{{download.bit}}} file is still updated in this case. |
| 62 | |
| 63 | If you want to generate a .bin file for use on SD cards, find the updated {{{download.bit}}} file as described above and follow the usual [wiki:howto/SD_Config SD card config] flow. |